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https://github.com/fpganinja/taxi.git
synced 2026-01-18 09:40:18 -08:00
eth: Add APB register interface to US/US+ transceiver wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
@@ -30,6 +30,7 @@ module taxi_gt_rx_reset #
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/*
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* GT
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*/
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input wire logic gt_rxusrclk2,
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output wire logic gt_rx_pd_out,
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output wire logic gt_rx_reset_out,
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input wire logic gt_rx_reset_done_in,
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@@ -94,6 +95,16 @@ gt_status_sync_inst (
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.out({gt_rx_reset_done_sync, gt_rx_pma_reset_done_sync, gt_rx_prgdiv_reset_done_sync, gt_userclk_rx_active_sync, gt_rx_cdr_lock_sync})
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);
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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gt_ctrl_sync_inst (
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.clk(gt_rxusrclk2),
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.in({gt_rx_pd_reg}),
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.out({gt_rx_pd_out})
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);
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wire rx_reset_sync;
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taxi_sync_reset #(
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@@ -119,7 +130,6 @@ logic rx_reset_done_reg = 1'b0;
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assign rx_reset_done_out = rx_reset_done_reg;
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assign gt_rx_pd_out = gt_rx_pd_reg;
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assign gt_rx_reset_out = gt_rx_reset_reg;
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assign gt_rx_pma_reset_out = gt_rx_pma_reset_reg;
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assign gt_rx_dfe_lpm_reset_out = gt_rx_dfe_lpm_reset_reg;
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@@ -28,6 +28,7 @@ module taxi_gt_tx_reset #
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/*
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* GT
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*/
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input wire logic gt_txusrclk2,
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output wire logic gt_tx_pd_out,
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output wire logic gt_tx_reset_out,
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input wire logic gt_tx_reset_done_in,
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@@ -81,6 +82,16 @@ gt_status_sync_inst (
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.out({gt_tx_reset_done_sync, gt_tx_pma_reset_done_sync, gt_tx_prgdiv_reset_done_sync, gt_userclk_tx_active_sync})
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);
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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gt_ctrl_sync_inst (
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.clk(gt_txusrclk2),
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.in({gt_tx_pd_reg}),
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.out({gt_tx_pd_out})
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);
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wire tx_reset_sync;
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taxi_sync_reset #(
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@@ -102,7 +113,6 @@ logic [1:0] state_reg = STATE_RESET;
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logic [CNT_W-1:0] tx_reset_cnt_reg = '0;
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logic tx_reset_done_reg = 1'b0;
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assign gt_tx_pd_out = gt_tx_pd_reg;
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assign gt_tx_reset_out = gt_tx_reset_reg;
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assign gt_tx_pma_reset_out = gt_tx_pma_reset_reg;
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assign gt_tx_pcs_reset_out = gt_tx_pcs_reset_reg;
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