From 5e890bc6cd5a54329f27125afdba75adab63c847 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 20 Aug 2025 06:33:21 -0700
Subject: [PATCH] axis: Add AXI stream tie and null source/sink modules

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 src/axis/rtl/taxi_axis_null_snk.sv | 30 ++++++++++++++
 src/axis/rtl/taxi_axis_null_src.sv | 37 +++++++++++++++++
 src/axis/rtl/taxi_axis_tie.sv      | 64 ++++++++++++++++++++++++++++++
 3 files changed, 131 insertions(+)
 create mode 100644 src/axis/rtl/taxi_axis_null_snk.sv
 create mode 100644 src/axis/rtl/taxi_axis_null_src.sv
 create mode 100644 src/axis/rtl/taxi_axis_tie.sv

diff --git a/src/axis/rtl/taxi_axis_null_snk.sv b/src/axis/rtl/taxi_axis_null_snk.sv
new file mode 100644
index 0000000..127eb60
--- /dev/null
+++ b/src/axis/rtl/taxi_axis_null_snk.sv
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream null sink
+ */
+module taxi_axis_null_snk
+(
+    /*
+     * AXI4-Stream input (sink)
+     */
+    taxi_axis_if.snk  s_axis
+);
+
+assign s_axis.tready = 1'b1;
+
+endmodule
+
+`resetall
diff --git a/src/axis/rtl/taxi_axis_null_src.sv b/src/axis/rtl/taxi_axis_null_src.sv
new file mode 100644
index 0000000..b61268b
--- /dev/null
+++ b/src/axis/rtl/taxi_axis_null_src.sv
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream null source
+ */
+module taxi_axis_null_src
+(
+    /*
+     * AXI4-Stream output (source)
+     */
+    taxi_axis_if.src  m_axis
+);
+
+assign m_axis.tdata  = '0;
+assign m_axis.tkeep  = '1;
+assign m_axis.tstrb  = m_axis.tkeep;
+assign m_axis.tvalid = 1'b0;
+assign m_axis.tlast  = 1'b1;
+assign m_axis.tid    = '0;
+assign m_axis.tdest  = '0;
+assign m_axis.tuser  = '0;
+
+endmodule
+
+`resetall
diff --git a/src/axis/rtl/taxi_axis_tie.sv b/src/axis/rtl/taxi_axis_tie.sv
new file mode 100644
index 0000000..75389e5
--- /dev/null
+++ b/src/axis/rtl/taxi_axis_tie.sv
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream tie
+ */
+module taxi_axis_tie
+(
+    /*
+     * AXI4-Stream input (sink)
+     */
+    taxi_axis_if.snk  s_axis,
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    taxi_axis_if.src  m_axis
+);
+
+// extract parameters
+localparam DATA_W = s_axis.DATA_W;
+localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
+localparam KEEP_W = s_axis.KEEP_W;
+localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
+localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
+localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
+localparam ID_W = s_axis.ID_W;
+localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
+localparam DEST_W = s_axis.DEST_W;
+localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
+localparam USER_W = s_axis.USER_W;
+
+// check configuration
+if (m_axis.DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
+    $fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
+
+assign m_axis.tdata  = s_axis.tdata;
+assign m_axis.tkeep  = KEEP_EN ? s_axis.tkeep : '1;
+assign m_axis.tstrb  = STRB_EN ? s_axis.tstrb : m_axis.tkeep;
+assign m_axis.tvalid = s_axis.tvalid;
+assign m_axis.tlast  = LAST_EN ? s_axis.tlast : 1'b1;
+assign m_axis.tid    = ID_EN   ? s_axis.tid   : '0;
+assign m_axis.tdest  = DEST_EN ? s_axis.tdest : '0;
+assign m_axis.tuser  = USER_EN ? s_axis.tuser : '0;
+
+assign s_axis.tready = m_axis.tready;
+
+endmodule
+
+`resetall