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Clean up always blocks

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-11-07 01:51:18 -08:00
parent efc907e4c9
commit 5f814e7da8
16 changed files with 30 additions and 30 deletions
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2
src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv
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@@ -188,7 +188,7 @@ reg [1:0] link_speed_sync_reg_2 = 2'b10;
assign link_speed = link_speed_sync_reg_2;
always @(posedge logic_clk) begin
always_ff @(posedge logic_clk) begin
link_speed_sync_reg_1 <= link_speed_int;
link_speed_sync_reg_2 <= link_speed_sync_reg_1;
end

2
src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv
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@@ -187,7 +187,7 @@ reg [1:0] link_speed_sync_reg_2 = 2'b10;
assign link_speed = link_speed_sync_reg_2;
always @(posedge logic_clk) begin
always_ff @(posedge logic_clk) begin
link_speed_sync_reg_1 <= link_speed_int;
link_speed_sync_reg_2 <= link_speed_sync_reg_1;
end

8
src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv
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@@ -161,7 +161,7 @@ reg [0:0] tx_sync_reg_4 = '0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
always_ff @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= '0;
end else begin
@@ -169,7 +169,7 @@ always @(posedge tx_clk or posedge tx_rst) begin
end
end
always @(posedge logic_clk or posedge logic_rst) begin
always_ff @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= '0;
tx_sync_reg_3 <= '0;
@@ -202,7 +202,7 @@ assign rx_block_lock = rx_sync_reg_4[4];
assign rx_high_ber = rx_sync_reg_4[5];
assign rx_status = rx_sync_reg_4[6];
always @(posedge rx_clk or posedge rx_rst) begin
always_ff @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= '0;
end else begin
@@ -216,7 +216,7 @@ always @(posedge rx_clk or posedge rx_rst) begin
end
end
always @(posedge logic_clk or posedge logic_rst) begin
always_ff @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= '0;
rx_sync_reg_3 <= '0;

2
src/eth/rtl/taxi_eth_phy_10g_rx_if.sv
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@@ -111,7 +111,7 @@ if (SERDES_PIPELINE > 0) begin
serdes_rx_hdr_valid_pipe_reg[n] = '0;
end
always @(posedge clk) begin
always_ff @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_data_valid_pipe_reg[n] <= n == 0 ? serdes_rx_data_valid : serdes_rx_data_valid_pipe_reg[n-1];
serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];

2
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
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@@ -119,7 +119,7 @@ if (SERDES_PIPELINE > 0) begin
serdes_tx_gbx_sync_pipe_reg[n] = '0;
end
always @(posedge clk) begin
always_ff @(posedge clk) begin
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1];
serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1];

2
src/eth/rtl/taxi_xgmii_baser_dec.sv
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@@ -152,7 +152,7 @@ end else begin : repack_in
assign encoded_rx_data_valid_int = encoded_rx_data_valid_reg && (GBX_IF_EN ? encoded_rx_data_valid : 1'b1);
assign encoded_rx_hdr_int = encoded_rx_hdr_reg;
always @(posedge clk) begin
always_ff @(posedge clk) begin
if (!GBX_IF_EN || encoded_rx_data_valid) begin
encoded_rx_data_reg <= encoded_rx_data;
encoded_rx_data_valid_reg <= encoded_rx_hdr_valid;

2
src/eth/rtl/taxi_xgmii_baser_enc.sv
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@@ -157,7 +157,7 @@ end else begin : repack_in
assign xgmii_txc_int = {xgmii_txc, xgmii_txc_reg};
assign xgmii_tx_valid_int = xgmii_tx_valid_reg && (GBX_IF_EN ? xgmii_tx_valid : 1'b1);
always @(posedge clk) begin
always_ff @(posedge clk) begin
if (!GBX_IF_EN || xgmii_tx_valid) begin
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;

4
src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv
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@@ -388,7 +388,7 @@ logic tx_req_stall_reg = 1'b0;
assign serdes_tx_gbx_req_sync = tx_req_sync_reg;
assign serdes_tx_gbx_req_stall = tx_req_stall_reg;
always @(posedge tx_clk) begin
always_ff @(posedge tx_clk) begin
tx_req_sync_reg <= 1'b0;
tx_req_stall_reg <= 1'b0;
@@ -407,7 +407,7 @@ logic [6:0] tx_seq_reg = '0;
assign gt_txsequence = {1'b0, tx_seq_reg[6:1]};
always @(posedge tx_clk) begin
always_ff @(posedge tx_clk) begin
tx_seq_reg <= tx_seq_reg + 1;
if (tx_seq_reg == 65) begin
tx_seq_reg <= '0;

8
src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv
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@@ -389,7 +389,7 @@ if (GT_TYPE == "GTY") begin : tx_seq
assign serdes_tx_gbx_req_sync = tx_req_sync_reg;
assign serdes_tx_gbx_req_stall = tx_req_stall_reg;
always @(posedge tx_clk) begin
always_ff @(posedge tx_clk) begin
tx_req_sync_reg <= 1'b0;
tx_req_stall_reg <= 1'b0;
@@ -408,7 +408,7 @@ if (GT_TYPE == "GTY") begin : tx_seq
assign gt_txsequence = {1'b0, tx_seq_reg[6:1]};
always @(posedge tx_clk) begin
always_ff @(posedge tx_clk) begin
tx_seq_reg <= tx_seq_reg + 1;
if (tx_seq_reg == 65) begin
tx_seq_reg <= '0;
@@ -430,7 +430,7 @@ end else begin : tx_seq
assign serdes_tx_gbx_req_sync = tx_req_sync_reg;
assign serdes_tx_gbx_req_stall = tx_req_stall_reg;
always @(posedge tx_clk) begin
always_ff @(posedge tx_clk) begin
tx_req_sync_reg <= 1'b0;
tx_req_stall_reg <= 1'b0;
@@ -449,7 +449,7 @@ end else begin : tx_seq
assign gt_txsequence = {1'b0, tx_seq_reg};
always @(posedge tx_clk) begin
always_ff @(posedge tx_clk) begin
tx_seq_reg <= tx_seq_reg + 1;
if (tx_seq_reg == 32) begin
tx_seq_reg <= '0;