bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 08:58:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

example/KC705: Fix UART IOSTANDARD for KC705

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-09 17:21:49 -07:00
parent fee23c0bf8
commit 62ccbcd22c
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
example/KC705/fpga/fpga.xdc
View File

@@ -69,10 +69,10 @@ set_false_path -from [get_ports {sw[*]}]
set_input_delay 0 [get_ports {sw[*]}]
# UART (U12 CP2103)
set_property -dict {LOC K24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U12.24 RXD_I
set_property -dict {LOC M19 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U12.25 TXD_O
set_property -dict {LOC L27 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U12.23 RTS_O_B
set_property -dict {LOC K23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U12.22 CTS_I_B
set_property -dict {LOC K24 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U12.24 RXD_I
set_property -dict {LOC M19 IOSTANDARD LVCMOS25} [get_ports {uart_rxd}] ;# U12.25 TXD_O
set_property -dict {LOC L27 IOSTANDARD LVCMOS25} [get_ports {uart_rts}] ;# U12.23 RTS_O_B
set_property -dict {LOC K23 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U12.22 CTS_I_B
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]