From 63c9544c3f6e0edff198aa66686e2020aa0a3344 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 20 Feb 2026 22:05:50 -0800 Subject: [PATCH] cndm: Clean up parameters, add flashing support via pyrite Signed-off-by: Alex Forencich --- src/cndm/board/AS02MC04/fpga/fpga/Makefile | 1 + src/cndm/board/AS02MC04/fpga/fpga/config.tcl | 113 +++++++- .../board/AS02MC04/fpga/fpga_10g/Makefile | 1 + .../board/AS02MC04/fpga/fpga_10g/config.tcl | 113 +++++++- .../AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl | 1 + src/cndm/board/AS02MC04/fpga/rtl/fpga.sv | 254 +++++++++++++++++- src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv | 120 ++++++++- .../board/AS02MC04/fpga/tb/fpga_core/Makefile | 15 +- .../fpga/tb/fpga_core/test_fpga_core.py | 15 +- .../fpga/tb/fpga_core/test_fpga_core.sv | 83 +++++- src/cndm/rtl/cndm_micro_core.sv | 20 ++ src/cndm/rtl/cndm_micro_pcie_us.sv | 45 +++- src/cndm/tb/cndm_micro_pcie_us/Makefile | 15 +- .../test_cndm_micro_pcie_us.py | 23 +- .../test_cndm_micro_pcie_us.sv | 47 +++- 15 files changed, 823 insertions(+), 43 deletions(-) diff --git a/src/cndm/board/AS02MC04/fpga/fpga/Makefile b/src/cndm/board/AS02MC04/fpga/fpga/Makefile index 6e35239..264fd0c 100644 --- a/src/cndm/board/AS02MC04/fpga/fpga/Makefile +++ b/src/cndm/board/AS02MC04/fpga/fpga/Makefile @@ -23,6 +23,7 @@ SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f # XDC files XDC_FILES = ../fpga.xdc diff --git a/src/cndm/board/AS02MC04/fpga/fpga/config.tcl b/src/cndm/board/AS02MC04/fpga/fpga/config.tcl index d3508a4..fb4a446 100644 --- a/src/cndm/board/AS02MC04/fpga/fpga/config.tcl +++ b/src/cndm/board/AS02MC04/fpga/fpga/config.tcl @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT # -# Copyright (c) 2025 FPGA Ninja, LLC +# Copyright (c) 2025-2026 FPGA Ninja, LLC # # Authors: # - Alex Forencich @@ -8,11 +8,120 @@ set params [dict create] -# 10G MAC configuration +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4A63093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x1ded] +set board_device_id [expr 0x0009] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration dict set params CFG_LOW_LATENCY "1" dict set params COMBINED_MAC_PCS "1" dict set params MAC_DATA_W "64" +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/src/cndm/board/AS02MC04/fpga/fpga_10g/Makefile b/src/cndm/board/AS02MC04/fpga/fpga_10g/Makefile index 7ea2ef8..f4a0620 100644 --- a/src/cndm/board/AS02MC04/fpga/fpga_10g/Makefile +++ b/src/cndm/board/AS02MC04/fpga/fpga_10g/Makefile @@ -23,6 +23,7 @@ SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f # XDC files XDC_FILES = ../fpga.xdc diff --git a/src/cndm/board/AS02MC04/fpga/fpga_10g/config.tcl b/src/cndm/board/AS02MC04/fpga/fpga_10g/config.tcl index cd72d45..41d7bf0 100644 --- a/src/cndm/board/AS02MC04/fpga/fpga_10g/config.tcl +++ b/src/cndm/board/AS02MC04/fpga/fpga_10g/config.tcl @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT # -# Copyright (c) 2025 FPGA Ninja, LLC +# Copyright (c) 2025-2026 FPGA Ninja, LLC # # Authors: # - Alex Forencich @@ -8,11 +8,120 @@ set params [dict create] -# 10G MAC configuration +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4A63093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x1ded] +set board_device_id [expr 0x0009] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration dict set params CFG_LOW_LATENCY "1" dict set params COMBINED_MAC_PCS "1" dict set params MAC_DATA_W "32" +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/src/cndm/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl b/src/cndm/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl index af4d96e..8f4f6d3 100644 --- a/src/cndm/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl +++ b/src/cndm/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl @@ -22,6 +22,7 @@ set_property -dict [list \ CONFIG.pf0_msi_enabled {true} \ CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ CONFIG.en_msi_per_vec_masking {true} \ + CONFIG.legacy_ext_pcie_cfg_space_enabled {true} \ CONFIG.vendor_id {1234} \ CONFIG.mode_selection {Advanced} \ CONFIG.en_gt_selection {true} \ diff --git a/src/cndm/board/AS02MC04/fpga/rtl/fpga.sv b/src/cndm/board/AS02MC04/fpga/rtl/fpga.sv index 340e7cc..f1abd51 100644 --- a/src/cndm/board/AS02MC04/fpga/rtl/fpga.sv +++ b/src/cndm/board/AS02MC04/fpga/rtl/fpga.sv @@ -23,9 +23,25 @@ module fpga # parameter string VENDOR = "XILINX", // device family parameter string FAMILY = "kintexuplus", + + // FW ID + parameter FPGA_ID = 32'h4A63093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h1ded_0009, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + // PTP configuration parameter logic PTP_TS_EN = 1'b1, - // 10G/25G MAC configuration + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, parameter MAC_DATA_W = 64 @@ -74,6 +90,8 @@ module fpga # ); // Clock and reset +wire pcie_user_clk; +wire pcie_user_rst; wire clk_100mhz_ibufg; @@ -189,6 +207,175 @@ sync_reset_125mhz_inst ( .out(rst_125mhz_int) ); +// Flash +wire qspi_clk_int; +wire [3:0] qspi_dq_int; +wire [3:0] qspi_dq_i_int; +wire [3:0] qspi_dq_o_int; +wire [3:0] qspi_dq_oe_int; +wire qspi_cs_int; + +reg qspi_clk_reg; +reg [3:0] qspi_dq_o_reg; +reg [3:0] qspi_dq_oe_reg; +reg qspi_cs_reg; + +always_ff @(posedge pcie_user_clk) begin + qspi_clk_reg <= qspi_clk_int; + qspi_dq_o_reg <= qspi_dq_o_int; + qspi_dq_oe_reg <= qspi_dq_oe_int; + qspi_cs_reg <= qspi_cs_int; +end + +taxi_sync_signal #( + .WIDTH(8), + .N(2) +) +flash_sync_inst ( + .clk(pcie_user_clk), + .in({qspi_dq_int}), + .out({qspi_dq_i_int}) +); + +STARTUPE3 +startupe3_inst ( + .CFGCLK(), + .CFGMCLK(), + .DI(qspi_dq_int), + .DO(qspi_dq_o_reg), + .DTS(~qspi_dq_oe_reg), + .EOS(), + .FCSBO(qspi_cs_reg), + .FCSBTS(1'b0), + .GSR(1'b0), + .GTS(1'b0), + .KEYCLEARB(1'b1), + .PACK(1'b0), + .PREQ(), + .USRCCLKO(qspi_clk_reg), + .USRCCLKTS(1'b0), + .USRDONEO(1'b0), + .USRDONETS(1'b1) +); + +// FPGA boot +wire fpga_boot; +wire fpga_boot_sync; + +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +fpga_boot_sync_inst ( + .clk(clk_125mhz_int), + .in({fpga_boot}), + .out({fpga_boot_sync}) +); + +wire icap_avail; +logic [2:0] icap_state_reg = 0; +logic icap_csib_reg = 1'b1; +logic icap_rdwrb_reg = 1'b0; +logic [31:0] icap_di_reg = 32'hffffffff; + +wire [31:0] icap_di_rev; + +assign icap_di_rev[ 7] = icap_di_reg[ 0]; +assign icap_di_rev[ 6] = icap_di_reg[ 1]; +assign icap_di_rev[ 5] = icap_di_reg[ 2]; +assign icap_di_rev[ 4] = icap_di_reg[ 3]; +assign icap_di_rev[ 3] = icap_di_reg[ 4]; +assign icap_di_rev[ 2] = icap_di_reg[ 5]; +assign icap_di_rev[ 1] = icap_di_reg[ 6]; +assign icap_di_rev[ 0] = icap_di_reg[ 7]; + +assign icap_di_rev[15] = icap_di_reg[ 8]; +assign icap_di_rev[14] = icap_di_reg[ 9]; +assign icap_di_rev[13] = icap_di_reg[10]; +assign icap_di_rev[12] = icap_di_reg[11]; +assign icap_di_rev[11] = icap_di_reg[12]; +assign icap_di_rev[10] = icap_di_reg[13]; +assign icap_di_rev[ 9] = icap_di_reg[14]; +assign icap_di_rev[ 8] = icap_di_reg[15]; + +assign icap_di_rev[23] = icap_di_reg[16]; +assign icap_di_rev[22] = icap_di_reg[17]; +assign icap_di_rev[21] = icap_di_reg[18]; +assign icap_di_rev[20] = icap_di_reg[19]; +assign icap_di_rev[19] = icap_di_reg[20]; +assign icap_di_rev[18] = icap_di_reg[21]; +assign icap_di_rev[17] = icap_di_reg[22]; +assign icap_di_rev[16] = icap_di_reg[23]; + +assign icap_di_rev[31] = icap_di_reg[24]; +assign icap_di_rev[30] = icap_di_reg[25]; +assign icap_di_rev[29] = icap_di_reg[26]; +assign icap_di_rev[28] = icap_di_reg[27]; +assign icap_di_rev[27] = icap_di_reg[28]; +assign icap_di_rev[26] = icap_di_reg[29]; +assign icap_di_rev[25] = icap_di_reg[30]; +assign icap_di_rev[24] = icap_di_reg[31]; + +always_ff @(posedge clk_125mhz_int) begin + case (icap_state_reg) + 0: begin + icap_state_reg <= 0; + icap_csib_reg <= 1'b1; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + + if (fpga_boot_sync && icap_avail) begin + icap_state_reg <= 1; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + end + end + 1: begin + icap_state_reg <= 2; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hAA995566; // sync word + end + 2: begin + icap_state_reg <= 3; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + 3: begin + icap_state_reg <= 4; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h30008001; // write 1 word to CMD + end + 4: begin + icap_state_reg <= 5; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h0000000F; // IPROG + end + 5: begin + icap_state_reg <= 0; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + endcase +end + +ICAPE3 +icape3_inst ( + .AVAIL(icap_avail), + .CLK(clk_125mhz_int), + .CSIB(icap_csib_reg), + .I(icap_di_rev), + .O(), + .PRDONE(), + .PRERROR(), + .RDWRB(icap_rdwrb_reg) +); + // PCIe localparam AXIS_PCIE_DATA_W = 256; localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32); @@ -201,12 +388,9 @@ localparam RC_STRADDLE = 1'b0; // AXIS_PCIE_DATA_W >= 256; localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6; localparam RQ_SEQ_NUM_EN = 1; -localparam PCIE_TAG_CNT = 64; +localparam PCIE_TAG_CNT = AXIS_PCIE_RQ_USER_W == 60 ? 64 : 256; localparam BAR0_APERTURE = 24; -logic pcie_user_clk; -logic pcie_user_rst; - taxi_axis_if #( .DATA_W(AXIS_PCIE_DATA_W), .KEEP_EN(1), @@ -265,6 +449,15 @@ wire [7:0] cfg_fc_cplh; wire [11:0] cfg_fc_cpld; wire [2:0] cfg_fc_sel; +wire cfg_ext_read_received; +wire cfg_ext_write_received; +wire [9:0] cfg_ext_register_number; +wire [7:0] cfg_ext_function_number; +wire [31:0] cfg_ext_write_data; +wire [3:0] cfg_ext_write_byte_enable; +wire [31:0] cfg_ext_read_data; +wire cfg_ext_read_data_valid; + // wire [3:0] cfg_interrupt_msix_enable; // wire [3:0] cfg_interrupt_msix_mask; // wire [251:0] cfg_interrupt_msix_vf_enable; @@ -437,6 +630,15 @@ pcie4_uscale_plus_inst ( .cfg_link_training_enable(1'b1), + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + .cfg_interrupt_int(4'd0), .cfg_interrupt_pending(4'd0), .cfg_interrupt_sent(), @@ -493,7 +695,28 @@ fpga_core #( .SIM(SIM), .VENDOR(VENDOR), .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // PTP configuration .PTP_TS_EN(PTP_TS_EN), + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W), + + // MAC configuration .CFG_LOW_LATENCY(CFG_LOW_LATENCY), .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .MAC_DATA_W(MAC_DATA_W) @@ -565,6 +788,15 @@ core_inst ( .cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_sel(cfg_fc_sel), + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + // .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), // .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), // .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), @@ -593,7 +825,17 @@ core_inst ( .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number) + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk_int), + .qspi_dq_i(qspi_dq_i_int), + .qspi_dq_o(qspi_dq_o_int), + .qspi_dq_oe(qspi_dq_oe_int), + .qspi_cs(qspi_cs_int) ); endmodule diff --git a/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv b/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv index 8c5658d..c615ba0 100644 --- a/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv +++ b/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv @@ -23,10 +23,28 @@ module fpga_core # parameter string VENDOR = "XILINX", // device family parameter string FAMILY = "kintexuplus", - parameter RQ_SEQ_NUM_W = 6, + + // FW ID + parameter FPGA_ID = 32'h4A63093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h1ded_0009, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + // PTP configuration parameter logic PTP_TS_EN = 1'b1, - // 10G/25G MAC configuration + + // PCIe interface configuration + parameter RQ_SEQ_NUM_W = 6, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, parameter MAC_DATA_W = 64 @@ -98,6 +116,15 @@ module fpga_core # input wire logic [11:0] cfg_fc_cpld, output wire logic [2:0] cfg_fc_sel, + input wire logic cfg_ext_read_received, + input wire logic cfg_ext_write_received, + input wire logic [9:0] cfg_ext_register_number, + input wire logic [7:0] cfg_ext_function_number, + input wire logic [31:0] cfg_ext_write_data, + input wire logic [3:0] cfg_ext_write_byte_enable, + output wire logic [31:0] cfg_ext_read_data, + output wire logic cfg_ext_read_data_valid, + input wire logic [3:0] cfg_interrupt_msi_enable, input wire logic [11:0] cfg_interrupt_msi_mmenable, input wire logic cfg_interrupt_msi_mask_update, @@ -113,12 +140,77 @@ module fpga_core # output wire logic cfg_interrupt_msi_tph_present, output wire logic [1:0] cfg_interrupt_msi_tph_type, output wire logic [7:0] cfg_interrupt_msi_tph_st_tag, - output wire logic [7:0] cfg_interrupt_msi_function_number + output wire logic [7:0] cfg_interrupt_msi_function_number, + + /* + * QSPI flash + */ + output wire logic fpga_boot, + output wire logic qspi_clk, + input wire logic [3:0] qspi_dq_i, + output wire logic [3:0] qspi_dq_o, + output wire logic [3:0] qspi_dq_oe, + output wire logic qspi_cs ); localparam logic PTP_TS_FMT_TOD = 1'b0; localparam PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 48; +// flashing via PCIe VPD +pyrite_pcie_us_vpd_qspi #( + .VPD_CAP_ID(8'h03), + .VPD_CAP_OFFSET(8'hB0), + .VPD_CAP_NEXT(8'h00), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Flash + .FLASH_SEG_COUNT(2), + .FLASH_SEG_DEFAULT(1), + .FLASH_SEG_FALLBACK(0), + .FLASH_SEG0_SIZE(32'h00000000), + .FLASH_DATA_W(4), + .FLASH_DUAL_QSPI(1'b0) +) +pyrite_inst ( + .clk(pcie_clk), + .rst(pcie_rst), + + /* + * PCIe + */ + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk), + .qspi_0_dq_i(qspi_dq_i), + .qspi_0_dq_o(qspi_dq_o), + .qspi_0_dq_oe(qspi_dq_oe), + .qspi_0_cs(qspi_cs), + .qspi_1_dq_i('0), + .qspi_1_dq_o(), + .qspi_1_dq_oe(), + .qspi_1_cs() +); + // SFP+ wire sfp_tx_clk[2]; wire sfp_tx_rst[2]; @@ -462,12 +554,32 @@ cndm_micro_pcie_us #( .SIM(SIM), .VENDOR(VENDOR), .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration .PORTS(2), + + // PTP configuration .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(1'b0), .PTP_CLK_PER_NS_NUM(32), .PTP_CLK_PER_NS_DENOM(5), + + // PCIe interface configuration .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), - .BAR0_APERTURE(24) + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W) ) cndm_inst ( /* diff --git a/src/cndm/board/AS02MC04/fpga/tb/fpga_core/Makefile b/src/cndm/board/AS02MC04/fpga/tb/fpga_core/Makefile index a250103..1c9392c 100644 --- a/src/cndm/board/AS02MC04/fpga/tb/fpga_core/Makefile +++ b/src/cndm/board/AS02MC04/fpga/tb/fpga_core/Makefile @@ -29,6 +29,7 @@ VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) @@ -40,9 +41,17 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) export PARAM_SIM := "1'b1" export PARAM_VENDOR := "\"XILINX\"" export PARAM_FAMILY := "\"kintexuplus\"" -export PARAM_PTP_TS_EN := "1'b1" -export PARAM_CFG_LOW_LATENCY := "1'b1" -export PARAM_COMBINED_MAC_PCS := "1'b1" + +# PTP configuration +export PARAM_PTP_TS_EN := 1 + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_W := 32 +export PARAM_AXIL_CTRL_ADDR_W := 24 + +# MAC configuration +export PARAM_CFG_LOW_LATENCY := 1 +export PARAM_COMBINED_MAC_PCS := 1 export PARAM_MAC_DATA_W := "64" ifeq ($(SIM), icarus) diff --git a/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py index 6951259..c47b2fa 100644 --- a/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py @@ -477,6 +477,7 @@ def test_fpga_core(request, mac_data_w): os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "pyrite", "rtl", "pyrite_pcie_us_vpd_qspi.f"), ] verilog_sources = process_f_files(verilog_sources) @@ -486,9 +487,17 @@ def test_fpga_core(request, mac_data_w): parameters['SIM'] = "1'b1" parameters['VENDOR'] = "\"XILINX\"" parameters['FAMILY'] = "\"kintexuplus\"" - parameters['PTP_TS_EN'] = "1'b1" - parameters['CFG_LOW_LATENCY'] = "1'b1" - parameters['COMBINED_MAC_PCS'] = "1'b1" + + # PTP configuration + parameters['PTP_TS_EN'] = 1 + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_W'] = 32 + parameters['AXIL_CTRL_ADDR_W'] = 24 + + # MAC configuration + parameters['CFG_LOW_LATENCY'] = 1 + parameters['COMBINED_MAC_PCS'] = 1 parameters['MAC_DATA_W'] = mac_data_w extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv b/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv index e6e8b5f..809cdf7 100644 --- a/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv +++ b/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv @@ -21,14 +21,32 @@ module test_fpga_core # parameter logic SIM = 1'b0, parameter string VENDOR = "XILINX", parameter string FAMILY = "kintexuplus", + + // FW ID + parameter FPGA_ID = 32'h4A63093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h1ded_0009, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // PTP configuration + parameter logic PTP_TS_EN = 1'b1, + + // PCIe interface configuration parameter AXIS_PCIE_DATA_W = 256, parameter AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161, parameter AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137, parameter AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183, parameter AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81, - // PTP configuration - parameter logic PTP_TS_EN = 1'b1, - // 10G/25G MAC configuration + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, parameter MAC_DATA_W = 64 @@ -117,6 +135,15 @@ logic [7:0] cfg_fc_cplh; logic [11:0] cfg_fc_cpld; logic [2:0] cfg_fc_sel; +logic cfg_ext_read_received; +logic cfg_ext_write_received; +logic [9:0] cfg_ext_register_number; +logic [7:0] cfg_ext_function_number; +logic [31:0] cfg_ext_write_data; +logic [3:0] cfg_ext_write_byte_enable; +logic [31:0] cfg_ext_read_data; +logic cfg_ext_read_data_valid; + logic [3:0] cfg_interrupt_msi_enable; logic [11:0] cfg_interrupt_msi_mmenable; logic cfg_interrupt_msi_mask_update; @@ -134,14 +161,39 @@ logic [1:0] cfg_interrupt_msi_tph_type; logic [7:0] cfg_interrupt_msi_tph_st_tag; logic [7:0] cfg_interrupt_msi_function_number; +logic fpga_boot; +logic qspi_clk; +logic [3:0] qspi_dq_i; +logic [3:0] qspi_dq_o; +logic [3:0] qspi_dq_oe; +logic qspi_cs; + fpga_core #( .SIM(SIM), .VENDOR(VENDOR), .FAMILY(FAMILY), - .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + // PTP configuration .PTP_TS_EN(PTP_TS_EN), - // 10G/25G MAC configuration + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W), + + // MAC configuration .CFG_LOW_LATENCY(CFG_LOW_LATENCY), .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .MAC_DATA_W(MAC_DATA_W) @@ -199,6 +251,15 @@ uut ( .cfg_fc_cpld(cfg_fc_cpld), .cfg_fc_sel(cfg_fc_sel), + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), @@ -228,7 +289,17 @@ uut ( .sfp_mgt_refclk_out(sfp_mgt_refclk_out), .sfp_npres(sfp_npres), .sfp_tx_fault(sfp_tx_fault), - .sfp_los(sfp_los) + .sfp_los(sfp_los), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk), + .qspi_dq_i(qspi_dq_i), + .qspi_dq_o(qspi_dq_o), + .qspi_dq_oe(qspi_dq_oe), + .qspi_cs(qspi_cs) ); endmodule diff --git a/src/cndm/rtl/cndm_micro_core.sv b/src/cndm/rtl/cndm_micro_core.sv index 23d71da..d2f5e03 100644 --- a/src/cndm/rtl/cndm_micro_core.sv +++ b/src/cndm/rtl/cndm_micro_core.sv @@ -16,7 +16,27 @@ Authors: * Corundum-micro core logic */ module cndm_micro_core #( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "virtexuplus", + + // FW ID + parameter FPGA_ID = 32'hDEADBEEF, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h1234_0000, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // Structural configuration parameter PORTS = 2, + + // PTP configuration parameter logic PTP_TS_EN = 1'b1, parameter logic PTP_TS_FMT_TOD = 1'b0, parameter PTP_CLK_PER_NS_NUM = 512, diff --git a/src/cndm/rtl/cndm_micro_pcie_us.sv b/src/cndm/rtl/cndm_micro_pcie_us.sv index a145e43..0a8b746 100644 --- a/src/cndm/rtl/cndm_micro_pcie_us.sv +++ b/src/cndm/rtl/cndm_micro_pcie_us.sv @@ -22,13 +22,32 @@ module cndm_micro_pcie_us #( parameter string VENDOR = "XILINX", // device family parameter string FAMILY = "virtexuplus", + + // FW ID + parameter FPGA_ID = 32'hDEADBEEF, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h1234_0000, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // Structural configuration parameter PORTS = 2, + + // PTP configuration parameter logic PTP_TS_EN = 1'b1, parameter logic PTP_TS_FMT_TOD = 1'b0, parameter PTP_CLK_PER_NS_NUM = 512, parameter PTP_CLK_PER_NS_DENOM = 165, + + // PCIe interface configuration parameter RQ_SEQ_NUM_W = 6, - parameter BAR0_APERTURE = 24 + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24 ) ( /* @@ -117,12 +136,9 @@ module cndm_micro_pcie_us #( localparam CL_PORTS = $clog2(PORTS); -localparam AXIL_DATA_W = 32; -localparam AXIL_ADDR_W = BAR0_APERTURE; - taxi_axil_if #( - .DATA_W(AXIL_DATA_W), - .ADDR_W(AXIL_ADDR_W), + .DATA_W(AXIL_CTRL_DATA_W), + .ADDR_W(AXIL_CTRL_ADDR_W), .AWUSER_EN(1'b0), .WUSER_EN(1'b0), .BUSER_EN(1'b0), @@ -477,7 +493,24 @@ msi_inst ( ); cndm_micro_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration .PORTS(PORTS), + + // PTP configuration .PTP_TS_EN(PTP_TS_EN), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM), diff --git a/src/cndm/tb/cndm_micro_pcie_us/Makefile b/src/cndm/tb/cndm_micro_pcie_us/Makefile index 3262a8f..eee83fc 100644 --- a/src/cndm/tb/cndm_micro_pcie_us/Makefile +++ b/src/cndm/tb/cndm_micro_pcie_us/Makefile @@ -38,14 +38,25 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) export PARAM_SIM := "1'b1" export PARAM_VENDOR := "\"XILINX\"" export PARAM_FAMILY := "\"virtexuplus\"" + +# Structural configuration export PARAM_PORTS := 2 + +# PTP configuration export PARAM_PTP_TS_EN := 1 export PARAM_PTP_TS_FMT_TOD := 0 export PARAM_PTP_CLK_PER_NS_NUM := 512 export PARAM_PTP_CLK_PER_NS_DENOM := 165 -export PARAM_MAC_DATA_W := 32 + +# PCIe interface configuration export PARAM_AXIS_PCIE_DATA_W := 256 -export PARAM_BAR0_APERTURE := 24 + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_W := 32 +export PARAM_AXIL_CTRL_ADDR_W := 24 + +# MAC configuration +export PARAM_MAC_DATA_W := 32 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py index bfd2c1c..3812ca4 100644 --- a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py +++ b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py @@ -511,14 +511,25 @@ def test_cndm_micro_pcie_us(request, mac_data_w): parameters['SIM'] = "1'b1" parameters['VENDOR'] = "\"XILINX\"" parameters['FAMILY'] = "\"virtexuplus\"" + + # Structural configuration parameters['PORTS'] = 2 - parameters["PTP_TS_EN"] = 1 - parameters["PTP_TS_FMT_TOD"] = 0 - parameters["PTP_CLK_PER_NS_NUM"] = 512 - parameters["PTP_CLK_PER_NS_DENOM"] = 165 - parameters['MAC_DATA_W'] = mac_data_w + + # PTP configuration + parameters['PTP_TS_EN'] = 1 + parameters['PTP_TS_FMT_TOD'] = 0 + parameters['PTP_CLK_PER_NS_NUM'] = 512 + parameters['PTP_CLK_PER_NS_DENOM'] = 165 + + # PCIe interface configuration parameters['AXIS_PCIE_DATA_W'] = 256 - parameters['BAR0_APERTURE'] = 24 + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_W'] = 32 + parameters['AXIL_CTRL_ADDR_W'] = 24 + + # MAC configuration + parameters['MAC_DATA_W'] = mac_data_w extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv index 3fdb96e..b9ea79e 100644 --- a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv +++ b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv @@ -21,18 +21,39 @@ module test_cndm_micro_pcie_us # parameter logic SIM = 1'b0, parameter string VENDOR = "XILINX", parameter string FAMILY = "virtexuplus", + + // FW ID + parameter FPGA_ID = 32'hDEADBEEF, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h1234_0000, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // Structural configuration parameter PORTS = 2, + + // PTP configuration parameter logic PTP_TS_EN = 1'b1, parameter logic PTP_TS_FMT_TOD = 1'b0, parameter PTP_CLK_PER_NS_NUM = 512, parameter PTP_CLK_PER_NS_DENOM = 165, - parameter MAC_DATA_W = 32, + + // PCIe interface configuration parameter AXIS_PCIE_DATA_W = 256, parameter AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161, parameter AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137, parameter AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183, parameter AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81, - parameter BAR0_APERTURE = 24 + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration + parameter MAC_DATA_W = 32 /* verilator lint_on WIDTHTRUNC */ ) (); @@ -172,12 +193,32 @@ cndm_micro_pcie_us #( .SIM(SIM), .VENDOR(VENDOR), .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration .PORTS(PORTS), + + // PTP configuration .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM), .PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM), + + // PCIe interface configuration .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), - .BAR0_APERTURE(BAR0_APERTURE) + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W) ) uut ( /*