eth: Support 32-bit sync gearbox in 10G MAC

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/rtl/taxi_axis_xgmii_rx_32.sv

@@ -19,6 +19,7 @@ module taxi_axis_xgmii_rx_32 #
 (
     parameter DATA_W = 32,
     parameter CTRL_W = (DATA_W/8),
+    parameter logic GBX_IF_EN = 1'b0,
     parameter logic PTP_TS_EN = 1'b0,
     parameter PTP_TS_W = 96
 )
@@ -31,6 +32,7 @@ module taxi_axis_xgmii_rx_32 #
      */
     input  wire logic [DATA_W-1:0]    xgmii_rxd,
     input  wire logic [CTRL_W-1:0]    xgmii_rxc,
+    input  wire logic                 xgmii_rx_valid,
 
     /*
      * Receive interface (AXI stream)
@@ -257,6 +259,10 @@ always_comb begin
     stat_rx_err_framing_next = 1'b0;
     stat_rx_err_preamble_next = 1'b0;
 
+    if (GBX_IF_EN && !xgmii_rx_valid) begin
+        // XGMII data not valid - hold state
+        state_next = state_reg;
+    end else begin
         // counter to measure frame length
         if (&frame_len_reg[15:2] == 0) begin
             if (term_present_reg) begin
@@ -459,6 +465,7 @@ always_comb begin
             end
         endcase
     end
+end
 
 always_ff @(posedge clk) begin
     state_reg <= state_next;
@@ -498,6 +505,7 @@ always_ff @(posedge clk) begin
     stat_rx_err_framing_reg <= stat_rx_err_framing_next;
     stat_rx_err_preamble_reg <= stat_rx_err_preamble_next;
 
+    if (!GBX_IF_EN || xgmii_rx_valid) begin
         term_lane_reg <= 0;
         term_present_reg <= 1'b0;
         framing_error_reg <= xgmii_rxc != 0;
@@ -530,6 +538,7 @@ always_ff @(posedge clk) begin
         xgmii_start_d0 <= xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START;
         xgmii_start_d1 <= xgmii_start_d0;
         xgmii_start_d2 <= xgmii_start_d1;
+    end
 
     if (rst) begin
         state_reg <= STATE_IDLE;

src/eth/rtl/taxi_axis_xgmii_tx_32.sv

@@ -19,6 +19,8 @@ module taxi_axis_xgmii_tx_32 #
 (
     parameter DATA_W = 32,
     parameter CTRL_W = (DATA_W/8),
+    parameter logic GBX_IF_EN = 1'b0,
+    parameter GBX_CNT = 1,
     parameter logic PADDING_EN = 1'b1,
     parameter logic DIC_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
@@ -41,6 +43,10 @@ module taxi_axis_xgmii_tx_32 #
      */
     output wire logic [DATA_W-1:0]    xgmii_txd,
     output wire logic [CTRL_W-1:0]    xgmii_txc,
+    output wire logic                 xgmii_tx_valid,
+    input  wire logic [GBX_CNT-1:0]   tx_gbx_req_sync = '0,
+    input  wire logic                 tx_gbx_req_stall = '0,
+    output wire logic [GBX_CNT-1:0]   tx_gbx_sync,
 
     /*
      * PTP
@@ -157,6 +163,8 @@ wire [31:0] crc_state_next[3:0];
 
 logic [DATA_W-1:0] xgmii_txd_reg = {CTRL_W{XGMII_IDLE}}, xgmii_txd_next;
 logic [CTRL_W-1:0] xgmii_txc_reg = {CTRL_W{1'b1}}, xgmii_txc_next;
+logic xgmii_tx_valid_reg = 1'b0;
+logic [GBX_CNT-1:0] tx_gbx_sync_reg = '0;
 
 logic start_packet_reg = 1'b0, start_packet_next;
 
@@ -172,10 +180,12 @@ logic stat_tx_err_oversize_reg = 1'b0, stat_tx_err_oversize_next;
 logic stat_tx_err_user_reg = 1'b0, stat_tx_err_user_next;
 logic stat_tx_err_underflow_reg = 1'b0, stat_tx_err_underflow_next;
 
-assign s_axis_tx.tready = s_axis_tx_tready_reg;
+assign s_axis_tx.tready = s_axis_tx_tready_reg && (!GBX_IF_EN || !tx_gbx_req_stall);
 
 assign xgmii_txd = xgmii_txd_reg;
 assign xgmii_txc = xgmii_txc_reg;
+assign xgmii_tx_valid = GBX_IF_EN ? xgmii_tx_valid_reg : 1'b1;
+assign tx_gbx_sync = GBX_IF_EN ? tx_gbx_sync_reg : '0;
 
 assign m_axis_tx_cpl.tdata = PTP_TS_EN ? m_axis_tx_cpl_ts_reg : '0;
 assign m_axis_tx_cpl.tkeep = 1'b1;
@@ -340,6 +350,12 @@ always_comb begin
         frame_next = !s_axis_tx.tlast;
     end
 
+    if (GBX_IF_EN && tx_gbx_req_stall) begin
+        // gearbox stall - hold state
+        state_next = state_reg;
+        // frame_start_next = frame_start_reg;
+        s_axis_tx_tready_next = s_axis_tx_tready_reg;
+    end else begin
         // counter for min frame length enforcement
         if (frame_min_count_reg > MIN_LEN_W'(CTRL_W)) begin
             frame_min_count_next = MIN_LEN_W'(frame_min_count_reg - CTRL_W);
@@ -626,6 +642,7 @@ always_comb begin
             end
         endcase
     end
+end
 
 always_ff @(posedge clk) begin
     state_reg <= state_next;
@@ -654,9 +671,13 @@ always_ff @(posedge clk) begin
     m_axis_tx_cpl_tag_reg <= m_axis_tx_cpl_tag_next;
     m_axis_tx_cpl_valid_reg <= m_axis_tx_cpl_valid_next;
 
+    if (GBX_IF_EN && tx_gbx_req_stall) begin
+        // gearbox stall
+    end else begin
         for (integer i = 0; i < 3; i = i + 1) begin
             crc_state_reg[i] <= crc_state_next[i];
         end
+    end
 
     if (update_crc) begin
         crc_state_reg[3] <= crc_state_next[3];
@@ -668,6 +689,7 @@ always_ff @(posedge clk) begin
 
     xgmii_txd_reg <= xgmii_txd_next;
     xgmii_txc_reg <= xgmii_txc_next;
+    xgmii_tx_valid_reg <= !tx_gbx_req_stall;
 
     start_packet_reg <= start_packet_next;
 
@@ -683,6 +705,8 @@ always_ff @(posedge clk) begin
     stat_tx_err_user_reg <= stat_tx_err_user_next;
     stat_tx_err_underflow_reg <= stat_tx_err_underflow_next;
 
+    tx_gbx_sync_reg <= tx_gbx_req_sync;
+
     if (rst) begin
         state_reg <= STATE_IDLE;
 
@@ -697,6 +721,8 @@ always_ff @(posedge clk) begin
 
         xgmii_txd_reg <= {CTRL_W{XGMII_IDLE}};
         xgmii_txc_reg <= {CTRL_W{1'b1}};
+        xgmii_tx_valid_reg <= 1'b0;
+        tx_gbx_sync_reg <= '0;
 
         start_packet_reg <= 1'b0;
 

src/eth/rtl/taxi_eth_mac_10g.sv

@@ -341,6 +341,7 @@ end else if (DATA_W == 32) begin
     taxi_axis_xgmii_rx_32 #(
         .DATA_W(DATA_W),
         .CTRL_W(CTRL_W),
+        .GBX_IF_EN(RX_GBX_IF_EN),
         .PTP_TS_EN(PTP_TS_EN),
         .PTP_TS_W(PTP_TS_W)
     )
@@ -353,6 +354,7 @@ end else if (DATA_W == 32) begin
          */
         .xgmii_rxd(xgmii_rxd),
         .xgmii_rxc(xgmii_rxc),
+        .xgmii_rx_valid(xgmii_rx_valid),
 
         /*
          * Receive interface (AXI stream)
@@ -397,6 +399,8 @@ end else if (DATA_W == 32) begin
     taxi_axis_xgmii_tx_32 #(
         .DATA_W(DATA_W),
         .CTRL_W(CTRL_W),
+        .GBX_IF_EN(TX_GBX_IF_EN),
+        .GBX_CNT(GBX_CNT),
         .PADDING_EN(PADDING_EN),
         .DIC_EN(DIC_EN),
         .MIN_FRAME_LEN(MIN_FRAME_LEN),
@@ -419,6 +423,10 @@ end else if (DATA_W == 32) begin
          */
         .xgmii_txd(xgmii_txd),
         .xgmii_txc(xgmii_txc),
+        .xgmii_tx_valid(xgmii_tx_valid),
+        .tx_gbx_req_sync(tx_gbx_req_sync),
+        .tx_gbx_req_stall(tx_gbx_req_stall),
+        .tx_gbx_sync(tx_gbx_sync),
 
         /*
          * PTP

src/eth/tb/taxi_axis_xgmii_rx_32/Makefile

@@ -35,6 +35,7 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_DATA_W := 32
+export PARAM_GBX_IF_EN := 0
 export PARAM_PTP_TS_EN := 1
 export PARAM_PTP_TS_W := 96
 

src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py

@@ -39,6 +39,8 @@ class TB:
 
         self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
 
+        dut.xgmii_rx_valid.setimmediatevalue(1)
+
         dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
         dut.cfg_rx_enable.setimmediatevalue(0)
 
@@ -305,6 +307,7 @@ def test_taxi_axis_xgmii_rx_32(request):
     parameters = {}
 
     parameters['DATA_W'] = 32
+    parameters['GBX_IF_EN'] = 0
     parameters['PTP_TS_EN'] = 1
     parameters['PTP_TS_W'] = 96
 

src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv

@@ -19,6 +19,7 @@ module test_taxi_axis_xgmii_rx_32 #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter DATA_W = 32,
+    parameter logic GBX_IF_EN = 1'b0,
     parameter logic PTP_TS_EN = 1'b0,
     parameter PTP_TS_W = 96
     /* verilator lint_on WIDTHTRUNC */
@@ -33,6 +34,7 @@ logic rst;
 
 logic [DATA_W-1:0] xgmii_rxd;
 logic [CTRL_W-1:0] xgmii_rxc;
+logic xgmii_rx_valid;
 
 taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
 
@@ -61,6 +63,7 @@ logic stat_rx_err_preamble;
 taxi_axis_xgmii_rx_32 #(
     .DATA_W(DATA_W),
     .CTRL_W(CTRL_W),
+    .GBX_IF_EN(GBX_IF_EN),
     .PTP_TS_EN(PTP_TS_EN),
     .PTP_TS_W(PTP_TS_W)
 )
@@ -73,6 +76,7 @@ uut (
      */
     .xgmii_rxd(xgmii_rxd),
     .xgmii_rxc(xgmii_rxc),
+    .xgmii_rx_valid(xgmii_rx_valid),
 
     /*
      * AXI4-Stream output (source)

src/eth/tb/taxi_axis_xgmii_tx_32/Makefile

@@ -35,6 +35,8 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
 export PARAM_DATA_W := 32
+export PARAM_GBX_IF_EN := 0
+export PARAM_GBX_CNT := 1
 export PARAM_PADDING_EN := 1
 export PARAM_DIC_EN := 1
 export PARAM_MIN_FRAME_LEN := 64

src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py

@@ -520,6 +520,8 @@ def test_taxi_axis_xgmii_tx_32(request, dic_en):
     parameters = {}
 
     parameters['DATA_W'] = 32
+    parameters['GBX_IF_EN'] = 0
+    parameters['GBX_CNT'] = 1
     parameters['PADDING_EN'] = 1
     parameters['DIC_EN'] = dic_en
     parameters['MIN_FRAME_LEN'] = 64

src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv

@@ -19,6 +19,8 @@ module test_taxi_axis_xgmii_tx_32 #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter DATA_W = 32,
+    parameter logic GBX_IF_EN = 1'b0,
+    parameter GBX_CNT = 1,
     parameter logic PADDING_EN = 1'b1,
     parameter logic DIC_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
@@ -41,6 +43,10 @@ taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis
 
 logic [DATA_W-1:0] xgmii_txd;
 logic [CTRL_W-1:0] xgmii_txc;
+logic xgmii_tx_valid;
+logic [GBX_CNT-1:0] tx_gbx_req_sync;
+logic tx_gbx_req_stall;
+logic [GBX_CNT-1:0] tx_gbx_sync;
 
 logic [PTP_TS_W-1:0] ptp_ts;
 
@@ -64,6 +70,8 @@ logic stat_tx_err_underflow;
 taxi_axis_xgmii_tx_32 #(
     .DATA_W(DATA_W),
     .CTRL_W(CTRL_W),
+    .GBX_IF_EN(GBX_IF_EN),
+    .GBX_CNT(GBX_CNT),
     .PADDING_EN(PADDING_EN),
     .DIC_EN(DIC_EN),
     .MIN_FRAME_LEN(MIN_FRAME_LEN),
@@ -86,6 +94,10 @@ uut (
      */
     .xgmii_txd(xgmii_txd),
     .xgmii_txc(xgmii_txc),
+    .xgmii_tx_valid(xgmii_tx_valid),
+    .tx_gbx_req_sync(tx_gbx_req_sync),
+    .tx_gbx_req_stall(tx_gbx_req_stall),
+    .tx_gbx_sync(tx_gbx_sync),
 
     /*
      * PTP