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example/HTG940: Add example design for HTG940
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
373
example/HTG940/fpga/rtl/fpga.sv
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373
example/HTG940/fpga/rtl/fpga.sv
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "zynquplus",
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// Use 90 degree clock for RGMII transmit
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parameter logic USE_CLK90 = 1'b0
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)
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(
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/*
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* Clock: 156.25 MHz LVDS
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*/
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input wire logic ref_clk_p,
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input wire logic ref_clk_n,
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/*
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* GPIO
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*/
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input wire logic [1:0] btn,
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input wire logic [7:0] sw,
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output wire logic [7:0] led,
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/*
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* I2C for board management
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*/
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inout wire logic i2c_main_scl,
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inout wire logic i2c_main_sda,
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output wire logic i2c_main_rst_n,
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/*
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* UART: 115200 bps, 8N1
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*/
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output wire logic uart_rxd,
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input wire logic uart_txd,
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input wire logic uart_rts,
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output wire logic uart_cts,
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output wire logic uart_rst_n,
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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input wire logic phy_rx_clk,
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input wire logic [3:0] phy_rxd,
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input wire logic phy_rx_ctl,
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output wire logic phy_tx_clk,
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output wire logic [3:0] phy_txd,
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output wire logic phy_tx_ctl
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);
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// Clock and reset
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wire ref_clk_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk90_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire clk90_125mhz_int;
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wire rst_125mhz_int;
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// Internal 312.5 MHz clock
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wire clk_312mhz_mmcm_out;
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wire clk_312mhz_int;
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wire rst_312mhz_int;
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wire mmcm_rst = ~btn[0];
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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ref_clk_ibufg_inst (
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.O (ref_clk_ibufg),
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.I (ref_clk_p),
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.IB (ref_clk_n)
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);
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// MMCM instance
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MMCME4_BASE #(
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// 156.25 MHz input
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.CLKIN1_PERIOD(6.4),
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.REF_JITTER1(0.010),
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// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(8),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 90 degrees
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.CLKOUT1_DIVIDE(10),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(90),
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// 1250 MHz / 4 = 312.5 MHz, 0 degrees
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.CLKOUT2_DIVIDE(4),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 156.25 MHz input
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.CLKIN1(ref_clk_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// 125 MHz, 90 degrees
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.CLKOUT1(clk90_125mhz_mmcm_out),
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.CLKOUT1B(),
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// 312.5 MHz, 0 degrees
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.CLKOUT2(clk_312mhz_mmcm_out),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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BUFG
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clk90_125mhz_bufg_inst (
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.I(clk90_125mhz_mmcm_out),
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.O(clk90_125mhz_int)
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);
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BUFG
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clk_312mhz_bufg_inst (
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.I(clk_312mhz_mmcm_out),
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.O(clk_312mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_312mhz_inst (
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.clk(clk_312mhz_int),
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.rst(~mmcm_locked),
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.out(rst_312mhz_int)
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);
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// GPIO
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wire btn_int;
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wire [7:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({btn[1],
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~sw}),
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.out({btn_int,
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sw_int})
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);
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wire uart_txd_int;
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wire uart_rts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({uart_txd, uart_rts}),
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.out({uart_txd_int, uart_rts_int})
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);
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wire i2c_scl_i;
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wire i2c_scl_o;
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wire i2c_scl_t;
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wire i2c_sda_i;
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wire i2c_sda_o;
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wire i2c_sda_t;
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assign i2c_scl_i = i2c_main_scl;
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assign i2c_main_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_main_sda;
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assign i2c_main_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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assign i2c_main_rst_n = 1'b1;
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// IODELAY elements for RGMII interface to PHY
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wire [3:0] phy_rxd_int;
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wire phy_rx_ctl_int;
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IDELAYCTRL #(
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.SIM_DEVICE("ULTRASCALE")
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)
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idelayctrl_inst (
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.REFCLK(clk_312mhz_int),
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.RST(rst_312mhz_int),
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.RDY()
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);
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for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
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IDELAYE3 #(
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.DELAY_SRC("IDATAIN"),
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.CASCADE("NONE"),
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.DELAY_TYPE("FIXED"),
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.DELAY_VALUE(0),
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.REFCLK_FREQUENCY(312.5),
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.DELAY_FORMAT("TIME"),
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.UPDATE_MODE("SYNC"),
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.SIM_DEVICE("ULTRASCALE_PLUS")
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)
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idelay_inst (
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.CASC_IN(1'b0),
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.CASC_RETURN(1'b0),
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.CASC_OUT(),
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.IDATAIN(phy_rxd[n]),
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.DATAIN(1'b0),
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.DATAOUT(phy_rxd_int[n]),
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.CLK(1'b0),
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.EN_VTC(1'b1),
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.CE(1'b0),
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.INC(1'b0),
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.LOAD(1'b0),
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.RST(1'b0),
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.CNTVALUEIN(9'd0),
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.CNTVALUEOUT()
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);
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end
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IDELAYE3 #(
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.DELAY_SRC("IDATAIN"),
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.CASCADE("NONE"),
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.DELAY_TYPE("FIXED"),
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.DELAY_VALUE(0),
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.REFCLK_FREQUENCY(312.5),
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.DELAY_FORMAT("TIME"),
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.UPDATE_MODE("SYNC"),
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.SIM_DEVICE("ULTRASCALE_PLUS")
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)
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phy_rx_ctl_idelay (
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.CASC_IN(1'b0),
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.CASC_RETURN(1'b0),
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.CASC_OUT(),
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.IDATAIN(phy_rx_ctl),
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.DATAIN(1'b0),
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.DATAOUT(phy_rx_ctl_int),
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.CLK(1'b0),
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.EN_VTC(1'b1),
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.CE(1'b0),
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.INC(1'b0),
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.LOAD(1'b0),
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.RST(1'b0),
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.CNTVALUEIN(9'd0),
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.CNTVALUEOUT()
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);
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.USE_CLK90(USE_CLK90)
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk(clk_125mhz_int),
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.clk90(clk90_125mhz_int),
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.rst(rst_125mhz_int),
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/*
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* GPIO
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*/
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.btn(btn_int),
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.sw(sw_int),
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.led(led),
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/*
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* UART: 115200 bps, 8N1
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*/
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.uart_rxd(uart_rxd),
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.uart_txd(uart_txd_int),
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.uart_rts(uart_rts_int),
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.uart_cts(uart_cts),
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.uart_rst_n(uart_rst_n),
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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.phy_rgmii_rx_clk(phy_rx_clk),
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.phy_rgmii_rxd(phy_rxd),
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.phy_rgmii_rx_ctl(phy_rx_ctl),
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.phy_rgmii_tx_clk(phy_tx_clk),
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.phy_rgmii_txd(phy_txd),
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.phy_rgmii_tx_ctl(phy_tx_ctl)
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);
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endmodule
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`resetall
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