diff --git a/example/ADM_PCIE_9V3/fpga/lib/taxi b/example/ADM_PCIE_9V3/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/ADM_PCIE_9V3/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/Alveo/fpga/lib/taxi b/example/Alveo/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/Alveo/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/Alveo/fpga/tb/fpga_core/baser.py b/example/Alveo/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/Alveo/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/Arty/fpga/lib/taxi b/example/Arty/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/Arty/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/HTG940/fpga/lib/taxi b/example/HTG940/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/HTG940/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/KC705/fpga/lib/taxi b/example/KC705/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/KC705/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/KCU105/fpga/fpga_10g/Makefile b/example/KCU105/fpga/fpga_10g/Makefile deleted file mode 100644 index aca362f..0000000 --- a/example/KCU105/fpga/fpga_10g/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# SPDX-License-Identifier: MIT -# -# Copyright (c) 2025 FPGA Ninja, LLC -# -# Authors: -# - Alex Forencich -# - -# FPGA settings -FPGA_PART = xcku040-ffva1156-2-e -FPGA_TOP = fpga -FPGA_ARCH = kintexu - -# Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv - -# XDC files -XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl - -# IP -IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl - -# Configuration -CONFIG_TCL_FILES = ./config.tcl - -include ../common/vivado.mk - -program: $(PROJECT).bit - echo "open_hw_manager" > program.tcl - echo "connect_hw_server" >> program.tcl - echo "open_hw_target" >> program.tcl - echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl - echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl - echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl - echo "program_hw_devices [current_hw_device]" >> program.tcl - echo "exit" >> program.tcl - vivado -nojournal -nolog -mode batch -source program.tcl diff --git a/example/KCU105/fpga/lib/taxi b/example/KCU105/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/KCU105/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/KCU105/fpga/tb/fpga_core/baser.py b/example/KCU105/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/KCU105/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/KR260/fpga/lib/taxi b/example/KR260/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/KR260/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/KR260/fpga/tb/fpga_core/baser.py b/example/KR260/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/KR260/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/Nexus_K3P_Q/fpga/lib/taxi b/example/Nexus_K3P_Q/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/Nexus_K3P_Q/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py b/example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/Nexus_K3P_S/fpga/lib/taxi b/example/Nexus_K3P_S/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/Nexus_K3P_S/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py b/example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/VCU108/fpga/lib/taxi b/example/VCU108/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/VCU108/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/VCU108/fpga/tb/fpga_core/baser.py b/example/VCU108/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/VCU108/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/VCU118/fpga/lib/taxi b/example/VCU118/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/VCU118/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/VCU118/fpga/tb/fpga_core/baser.py b/example/VCU118/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/VCU118/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/XUPP3R/fpga/lib/taxi b/example/XUPP3R/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/XUPP3R/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/XUPP3R/fpga/tb/fpga_core/baser.py b/example/XUPP3R/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/XUPP3R/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/ZCU102/fpga/fpga_10g/Makefile b/example/ZCU102/fpga/fpga_10g/Makefile deleted file mode 100644 index 2b532f0..0000000 --- a/example/ZCU102/fpga/fpga_10g/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# SPDX-License-Identifier: MIT -# -# Copyright (c) 2025 FPGA Ninja, LLC -# -# Authors: -# - Alex Forencich -# - -# FPGA settings -FPGA_PART = xczu9eg-ffvb1156-2-e -FPGA_TOP = fpga -FPGA_ARCH = zynquplus - -# Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv - -# XDC files -XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl - -# IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl - -# Configuration -CONFIG_TCL_FILES = ./config.tcl - -include ../common/vivado.mk - -program: $(FPGA_TOP).bit - echo "open_hw_manager" > program.tcl - echo "connect_hw_server" >> program.tcl - echo "open_hw_target" >> program.tcl - echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl - echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl - echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl - echo "program_hw_devices [current_hw_device]" >> program.tcl - echo "exit" >> program.tcl - vivado -nojournal -nolog -mode batch -source program.tcl - diff --git a/example/ZCU102/fpga/lib/taxi b/example/ZCU102/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/ZCU102/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/ZCU102/fpga/tb/fpga_core/baser.py b/example/ZCU102/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/ZCU102/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/ZCU106/fpga/fpga_10g/Makefile b/example/ZCU106/fpga/fpga_10g/Makefile deleted file mode 100644 index df42fa3..0000000 --- a/example/ZCU106/fpga/fpga_10g/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# SPDX-License-Identifier: MIT -# -# Copyright (c) 2025 FPGA Ninja, LLC -# -# Authors: -# - Alex Forencich -# - -# FPGA settings -FPGA_PART = xczu7ev-ffvc1156-2-e -FPGA_TOP = fpga -FPGA_ARCH = zynquplus - -# Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv - -# XDC files -XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl - -# IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl - -# Configuration -CONFIG_TCL_FILES = ./config.tcl - -include ../common/vivado.mk - -program: $(FPGA_TOP).bit - echo "open_hw_manager" > program.tcl - echo "connect_hw_server" >> program.tcl - echo "open_hw_target" >> program.tcl - echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl - echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl - echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl - echo "program_hw_devices [current_hw_device]" >> program.tcl - echo "exit" >> program.tcl - vivado -nojournal -nolog -mode batch -source program.tcl - diff --git a/example/ZCU106/fpga/lib/taxi b/example/ZCU106/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/ZCU106/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/ZCU106/fpga/tb/fpga_core/baser.py b/example/ZCU106/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/ZCU106/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/ZCU111/fpga/fpga/Makefile b/example/ZCU111/fpga/fpga/Makefile deleted file mode 100644 index bfaaa39..0000000 --- a/example/ZCU111/fpga/fpga/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# SPDX-License-Identifier: MIT -# -# Copyright (c) 2025 FPGA Ninja, LLC -# -# Authors: -# - Alex Forencich -# - -# FPGA settings -FPGA_PART = xczu28dr-ffvg1517-2-e -FPGA_TOP = fpga -FPGA_ARCH = zynquplus - -# Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv - -# XDC files -XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl - -# IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl - -# Configuration -#CONFIG_TCL_FILES = ./config.tcl - -include ../common/vivado.mk - -program: $(FPGA_TOP).bit - echo "open_hw_manager" > program.tcl - echo "connect_hw_server" >> program.tcl - echo "open_hw_target" >> program.tcl - echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl - echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl - echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl - echo "program_hw_devices [current_hw_device]" >> program.tcl - echo "exit" >> program.tcl - vivado -nojournal -nolog -mode batch -source program.tcl - diff --git a/example/ZCU111/fpga/fpga_10g/Makefile b/example/ZCU111/fpga/fpga_10g/Makefile deleted file mode 100644 index bcd112a..0000000 --- a/example/ZCU111/fpga/fpga_10g/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# SPDX-License-Identifier: MIT -# -# Copyright (c) 2025 FPGA Ninja, LLC -# -# Authors: -# - Alex Forencich -# - -# FPGA settings -FPGA_PART = xczu28dr-ffvg1517-2-e -FPGA_TOP = fpga -FPGA_ARCH = zynquplus - -# Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv - -# XDC files -XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl - -# IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl - -# Configuration -#CONFIG_TCL_FILES = ./config.tcl - -include ../common/vivado.mk - -program: $(FPGA_TOP).bit - echo "open_hw_manager" > program.tcl - echo "connect_hw_server" >> program.tcl - echo "open_hw_target" >> program.tcl - echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl - echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl - echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl - echo "program_hw_devices [current_hw_device]" >> program.tcl - echo "exit" >> program.tcl - vivado -nojournal -nolog -mode batch -source program.tcl - diff --git a/example/ZCU111/fpga/lib/taxi b/example/ZCU111/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/ZCU111/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/ZCU111/fpga/tb/fpga_core/baser.py b/example/ZCU111/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/ZCU111/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/example/fb2CG/fpga/lib/taxi b/example/fb2CG/fpga/lib/taxi deleted file mode 120000 index 11a54ed..0000000 --- a/example/fb2CG/fpga/lib/taxi +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/fb2CG/fpga/tb/fpga_core/baser.py b/example/fb2CG/fpga/tb/fpga_core/baser.py deleted file mode 120000 index ac1737a..0000000 --- a/example/fb2CG/fpga/tb/fpga_core/baser.py +++ /dev/null @@ -1 +0,0 @@ -../../lib/taxi/tb/eth/baser.py \ No newline at end of file diff --git a/rtl/axis/taxi_axis_arb_mux.f b/rtl/axis/taxi_axis_arb_mux.f deleted file mode 100644 index ef7656d..0000000 --- a/rtl/axis/taxi_axis_arb_mux.f +++ /dev/null @@ -1,4 +0,0 @@ -taxi_axis_arb_mux.sv -taxi_axis_if.sv -../prim/taxi_arbiter.sv -../prim/taxi_penc.sv diff --git a/rtl/axis/taxi_axis_async_fifo.f b/rtl/axis/taxi_axis_async_fifo.f deleted file mode 100644 index 91a82f3..0000000 --- a/rtl/axis/taxi_axis_async_fifo.f +++ /dev/null @@ -1,4 +0,0 @@ -taxi_axis_async_fifo.sv -../sync/taxi_sync_reset.sv -../sync/taxi_sync_signal.sv -taxi_axis_if.sv diff --git a/rtl/eth/taxi_eth_mac_10g_fifo.f b/rtl/eth/taxi_eth_mac_10g_fifo.f deleted file mode 100644 index 5423500..0000000 --- a/rtl/eth/taxi_eth_mac_10g_fifo.f +++ /dev/null @@ -1,4 +0,0 @@ -taxi_eth_mac_10g_fifo.sv -taxi_eth_mac_10g.f -../ptp/taxi_ptp_clock_cdc.sv -../axis/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_1g_fifo.f b/rtl/eth/taxi_eth_mac_1g_fifo.f deleted file mode 100644 index 1f80bed..0000000 --- a/rtl/eth/taxi_eth_mac_1g_fifo.f +++ /dev/null @@ -1,3 +0,0 @@ -taxi_eth_mac_1g_fifo.sv -taxi_eth_mac_1g.f -../axis/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_1g_gmii_fifo.f b/rtl/eth/taxi_eth_mac_1g_gmii_fifo.f deleted file mode 100644 index e4655dc..0000000 --- a/rtl/eth/taxi_eth_mac_1g_gmii_fifo.f +++ /dev/null @@ -1,3 +0,0 @@ -taxi_eth_mac_1g_gmii_fifo.sv -taxi_eth_mac_1g_gmii.f -../axis/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f b/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f deleted file mode 100644 index fee5a03..0000000 --- a/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f +++ /dev/null @@ -1,3 +0,0 @@ -taxi_eth_mac_1g_rgmii_fifo.sv -taxi_eth_mac_1g_rgmii.f -../axis/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_mii_fifo.f b/rtl/eth/taxi_eth_mac_mii_fifo.f deleted file mode 100644 index 03d6056..0000000 --- a/rtl/eth/taxi_eth_mac_mii_fifo.f +++ /dev/null @@ -1,3 +0,0 @@ -taxi_eth_mac_mii_fifo.sv -taxi_eth_mac_mii.f -../axis/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_phy_10g_fifo.f b/rtl/eth/taxi_eth_mac_phy_10g_fifo.f deleted file mode 100644 index 958a44a..0000000 --- a/rtl/eth/taxi_eth_mac_phy_10g_fifo.f +++ /dev/null @@ -1,4 +0,0 @@ -taxi_eth_mac_phy_10g_fifo.sv -taxi_eth_mac_phy_10g.f -../ptp/taxi_ptp_clock_cdc.sv -../axis/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_phy_10g_rx.f b/rtl/eth/taxi_eth_mac_phy_10g_rx.f deleted file mode 100644 index 350c266..0000000 --- a/rtl/eth/taxi_eth_mac_phy_10g_rx.f +++ /dev/null @@ -1,5 +0,0 @@ -taxi_eth_mac_phy_10g_rx.sv -taxi_eth_phy_10g_rx_if.f -taxi_axis_baser_rx_64.sv -../lfsr/taxi_lfsr.sv -../axis/taxi_axis_if.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g_tx.f b/rtl/eth/taxi_eth_mac_phy_10g_tx.f deleted file mode 100644 index be37e02..0000000 --- a/rtl/eth/taxi_eth_mac_phy_10g_tx.f +++ /dev/null @@ -1,5 +0,0 @@ -taxi_eth_mac_phy_10g_tx.sv -taxi_eth_phy_10g_tx_if.f -taxi_axis_baser_tx_64.sv -../lfsr/taxi_lfsr.sv -../axis/taxi_axis_if.sv diff --git a/rtl/eth/taxi_eth_mac_stats.f b/rtl/eth/taxi_eth_mac_stats.f deleted file mode 100644 index 8f167bf..0000000 --- a/rtl/eth/taxi_eth_mac_stats.f +++ /dev/null @@ -1,4 +0,0 @@ -taxi_eth_mac_stats.sv -../axis/taxi_axis_async_fifo.f -../axis/taxi_axis_arb_mux.f -../stats/taxi_stats_collect.sv diff --git a/rtl/eth/taxi_eth_phy_10g_tx_if.f b/rtl/eth/taxi_eth_phy_10g_tx_if.f deleted file mode 100644 index 625f016..0000000 --- a/rtl/eth/taxi_eth_phy_10g_tx_if.f +++ /dev/null @@ -1,2 +0,0 @@ -taxi_eth_phy_10g_tx_if.sv -../lfsr/taxi_lfsr.sv diff --git a/rtl/eth/taxi_gmii_phy_if.f b/rtl/eth/taxi_gmii_phy_if.f deleted file mode 100644 index 16e16d7..0000000 --- a/rtl/eth/taxi_gmii_phy_if.f +++ /dev/null @@ -1,5 +0,0 @@ -taxi_gmii_phy_if.sv -../io/taxi_ssio_sdr_in.sv -../io/taxi_ssio_sdr_out.sv -../io/taxi_oddr.sv -../sync/taxi_sync_reset.sv diff --git a/rtl/eth/taxi_mii_phy_if.f b/rtl/eth/taxi_mii_phy_if.f deleted file mode 100644 index f7cc5f4..0000000 --- a/rtl/eth/taxi_mii_phy_if.f +++ /dev/null @@ -1,3 +0,0 @@ -taxi_mii_phy_if.sv -../io/taxi_ssio_sdr_in.sv -../sync/taxi_sync_reset.sv diff --git a/rtl/eth/taxi_rgmii_phy_if.f b/rtl/eth/taxi_rgmii_phy_if.f deleted file mode 100644 index 7012b12..0000000 --- a/rtl/eth/taxi_rgmii_phy_if.f +++ /dev/null @@ -1,5 +0,0 @@ -taxi_rgmii_phy_if.sv -../io/taxi_ssio_ddr_in.sv -../io/taxi_iddr.sv -../io/taxi_oddr.sv -../sync/taxi_sync_reset.sv diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gt.f b/rtl/eth/us/taxi_eth_phy_25g_us_gt.f deleted file mode 100644 index f9e932a..0000000 --- a/rtl/eth/us/taxi_eth_phy_25g_us_gt.f +++ /dev/null @@ -1,2 +0,0 @@ -taxi_eth_phy_25g_us_gt.sv -../../sync/taxi_sync_reset.sv diff --git a/rtl/xfcp/taxi_xfcp_if_uart.f b/rtl/xfcp/taxi_xfcp_if_uart.f deleted file mode 100644 index 370bece..0000000 --- a/rtl/xfcp/taxi_xfcp_if_uart.f +++ /dev/null @@ -1,5 +0,0 @@ -taxi_xfcp_if_uart.sv -../lss/taxi_uart.f -../axis/taxi_axis_fifo.sv -../axis/taxi_axis_cobs_encode.f -../axis/taxi_axis_cobs_decode.sv \ No newline at end of file diff --git a/rtl/xfcp/taxi_xfcp_mod_axi.f b/rtl/xfcp/taxi_xfcp_mod_axi.f deleted file mode 100644 index 3ec0865..0000000 --- a/rtl/xfcp/taxi_xfcp_mod_axi.f +++ /dev/null @@ -1,5 +0,0 @@ -taxi_xfcp_mod_axi.sv -taxi_xfcp_mod_axil.sv -../axi/taxi_axi_if.sv -../axi/taxi_axil_if.sv -../axis/taxi_axis_if.sv diff --git a/rtl/xfcp/taxi_xfcp_mod_i2c_master.f b/rtl/xfcp/taxi_xfcp_mod_i2c_master.f deleted file mode 100644 index 6080cab..0000000 --- a/rtl/xfcp/taxi_xfcp_mod_i2c_master.f +++ /dev/null @@ -1,3 +0,0 @@ -taxi_xfcp_mod_i2c_master.sv -../lss/taxi_i2c_master.sv -../axis/taxi_axis_if.sv diff --git a/rtl/xfcp/taxi_xfcp_mod_stats.f b/rtl/xfcp/taxi_xfcp_mod_stats.f deleted file mode 100644 index ffd74d2..0000000 --- a/rtl/xfcp/taxi_xfcp_mod_stats.f +++ /dev/null @@ -1,7 +0,0 @@ -taxi_xfcp_mod_stats.sv -taxi_xfcp_mod_axil.sv -taxi_xfcp_switch.f -../stats/taxi_stats_counter.sv -../stats/taxi_stats_strings_full.sv -../axi/taxi_axil_if.sv -../axis/taxi_axis_if.sv diff --git a/rtl/xfcp/taxi_xfcp_switch.f b/rtl/xfcp/taxi_xfcp_switch.f deleted file mode 100644 index e4f20cd..0000000 --- a/rtl/xfcp/taxi_xfcp_switch.f +++ /dev/null @@ -1,4 +0,0 @@ -taxi_xfcp_switch.sv -../prim/taxi_arbiter.sv -../prim/taxi_penc.sv -../axis/taxi_axis_if.sv diff --git a/src/axi/lib/taxi b/src/axi/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/axi/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/rtl/axi/taxi_axi_if.sv b/src/axi/rtl/taxi_axi_if.sv similarity index 100% rename from rtl/axi/taxi_axi_if.sv rename to src/axi/rtl/taxi_axi_if.sv diff --git a/rtl/axi/taxi_axi_ram.sv b/src/axi/rtl/taxi_axi_ram.sv similarity index 100% rename from rtl/axi/taxi_axi_ram.sv rename to src/axi/rtl/taxi_axi_ram.sv diff --git a/rtl/axi/taxi_axi_register.f b/src/axi/rtl/taxi_axi_register.f similarity index 100% rename from rtl/axi/taxi_axi_register.f rename to src/axi/rtl/taxi_axi_register.f diff --git a/rtl/axi/taxi_axi_register.sv b/src/axi/rtl/taxi_axi_register.sv similarity index 100% rename from rtl/axi/taxi_axi_register.sv rename to src/axi/rtl/taxi_axi_register.sv diff --git a/rtl/axi/taxi_axi_register_rd.sv b/src/axi/rtl/taxi_axi_register_rd.sv similarity index 100% rename from rtl/axi/taxi_axi_register_rd.sv rename to src/axi/rtl/taxi_axi_register_rd.sv diff --git a/rtl/axi/taxi_axi_register_wr.sv b/src/axi/rtl/taxi_axi_register_wr.sv similarity index 100% rename from rtl/axi/taxi_axi_register_wr.sv rename to src/axi/rtl/taxi_axi_register_wr.sv diff --git a/rtl/axi/taxi_axil_dp_ram.sv b/src/axi/rtl/taxi_axil_dp_ram.sv similarity index 100% rename from rtl/axi/taxi_axil_dp_ram.sv rename to src/axi/rtl/taxi_axil_dp_ram.sv diff --git a/rtl/axi/taxi_axil_if.sv b/src/axi/rtl/taxi_axil_if.sv similarity index 100% rename from rtl/axi/taxi_axil_if.sv rename to src/axi/rtl/taxi_axil_if.sv diff --git a/rtl/axi/taxi_axil_ram.sv b/src/axi/rtl/taxi_axil_ram.sv similarity index 100% rename from rtl/axi/taxi_axil_ram.sv rename to src/axi/rtl/taxi_axil_ram.sv diff --git a/rtl/axi/taxi_axil_register.f b/src/axi/rtl/taxi_axil_register.f similarity index 100% rename from rtl/axi/taxi_axil_register.f rename to src/axi/rtl/taxi_axil_register.f diff --git a/rtl/axi/taxi_axil_register.sv b/src/axi/rtl/taxi_axil_register.sv similarity index 100% rename from rtl/axi/taxi_axil_register.sv rename to src/axi/rtl/taxi_axil_register.sv diff --git a/rtl/axi/taxi_axil_register_rd.sv b/src/axi/rtl/taxi_axil_register_rd.sv similarity index 100% rename from rtl/axi/taxi_axil_register_rd.sv rename to src/axi/rtl/taxi_axil_register_rd.sv diff --git a/rtl/axi/taxi_axil_register_wr.sv b/src/axi/rtl/taxi_axil_register_wr.sv similarity index 100% rename from rtl/axi/taxi_axil_register_wr.sv rename to src/axi/rtl/taxi_axil_register_wr.sv diff --git a/tb/axi/taxi_axi_ram/Makefile b/src/axi/tb/taxi_axi_ram/Makefile similarity index 89% rename from tb/axi/taxi_axi_ram/Makefile rename to src/axi/tb/taxi_axi_ram/Makefile index c4ebea2..41aa0da 100644 --- a/tb/axi/taxi_axi_ram/Makefile +++ b/src/axi/tb/taxi_axi_ram/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axi_ram COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axi_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axi_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axi/taxi_axi_ram/test_taxi_axi_ram.py b/src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py similarity index 95% rename from tb/axi/taxi_axi_ram/test_taxi_axi_ram.py rename to src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py index edb3d97..2dc6a56 100644 --- a/tb/axi/taxi_axi_ram/test_taxi_axi_ram.py +++ b/src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py @@ -186,7 +186,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -210,8 +212,8 @@ def test_taxi_axi_ram(request, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axi", f"{dut}.sv"), - os.path.join(rtl_dir, "axi", "taxi_axi_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axi_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axi/taxi_axi_ram/test_taxi_axi_ram.sv b/src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv similarity index 100% rename from tb/axi/taxi_axi_ram/test_taxi_axi_ram.sv rename to src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv diff --git a/tb/axi/taxi_axi_register/Makefile b/src/axi/tb/taxi_axi_register/Makefile similarity index 94% rename from tb/axi/taxi_axi_register/Makefile rename to src/axi/tb/taxi_axi_register/Makefile index 70cc047..fc087fa 100644 --- a/tb/axi/taxi_axi_register/Makefile +++ b/src/axi/tb/taxi_axi_register/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: CERN-OHL-S-2.0 # # Copyright (c) 2020-2025 +# # Authors: # - Alex Forencich @@ -12,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axi_register COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axi/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axi/taxi_axi_register/test_taxi_axi_register.py b/src/axi/tb/taxi_axi_register/test_taxi_axi_register.py similarity index 97% rename from tb/axi/taxi_axi_register/test_taxi_axi_register.py rename to src/axi/tb/taxi_axi_register/test_taxi_axi_register.py index 01098e3..f1607a4 100644 --- a/tb/axi/taxi_axi_register/test_taxi_axi_register.py +++ b/src/axi/tb/taxi_axi_register/test_taxi_axi_register.py @@ -194,7 +194,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -219,7 +221,7 @@ def test_taxi_axi_register(request, data_w, reg_type): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axi", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axi/taxi_axi_register/test_taxi_axi_register.sv b/src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv similarity index 100% rename from tb/axi/taxi_axi_register/test_taxi_axi_register.sv rename to src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv diff --git a/tb/axi/taxi_axil_dp_ram/Makefile b/src/axi/tb/taxi_axil_dp_ram/Makefile similarity index 89% rename from tb/axi/taxi_axil_dp_ram/Makefile rename to src/axi/tb/taxi_axil_dp_ram/Makefile index 735a405..67000b6 100644 --- a/tb/axi/taxi_axil_dp_ram/Makefile +++ b/src/axi/tb/taxi_axil_dp_ram/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axil_dp_ram COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py b/src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py similarity index 96% rename from tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py rename to src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py index dcd5e81..964785c 100644 --- a/tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py +++ b/src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py @@ -220,7 +220,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -244,8 +246,8 @@ def test_taxi_axil_dp_ram(request, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axi", f"{dut}.sv"), - os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axil_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv b/src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv similarity index 100% rename from tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv rename to src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv diff --git a/tb/axi/taxi_axil_ram/Makefile b/src/axi/tb/taxi_axil_ram/Makefile similarity index 89% rename from tb/axi/taxi_axil_ram/Makefile rename to src/axi/tb/taxi_axil_ram/Makefile index 178c087..bb05c07 100644 --- a/tb/axi/taxi_axil_ram/Makefile +++ b/src/axi/tb/taxi_axil_ram/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axil_ram COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axi/taxi_axil_ram/test_taxi_axil_ram.py b/src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py similarity index 95% rename from tb/axi/taxi_axil_ram/test_taxi_axil_ram.py rename to src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py index 10fe27f..20a812b 100644 --- a/tb/axi/taxi_axil_ram/test_taxi_axil_ram.py +++ b/src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py @@ -168,7 +168,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -192,8 +194,8 @@ def test_taxi_axil_ram(request, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axi", f"{dut}.sv"), - os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axil_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axi/taxi_axil_ram/test_taxi_axil_ram.sv b/src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv similarity index 100% rename from tb/axi/taxi_axil_ram/test_taxi_axil_ram.sv rename to src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv diff --git a/tb/axi/taxi_axil_register/Makefile b/src/axi/tb/taxi_axil_register/Makefile similarity index 94% rename from tb/axi/taxi_axil_register/Makefile rename to src/axi/tb/taxi_axil_register/Makefile index aa6040c..f34e339 100644 --- a/tb/axi/taxi_axil_register/Makefile +++ b/src/axi/tb/taxi_axil_register/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axil_register COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axi/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axi/taxi_axil_register/test_taxi_axil_register.py b/src/axi/tb/taxi_axil_register/test_taxi_axil_register.py similarity index 96% rename from tb/axi/taxi_axil_register/test_taxi_axil_register.py rename to src/axi/tb/taxi_axil_register/test_taxi_axil_register.py index 07f5b0a..de94f05 100644 --- a/tb/axi/taxi_axil_register/test_taxi_axil_register.py +++ b/src/axi/tb/taxi_axil_register/test_taxi_axil_register.py @@ -176,7 +176,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -201,7 +203,7 @@ def test_taxi_axil_register(request, data_w, reg_type): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axi", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axi/taxi_axil_register/test_taxi_axil_register.sv b/src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv similarity index 100% rename from tb/axi/taxi_axil_register/test_taxi_axil_register.sv rename to src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv diff --git a/src/axis/lib/taxi b/src/axis/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/axis/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/rtl/axis/taxi_axis_adapter.sv b/src/axis/rtl/taxi_axis_adapter.sv similarity index 100% rename from rtl/axis/taxi_axis_adapter.sv rename to src/axis/rtl/taxi_axis_adapter.sv diff --git a/src/axis/rtl/taxi_axis_arb_mux.f b/src/axis/rtl/taxi_axis_arb_mux.f new file mode 100644 index 0000000..a8d9358 --- /dev/null +++ b/src/axis/rtl/taxi_axis_arb_mux.f @@ -0,0 +1,4 @@ +taxi_axis_arb_mux.sv +taxi_axis_if.sv +../lib/taxi/src/prim/rtl/taxi_arbiter.sv +../lib/taxi/src/prim/rtl/taxi_penc.sv diff --git a/rtl/axis/taxi_axis_arb_mux.sv b/src/axis/rtl/taxi_axis_arb_mux.sv similarity index 100% rename from rtl/axis/taxi_axis_arb_mux.sv rename to src/axis/rtl/taxi_axis_arb_mux.sv diff --git a/src/axis/rtl/taxi_axis_async_fifo.f b/src/axis/rtl/taxi_axis_async_fifo.f new file mode 100644 index 0000000..394fc5e --- /dev/null +++ b/src/axis/rtl/taxi_axis_async_fifo.f @@ -0,0 +1,4 @@ +taxi_axis_async_fifo.sv +../lib/taxi/src/sync/rtl/taxi_sync_reset.sv +../lib/taxi/src/sync/rtl/taxi_sync_signal.sv +taxi_axis_if.sv diff --git a/rtl/axis/taxi_axis_async_fifo.sv b/src/axis/rtl/taxi_axis_async_fifo.sv similarity index 100% rename from rtl/axis/taxi_axis_async_fifo.sv rename to src/axis/rtl/taxi_axis_async_fifo.sv diff --git a/rtl/axis/taxi_axis_async_fifo_adapter.f b/src/axis/rtl/taxi_axis_async_fifo_adapter.f similarity index 100% rename from rtl/axis/taxi_axis_async_fifo_adapter.f rename to src/axis/rtl/taxi_axis_async_fifo_adapter.f diff --git a/rtl/axis/taxi_axis_async_fifo_adapter.sv b/src/axis/rtl/taxi_axis_async_fifo_adapter.sv similarity index 100% rename from rtl/axis/taxi_axis_async_fifo_adapter.sv rename to src/axis/rtl/taxi_axis_async_fifo_adapter.sv diff --git a/rtl/axis/taxi_axis_broadcast.sv b/src/axis/rtl/taxi_axis_broadcast.sv similarity index 100% rename from rtl/axis/taxi_axis_broadcast.sv rename to src/axis/rtl/taxi_axis_broadcast.sv diff --git a/rtl/axis/taxi_axis_cobs_decode.sv b/src/axis/rtl/taxi_axis_cobs_decode.sv similarity index 100% rename from rtl/axis/taxi_axis_cobs_decode.sv rename to src/axis/rtl/taxi_axis_cobs_decode.sv diff --git a/rtl/axis/taxi_axis_cobs_encode.f b/src/axis/rtl/taxi_axis_cobs_encode.f similarity index 100% rename from rtl/axis/taxi_axis_cobs_encode.f rename to src/axis/rtl/taxi_axis_cobs_encode.f diff --git a/rtl/axis/taxi_axis_cobs_encode.sv b/src/axis/rtl/taxi_axis_cobs_encode.sv similarity index 100% rename from rtl/axis/taxi_axis_cobs_encode.sv rename to src/axis/rtl/taxi_axis_cobs_encode.sv diff --git a/rtl/axis/taxi_axis_fifo.sv b/src/axis/rtl/taxi_axis_fifo.sv similarity index 100% rename from rtl/axis/taxi_axis_fifo.sv rename to src/axis/rtl/taxi_axis_fifo.sv diff --git a/rtl/axis/taxi_axis_fifo_adapter.f b/src/axis/rtl/taxi_axis_fifo_adapter.f similarity index 100% rename from rtl/axis/taxi_axis_fifo_adapter.f rename to src/axis/rtl/taxi_axis_fifo_adapter.f diff --git a/rtl/axis/taxi_axis_fifo_adapter.sv b/src/axis/rtl/taxi_axis_fifo_adapter.sv similarity index 100% rename from rtl/axis/taxi_axis_fifo_adapter.sv rename to src/axis/rtl/taxi_axis_fifo_adapter.sv diff --git a/rtl/axis/taxi_axis_if.sv b/src/axis/rtl/taxi_axis_if.sv similarity index 100% rename from rtl/axis/taxi_axis_if.sv rename to src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/axis/taxi_axis_mux.sv b/src/axis/rtl/taxi_axis_mux.sv similarity index 100% rename from rtl/axis/taxi_axis_mux.sv rename to src/axis/rtl/taxi_axis_mux.sv diff --git a/rtl/axis/taxi_axis_pipeline_fifo.sv b/src/axis/rtl/taxi_axis_pipeline_fifo.sv similarity index 100% rename from rtl/axis/taxi_axis_pipeline_fifo.sv rename to src/axis/rtl/taxi_axis_pipeline_fifo.sv diff --git a/rtl/axis/taxi_axis_pipeline_register.f b/src/axis/rtl/taxi_axis_pipeline_register.f similarity index 100% rename from rtl/axis/taxi_axis_pipeline_register.f rename to src/axis/rtl/taxi_axis_pipeline_register.f diff --git a/rtl/axis/taxi_axis_pipeline_register.sv b/src/axis/rtl/taxi_axis_pipeline_register.sv similarity index 100% rename from rtl/axis/taxi_axis_pipeline_register.sv rename to src/axis/rtl/taxi_axis_pipeline_register.sv diff --git a/rtl/axis/taxi_axis_register.sv b/src/axis/rtl/taxi_axis_register.sv similarity index 100% rename from rtl/axis/taxi_axis_register.sv rename to src/axis/rtl/taxi_axis_register.sv diff --git a/syn/vivado/taxi_axis_async_fifo.tcl b/src/axis/syn/vivado/taxi_axis_async_fifo.tcl similarity index 100% rename from syn/vivado/taxi_axis_async_fifo.tcl rename to src/axis/syn/vivado/taxi_axis_async_fifo.tcl diff --git a/tb/axis/taxi_axis_adapter/Makefile b/src/axis/tb/taxi_axis_adapter/Makefile similarity index 91% rename from tb/axis/taxi_axis_adapter/Makefile rename to src/axis/tb/taxi_axis_adapter/Makefile index 3ea9161..f17cd94 100644 --- a/tb/axis/taxi_axis_adapter/Makefile +++ b/src/axis/tb/taxi_axis_adapter/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_adapter COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_adapter/test_taxi_axis_adapter.py b/src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py similarity index 95% rename from tb/axis/taxi_axis_adapter/test_taxi_axis_adapter.py rename to src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py index cb6533f..5aca613 100644 --- a/tb/axis/taxi_axis_adapter/test_taxi_axis_adapter.py +++ b/src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py @@ -199,7 +199,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -224,8 +226,8 @@ def test_taxi_axis_register(request, s_data_width, m_data_width): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_adapter/test_taxi_axis_adapter.sv b/src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv similarity index 100% rename from tb/axis/taxi_axis_adapter/test_taxi_axis_adapter.sv rename to src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv diff --git a/tb/axis/taxi_axis_arb_mux/Makefile b/src/axis/tb/taxi_axis_arb_mux/Makefile similarity index 94% rename from tb/axis/taxi_axis_arb_mux/Makefile rename to src/axis/tb/taxi_axis_arb_mux/Makefile index 6909cbc..7b9e575 100644 --- a/tb/axis/taxi_axis_arb_mux/Makefile +++ b/src/axis/tb/taxi_axis_arb_mux/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_arb_mux COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py b/src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py similarity index 97% rename from tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py rename to src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py index b292674..79d2756 100644 --- a/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py +++ b/src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py @@ -296,7 +296,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -322,7 +324,7 @@ def test_taxi_axis_arb_mux(request, s_count, data_w, round_robin): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv b/src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv similarity index 100% rename from tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv rename to src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv diff --git a/tb/axis/taxi_axis_async_fifo/Makefile b/src/axis/tb/taxi_axis_async_fifo/Makefile similarity index 94% rename from tb/axis/taxi_axis_async_fifo/Makefile rename to src/axis/tb/taxi_axis_async_fifo/Makefile index a0b4546..7bf4505 100644 --- a/tb/axis/taxi_axis_async_fifo/Makefile +++ b/src/axis/tb/taxi_axis_async_fifo/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_async_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py b/src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py similarity index 98% rename from tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py rename to src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py index 9c6e355..58652bb 100644 --- a/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py +++ b/src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py @@ -648,7 +648,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -682,7 +684,7 @@ def test_taxi_axis_async_fifo(request, data_w, ram_pipeline, output_fifo, verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv b/src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv similarity index 100% rename from tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv rename to src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv diff --git a/tb/axis/taxi_axis_async_fifo_adapter/Makefile b/src/axis/tb/taxi_axis_async_fifo_adapter/Makefile similarity index 95% rename from tb/axis/taxi_axis_async_fifo_adapter/Makefile rename to src/axis/tb/taxi_axis_async_fifo_adapter/Makefile index cdae67c..97d8816 100644 --- a/tb/axis/taxi_axis_async_fifo_adapter/Makefile +++ b/src/axis/tb/taxi_axis_async_fifo_adapter/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_async_fifo_adapter COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py b/src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py similarity index 98% rename from tb/axis/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py rename to src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py index adac7f4..df40759 100644 --- a/tb/axis/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py +++ b/src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py @@ -648,7 +648,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -680,7 +682,7 @@ def test_taxi_axis_async_fifo_adapter(request, s_data_w, m_data_w, verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.sv b/src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.sv similarity index 100% rename from tb/axis/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.sv rename to src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.sv diff --git a/tb/axis/taxi_axis_broadcast/Makefile b/src/axis/tb/taxi_axis_broadcast/Makefile similarity index 91% rename from tb/axis/taxi_axis_broadcast/Makefile rename to src/axis/tb/taxi_axis_broadcast/Makefile index 7679db4..0414cae 100644 --- a/tb/axis/taxi_axis_broadcast/Makefile +++ b/src/axis/tb/taxi_axis_broadcast/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_broadcast COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.py b/src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py similarity index 94% rename from tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.py rename to src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py index 5eeb0e8..56eaed8 100644 --- a/tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.py +++ b/src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py @@ -125,7 +125,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -150,8 +152,8 @@ def test_taxi_axis_broadcast(request, m_count, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.sv b/src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv similarity index 100% rename from tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.sv rename to src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv diff --git a/tb/axis/taxi_axis_cobs_decode/Makefile b/src/axis/tb/taxi_axis_cobs_decode/Makefile similarity index 89% rename from tb/axis/taxi_axis_cobs_decode/Makefile rename to src/axis/tb/taxi_axis_cobs_decode/Makefile index 862fa7d..0c18bc6 100644 --- a/tb/axis/taxi_axis_cobs_decode/Makefile +++ b/src/axis/tb/taxi_axis_cobs_decode/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_cobs_decode COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py b/src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py similarity index 95% rename from tb/axis/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py rename to src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py index 23e690b..2ee6ce1 100644 --- a/tb/axis/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py +++ b/src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py @@ -193,7 +193,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -216,8 +218,8 @@ def test_taxi_axis_cobs_decode(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv b/src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv similarity index 100% rename from tb/axis/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv rename to src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv diff --git a/tb/axis/taxi_axis_cobs_encode/Makefile b/src/axis/tb/taxi_axis_cobs_encode/Makefile similarity index 91% rename from tb/axis/taxi_axis_cobs_encode/Makefile rename to src/axis/tb/taxi_axis_cobs_encode/Makefile index 2d8de24..a7bc62a 100644 --- a/tb/axis/taxi_axis_cobs_encode/Makefile +++ b/src/axis/tb/taxi_axis_cobs_encode/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_cobs_encode COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py b/src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py similarity index 96% rename from tb/axis/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py rename to src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py index 6a2bd5f..dd5146a 100644 --- a/tb/axis/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py +++ b/src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py @@ -200,7 +200,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -224,7 +226,7 @@ def test_taxi_axis_cobs_encode(request, append_zero): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv b/src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv similarity index 100% rename from tb/axis/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv rename to src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv diff --git a/tb/axis/taxi_axis_fifo/Makefile b/src/axis/tb/taxi_axis_fifo/Makefile similarity index 92% rename from tb/axis/taxi_axis_fifo/Makefile rename to src/axis/tb/taxi_axis_fifo/Makefile index 0fca470..c85bdc7 100644 --- a/tb/axis/taxi_axis_fifo/Makefile +++ b/src/axis/tb/taxi_axis_fifo/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_fifo/test_taxi_axis_fifo.py b/src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py similarity index 97% rename from tb/axis/taxi_axis_fifo/test_taxi_axis_fifo.py rename to src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py index 0b3474c..178d549 100644 --- a/tb/axis/taxi_axis_fifo/test_taxi_axis_fifo.py +++ b/src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py @@ -430,7 +430,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -463,8 +465,8 @@ def test_taxi_axis_fifo(request, data_w, ram_pipeline, output_fifo, verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_fifo/test_taxi_axis_fifo.sv b/src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv similarity index 100% rename from tb/axis/taxi_axis_fifo/test_taxi_axis_fifo.sv rename to src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv diff --git a/tb/axis/taxi_axis_fifo_adapter/Makefile b/src/axis/tb/taxi_axis_fifo_adapter/Makefile similarity index 95% rename from tb/axis/taxi_axis_fifo_adapter/Makefile rename to src/axis/tb/taxi_axis_fifo_adapter/Makefile index b93f026..ca51d1e 100644 --- a/tb/axis/taxi_axis_fifo_adapter/Makefile +++ b/src/axis/tb/taxi_axis_fifo_adapter/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_fifo_adapter COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.py b/src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.py similarity index 98% rename from tb/axis/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.py rename to src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.py index 95d7c1f..ca6ed92 100644 --- a/tb/axis/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.py +++ b/src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.py @@ -428,7 +428,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -460,7 +462,7 @@ def test_taxi_axis_fifo_adapter(request, s_data_width, m_data_width, verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.sv b/src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.sv similarity index 100% rename from tb/axis/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.sv rename to src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.sv diff --git a/tb/axis/taxi_axis_mux/Makefile b/src/axis/tb/taxi_axis_mux/Makefile similarity index 91% rename from tb/axis/taxi_axis_mux/Makefile rename to src/axis/tb/taxi_axis_mux/Makefile index 4bf4091..76a2eb0 100644 --- a/tb/axis/taxi_axis_mux/Makefile +++ b/src/axis/tb/taxi_axis_mux/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_mux COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_mux/test_taxi_axis_mux.py b/src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py similarity index 95% rename from tb/axis/taxi_axis_mux/test_taxi_axis_mux.py rename to src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py index cc525ea..97789ac 100644 --- a/tb/axis/taxi_axis_mux/test_taxi_axis_mux.py +++ b/src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py @@ -161,7 +161,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -186,8 +188,8 @@ def test_taxi_axis_mux(request, s_count, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_mux/test_taxi_axis_mux.sv b/src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv similarity index 100% rename from tb/axis/taxi_axis_mux/test_taxi_axis_mux.sv rename to src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv diff --git a/tb/axis/taxi_axis_pipeline_fifo/Makefile b/src/axis/tb/taxi_axis_pipeline_fifo/Makefile similarity index 91% rename from tb/axis/taxi_axis_pipeline_fifo/Makefile rename to src/axis/tb/taxi_axis_pipeline_fifo/Makefile index dc7b187..3e08e18 100644 --- a/tb/axis/taxi_axis_pipeline_fifo/Makefile +++ b/src/axis/tb/taxi_axis_pipeline_fifo/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_pipeline_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.py b/src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.py similarity index 96% rename from tb/axis/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.py rename to src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.py index 5780c61..15dce4d 100644 --- a/tb/axis/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.py +++ b/src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.py @@ -285,7 +285,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -310,8 +312,8 @@ def test_taxi_axis_pipeline_fifo(request, length, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv b/src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv similarity index 100% rename from tb/axis/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv rename to src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv diff --git a/tb/axis/taxi_axis_pipeline_register/Makefile b/src/axis/tb/taxi_axis_pipeline_register/Makefile similarity index 93% rename from tb/axis/taxi_axis_pipeline_register/Makefile rename to src/axis/tb/taxi_axis_pipeline_register/Makefile index 0cc1c00..2d330c3 100644 --- a/tb/axis/taxi_axis_pipeline_register/Makefile +++ b/src/axis/tb/taxi_axis_pipeline_register/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_pipeline_register COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.py b/src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.py similarity index 96% rename from tb/axis/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.py rename to src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.py index a74402c..d5ca975 100644 --- a/tb/axis/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.py +++ b/src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.py @@ -195,7 +195,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -221,7 +223,7 @@ def test_taxi_axis_pipeline_register(request, length, data_w, reg_type): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv b/src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv similarity index 100% rename from tb/axis/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv rename to src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv diff --git a/tb/axis/taxi_axis_register/Makefile b/src/axis/tb/taxi_axis_register/Makefile similarity index 91% rename from tb/axis/taxi_axis_register/Makefile rename to src/axis/tb/taxi_axis_register/Makefile index 7121c42..2925391 100644 --- a/tb/axis/taxi_axis_register/Makefile +++ b/src/axis/tb/taxi_axis_register/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_register COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/axis/taxi_axis_register/test_taxi_axis_register.py b/src/axis/tb/taxi_axis_register/test_taxi_axis_register.py similarity index 95% rename from tb/axis/taxi_axis_register/test_taxi_axis_register.py rename to src/axis/tb/taxi_axis_register/test_taxi_axis_register.py index 3e942c0..389b20d 100644 --- a/tb/axis/taxi_axis_register/test_taxi_axis_register.py +++ b/src/axis/tb/taxi_axis_register/test_taxi_axis_register.py @@ -195,7 +195,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -220,8 +222,8 @@ def test_taxi_axis_register(request, data_w, reg_type): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "axis", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/axis/taxi_axis_register/test_taxi_axis_register.sv b/src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv similarity index 100% rename from tb/axis/taxi_axis_register/test_taxi_axis_register.sv rename to src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv diff --git a/example/ADM_PCIE_9V3/fpga/README.md b/src/eth/example/ADM_PCIE_9V3/fpga/README.md similarity index 100% rename from example/ADM_PCIE_9V3/fpga/README.md rename to src/eth/example/ADM_PCIE_9V3/fpga/README.md diff --git a/example/ADM_PCIE_9V3/fpga/common/vivado.mk b/src/eth/example/ADM_PCIE_9V3/fpga/common/vivado.mk similarity index 100% rename from example/ADM_PCIE_9V3/fpga/common/vivado.mk rename to src/eth/example/ADM_PCIE_9V3/fpga/common/vivado.mk diff --git a/example/ADM_PCIE_9V3/fpga/fpga.xdc b/src/eth/example/ADM_PCIE_9V3/fpga/fpga.xdc similarity index 100% rename from example/ADM_PCIE_9V3/fpga/fpga.xdc rename to src/eth/example/ADM_PCIE_9V3/fpga/fpga.xdc diff --git a/example/ADM_PCIE_9V3/fpga/fpga/Makefile b/src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile similarity index 80% rename from example/ADM_PCIE_9V3/fpga/fpga/Makefile rename to src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile index 8b922c8..970fd59 100644 --- a/example/ADM_PCIE_9V3/fpga/fpga/Makefile +++ b/src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile @@ -11,24 +11,28 @@ FPGA_PART = xcvu3p-ffvc1517-2-i FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile b/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile similarity index 80% rename from example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile rename to src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile index 55a10de..931743f 100644 --- a/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile +++ b/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile @@ -11,24 +11,28 @@ FPGA_PART = xcvu3p-ffvc1517-2-i FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi b/src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv similarity index 100% rename from example/ADM_PCIE_9V3/fpga/rtl/fpga.sv rename to src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv diff --git a/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv similarity index 100% rename from example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv rename to src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv diff --git a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile similarity index 75% rename from example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile rename to src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile index 1f60d62..e791e57 100644 --- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile @@ -13,17 +13,21 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py similarity index 90% rename from example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py index 088d05d..68ffc04 100644 --- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py @@ -138,7 +138,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -161,11 +162,11 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/Alveo/fpga/README.md b/src/eth/example/Alveo/fpga/README.md similarity index 100% rename from example/Alveo/fpga/README.md rename to src/eth/example/Alveo/fpga/README.md diff --git a/example/Alveo/fpga/common/vivado.mk b/src/eth/example/Alveo/fpga/common/vivado.mk similarity index 100% rename from example/Alveo/fpga/common/vivado.mk rename to src/eth/example/Alveo/fpga/common/vivado.mk diff --git a/example/Alveo/fpga/fpga_AU200_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU200/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU200_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU200/Makefile index fe6f0a0..ccd64d3 100644 --- a/example/Alveo/fpga/fpga_AU200_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU200/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu200-fsgd2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au200.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au200.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU200/Makefile b/src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU200/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile index 0e26a27..c652db3 100644 --- a/example/Alveo/fpga/fpga_AU200/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu200-fsgd2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au200.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au200.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU250/Makefile b/src/eth/example/Alveo/fpga/fpga_AU250/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU250/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU250/Makefile index 6b7095c..66be138 100644 --- a/example/Alveo/fpga/fpga_AU250/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU250/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu250-figd2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au200.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au200.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU250_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU250_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile index 64d731d..3c73cce 100644 --- a/example/Alveo/fpga/fpga_AU250_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu250-figd2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au200.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au200.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU280/Makefile b/src/eth/example/Alveo/fpga/fpga_AU280/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU280/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU280/Makefile index be9d24d..0992342 100644 --- a/example/Alveo/fpga/fpga_AU280/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU280/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu280-fsvh2892-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au280.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au280.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au280.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU280_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU280_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile index a1722ef..0992342 100644 --- a/example/Alveo/fpga/fpga_AU280_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu280-fsvh2892-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au280.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au280.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au280.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU45N/Makefile b/src/eth/example/Alveo/fpga/fpga_AU45N/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU45N/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU45N/Makefile index 96e6d6b..e424989 100644 --- a/example/Alveo/fpga/fpga_AU45N/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU45N/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu26-vsva1365-2LV-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au45n.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au45n.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au45n.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU45N_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU45N_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile index 9d340e0..c689380 100644 --- a/example/Alveo/fpga/fpga_AU45N_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu26-vsva1365-2LV-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au45n.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au45n.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au45n.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU50/Makefile b/src/eth/example/Alveo/fpga/fpga_AU50/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU50/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU50/Makefile index 979cbf0..9e60ac0 100644 --- a/example/Alveo/fpga/fpga_AU50/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU50/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu50-fsvh2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au50.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au50.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au50.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU50_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU50_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile index a11090b..9febd53 100644 --- a/example/Alveo/fpga/fpga_AU50_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu50-fsvh2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au50.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au50.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au50.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55C/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55C/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU55C/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU55C/Makefile index 57332be..dfc500b 100644 --- a/example/Alveo/fpga/fpga_AU55C/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55C/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu55c-fsvh2892-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au55.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au55.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au55.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55C_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU55C_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile index 1c440fc..1ac4968 100644 --- a/example/Alveo/fpga/fpga_AU55C_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu55c-fsvh2892-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au55.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au55.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au55.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55N/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55N/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU55N/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU55N/Makefile index c329764..f59ca7b 100644 --- a/example/Alveo/fpga/fpga_AU55N/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55N/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu55n-fsvh2892-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au55.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au55.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au55.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55N_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_AU55N_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile index ecd2dc5..c221757 100644 --- a/example/Alveo/fpga/fpga_AU55N_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcu55n-fsvh2892-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au55.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au55.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au55.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_VCU1525/Makefile b/src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile similarity index 88% rename from example/Alveo/fpga/fpga_VCU1525/Makefile rename to src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile index b831781..c953c67 100644 --- a/example/Alveo/fpga/fpga_VCU1525/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcvu9p-fsgd2104-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au200.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au200.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_VCU1525_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile similarity index 88% rename from example/Alveo/fpga/fpga_VCU1525_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile index f459065..63f7863 100644 --- a/example/Alveo/fpga/fpga_VCU1525_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcvu9p-fsgd2104-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_au200.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_au200.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_X3522/Makefile b/src/eth/example/Alveo/fpga/fpga_X3522/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_X3522/Makefile rename to src/eth/example/Alveo/fpga/fpga_X3522/Makefile index f81f0fd..c7d3301 100644 --- a/example/Alveo/fpga/fpga_X3522/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_X3522/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcux35-vsva1365-3-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_x3522.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_x3522.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_x3522.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_X3522_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile similarity index 76% rename from example/Alveo/fpga/fpga_X3522_10g/Makefile rename to src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile index d44561c..8fe3563 100644 --- a/example/Alveo/fpga/fpga_X3522_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile @@ -11,27 +11,31 @@ FPGA_PART = xcux35-vsva1365-3-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_x3522.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga_x3522.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga_x3522.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_au200.xdc b/src/eth/example/Alveo/fpga/fpga_au200.xdc similarity index 100% rename from example/Alveo/fpga/fpga_au200.xdc rename to src/eth/example/Alveo/fpga/fpga_au200.xdc diff --git a/example/Alveo/fpga/fpga_au280.xdc b/src/eth/example/Alveo/fpga/fpga_au280.xdc similarity index 100% rename from example/Alveo/fpga/fpga_au280.xdc rename to src/eth/example/Alveo/fpga/fpga_au280.xdc diff --git a/example/Alveo/fpga/fpga_au45n.xdc b/src/eth/example/Alveo/fpga/fpga_au45n.xdc similarity index 100% rename from example/Alveo/fpga/fpga_au45n.xdc rename to src/eth/example/Alveo/fpga/fpga_au45n.xdc diff --git a/example/Alveo/fpga/fpga_au50.xdc b/src/eth/example/Alveo/fpga/fpga_au50.xdc similarity index 100% rename from example/Alveo/fpga/fpga_au50.xdc rename to src/eth/example/Alveo/fpga/fpga_au50.xdc diff --git a/example/Alveo/fpga/fpga_au55.xdc b/src/eth/example/Alveo/fpga/fpga_au55.xdc similarity index 100% rename from example/Alveo/fpga/fpga_au55.xdc rename to src/eth/example/Alveo/fpga/fpga_au55.xdc diff --git a/example/Alveo/fpga/fpga_x3522.xdc b/src/eth/example/Alveo/fpga/fpga_x3522.xdc similarity index 100% rename from example/Alveo/fpga/fpga_x3522.xdc rename to src/eth/example/Alveo/fpga/fpga_x3522.xdc diff --git a/src/eth/example/Alveo/fpga/lib/taxi b/src/eth/example/Alveo/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/Alveo/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/Alveo/fpga/rtl/fpga_au200.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv similarity index 100% rename from example/Alveo/fpga/rtl/fpga_au200.sv rename to src/eth/example/Alveo/fpga/rtl/fpga_au200.sv diff --git a/example/Alveo/fpga/rtl/fpga_au280.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv similarity index 100% rename from example/Alveo/fpga/rtl/fpga_au280.sv rename to src/eth/example/Alveo/fpga/rtl/fpga_au280.sv diff --git a/example/Alveo/fpga/rtl/fpga_au45n.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv similarity index 100% rename from example/Alveo/fpga/rtl/fpga_au45n.sv rename to src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv diff --git a/example/Alveo/fpga/rtl/fpga_au50.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv similarity index 100% rename from example/Alveo/fpga/rtl/fpga_au50.sv rename to src/eth/example/Alveo/fpga/rtl/fpga_au50.sv diff --git a/example/Alveo/fpga/rtl/fpga_au55.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv similarity index 100% rename from example/Alveo/fpga/rtl/fpga_au55.sv rename to src/eth/example/Alveo/fpga/rtl/fpga_au55.sv diff --git a/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv similarity index 100% rename from example/Alveo/fpga/rtl/fpga_core.sv rename to src/eth/example/Alveo/fpga/rtl/fpga_core.sv diff --git a/example/Alveo/fpga/rtl/fpga_x3522.sv b/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv similarity index 100% rename from example/Alveo/fpga/rtl/fpga_x3522.sv rename to src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv diff --git a/example/Alveo/fpga/tb/fpga_core/Makefile b/src/eth/example/Alveo/fpga/tb/fpga_core/Makefile similarity index 72% rename from example/Alveo/fpga/tb/fpga_core/Makefile rename to src/eth/example/Alveo/fpga/tb/fpga_core/Makefile index 7870181..0e4ed6d 100644 --- a/example/Alveo/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/Makefile @@ -13,20 +13,24 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/Alveo/fpga/tb/fpga_core/baser.py b/src/eth/example/Alveo/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py similarity index 88% rename from example/Alveo/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py index ed4e595..6cc71c2 100644 --- a/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -154,7 +154,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -177,14 +178,14 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/Arty/fpga/README.md b/src/eth/example/Arty/fpga/README.md similarity index 100% rename from example/Arty/fpga/README.md rename to src/eth/example/Arty/fpga/README.md diff --git a/example/Arty/fpga/common/vivado.mk b/src/eth/example/Arty/fpga/common/vivado.mk similarity index 100% rename from example/Arty/fpga/common/vivado.mk rename to src/eth/example/Arty/fpga/common/vivado.mk diff --git a/example/Arty/fpga/fpga.xdc b/src/eth/example/Arty/fpga/fpga.xdc similarity index 100% rename from example/Arty/fpga/fpga.xdc rename to src/eth/example/Arty/fpga/fpga.xdc diff --git a/example/Arty/fpga/fpga/Makefile b/src/eth/example/Arty/fpga/fpga/Makefile similarity index 78% rename from example/Arty/fpga/fpga/Makefile rename to src/eth/example/Arty/fpga/fpga/Makefile index 35bb2f1..be9434b 100644 --- a/example/Arty/fpga/fpga/Makefile +++ b/src/eth/example/Arty/fpga/fpga/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xc7a35t-csg324-1 FPGA_TOP = fpga FPGA_ARCH = artix7 +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_mii_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_mii_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl include ../common/vivado.mk diff --git a/src/eth/example/Arty/fpga/lib/taxi b/src/eth/example/Arty/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/Arty/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/Arty/fpga/rtl/fpga.sv b/src/eth/example/Arty/fpga/rtl/fpga.sv similarity index 100% rename from example/Arty/fpga/rtl/fpga.sv rename to src/eth/example/Arty/fpga/rtl/fpga.sv diff --git a/example/Arty/fpga/rtl/fpga_core.sv b/src/eth/example/Arty/fpga/rtl/fpga_core.sv similarity index 100% rename from example/Arty/fpga/rtl/fpga_core.sv rename to src/eth/example/Arty/fpga/rtl/fpga_core.sv diff --git a/example/Arty/fpga/tb/fpga_core/Makefile b/src/eth/example/Arty/fpga/tb/fpga_core/Makefile similarity index 69% rename from example/Arty/fpga/tb/fpga_core/Makefile rename to src/eth/example/Arty/fpga/tb/fpga_core/Makefile index 720b220..36ae424 100644 --- a/example/Arty/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/Arty/fpga/tb/fpga_core/Makefile @@ -13,19 +13,23 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_mii_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_mii_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py similarity index 86% rename from example/Arty/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py index 34a456d..3095370 100644 --- a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py @@ -122,7 +122,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -145,13 +146,13 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_mii_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_mii_fifo.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/HTG940/fpga/README.md b/src/eth/example/HTG940/fpga/README.md similarity index 100% rename from example/HTG940/fpga/README.md rename to src/eth/example/HTG940/fpga/README.md diff --git a/example/HTG940/fpga/common/vivado.mk b/src/eth/example/HTG940/fpga/common/vivado.mk similarity index 100% rename from example/HTG940/fpga/common/vivado.mk rename to src/eth/example/HTG940/fpga/common/vivado.mk diff --git a/example/HTG940/fpga/eth_rgmii.xdc b/src/eth/example/HTG940/fpga/eth_rgmii.xdc similarity index 100% rename from example/HTG940/fpga/eth_rgmii.xdc rename to src/eth/example/HTG940/fpga/eth_rgmii.xdc diff --git a/example/HTG940/fpga/fpga.xdc b/src/eth/example/HTG940/fpga/fpga.xdc similarity index 100% rename from example/HTG940/fpga/fpga.xdc rename to src/eth/example/HTG940/fpga/fpga.xdc diff --git a/example/HTG940/fpga/fpga_vu13p/Makefile b/src/eth/example/HTG940/fpga/fpga_vu13p/Makefile similarity index 79% rename from example/HTG940/fpga/fpga_vu13p/Makefile rename to src/eth/example/HTG940/fpga/fpga_vu13p/Makefile index 6be0e1c..522e23a 100644 --- a/example/HTG940/fpga/fpga_vu13p/Makefile +++ b/src/eth/example/HTG940/fpga/fpga_vu13p/Makefile @@ -11,25 +11,29 @@ FPGA_PART = xcvu13p-fhgb2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga.xdc XDC_FILES += ../eth_rgmii.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_rgmii_phy_if.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP #IP_TCL_FILES += ../ip/eth_xcvr_gt.tcl diff --git a/example/HTG940/fpga/fpga_vu9p/Makefile b/src/eth/example/HTG940/fpga/fpga_vu9p/Makefile similarity index 79% rename from example/HTG940/fpga/fpga_vu9p/Makefile rename to src/eth/example/HTG940/fpga/fpga_vu9p/Makefile index 454d6ee..bc5cdd9 100644 --- a/example/HTG940/fpga/fpga_vu9p/Makefile +++ b/src/eth/example/HTG940/fpga/fpga_vu9p/Makefile @@ -11,25 +11,29 @@ FPGA_PART = xcvu9p-flgb2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga.xdc XDC_FILES += ../eth_rgmii.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_rgmii_phy_if.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP #IP_TCL_FILES += ../ip/eth_xcvr_gt.tcl diff --git a/src/eth/example/HTG940/fpga/lib/taxi b/src/eth/example/HTG940/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/HTG940/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/HTG940/fpga/rtl/fpga.sv b/src/eth/example/HTG940/fpga/rtl/fpga.sv similarity index 100% rename from example/HTG940/fpga/rtl/fpga.sv rename to src/eth/example/HTG940/fpga/rtl/fpga.sv diff --git a/example/HTG940/fpga/rtl/fpga_core.sv b/src/eth/example/HTG940/fpga/rtl/fpga_core.sv similarity index 100% rename from example/HTG940/fpga/rtl/fpga_core.sv rename to src/eth/example/HTG940/fpga/rtl/fpga_core.sv diff --git a/example/HTG940/fpga/tb/fpga_core/Makefile b/src/eth/example/HTG940/fpga/tb/fpga_core/Makefile similarity index 72% rename from example/HTG940/fpga/tb/fpga_core/Makefile rename to src/eth/example/HTG940/fpga/tb/fpga_core/Makefile index ee5d89e..4a0fa50 100644 --- a/example/HTG940/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/HTG940/fpga/tb/fpga_core/Makefile @@ -13,18 +13,22 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py similarity index 87% rename from example/HTG940/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py index 3f3687c..dbf2183 100644 --- a/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py @@ -128,7 +128,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -151,12 +152,12 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_rgmii_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/KC705/fpga/README.md b/src/eth/example/KC705/fpga/README.md similarity index 100% rename from example/KC705/fpga/README.md rename to src/eth/example/KC705/fpga/README.md diff --git a/example/KC705/fpga/common/vivado.mk b/src/eth/example/KC705/fpga/common/vivado.mk similarity index 100% rename from example/KC705/fpga/common/vivado.mk rename to src/eth/example/KC705/fpga/common/vivado.mk diff --git a/example/KC705/fpga/eth_gmii.xdc b/src/eth/example/KC705/fpga/eth_gmii.xdc similarity index 100% rename from example/KC705/fpga/eth_gmii.xdc rename to src/eth/example/KC705/fpga/eth_gmii.xdc diff --git a/example/KC705/fpga/eth_rgmii.xdc b/src/eth/example/KC705/fpga/eth_rgmii.xdc similarity index 100% rename from example/KC705/fpga/eth_rgmii.xdc rename to src/eth/example/KC705/fpga/eth_rgmii.xdc diff --git a/example/KC705/fpga/fpga.xdc b/src/eth/example/KC705/fpga/fpga.xdc similarity index 100% rename from example/KC705/fpga/fpga.xdc rename to src/eth/example/KC705/fpga/fpga.xdc diff --git a/example/KC705/fpga/fpga_gmii_1g/Makefile b/src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile similarity index 52% rename from example/KC705/fpga/fpga_gmii_1g/Makefile rename to src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile index 8d92f73..98fd70d 100644 --- a/example/KC705/fpga/fpga_gmii_1g/Makefile +++ b/src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile @@ -11,25 +11,29 @@ FPGA_PART = xc7k325tffg900-2 FPGA_TOP = fpga FPGA_ARCH = kintex7 +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_gmii_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc XDC_FILES += ../eth_gmii.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl diff --git a/example/KC705/fpga/fpga_gmii_1g/config.tcl b/src/eth/example/KC705/fpga/fpga_gmii_1g/config.tcl similarity index 100% rename from example/KC705/fpga/fpga_gmii_1g/config.tcl rename to src/eth/example/KC705/fpga/fpga_gmii_1g/config.tcl diff --git a/example/KC705/fpga/fpga_rgmii_1g/Makefile b/src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile similarity index 50% rename from example/KC705/fpga/fpga_rgmii_1g/Makefile rename to src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile index f702f75..3348903 100644 --- a/example/KC705/fpga/fpga_rgmii_1g/Makefile +++ b/src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile @@ -11,26 +11,30 @@ FPGA_PART = xc7k325tffg900-2 FPGA_TOP = fpga FPGA_ARCH = kintex7 +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc XDC_FILES += ../eth_rgmii.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_rgmii_phy_if.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl diff --git a/example/KC705/fpga/fpga_rgmii_1g/config.tcl b/src/eth/example/KC705/fpga/fpga_rgmii_1g/config.tcl similarity index 100% rename from example/KC705/fpga/fpga_rgmii_1g/config.tcl rename to src/eth/example/KC705/fpga/fpga_rgmii_1g/config.tcl diff --git a/example/KC705/fpga/fpga_rgmii_1g/generate_bit_iodelay.tcl b/src/eth/example/KC705/fpga/fpga_rgmii_1g/generate_bit_iodelay.tcl similarity index 100% rename from example/KC705/fpga/fpga_rgmii_1g/generate_bit_iodelay.tcl rename to src/eth/example/KC705/fpga/fpga_rgmii_1g/generate_bit_iodelay.tcl diff --git a/example/KC705/fpga/fpga_sgmii_1g/Makefile b/src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile similarity index 53% rename from example/KC705/fpga/fpga_sgmii_1g/Makefile rename to src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile index 6e7916e..3107772 100644 --- a/example/KC705/fpga/fpga_sgmii_1g/Makefile +++ b/src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xc7k325tffg900-2 FPGA_TOP = fpga FPGA_ARCH = kintex7 +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl diff --git a/example/KC705/fpga/fpga_sgmii_1g/config.tcl b/src/eth/example/KC705/fpga/fpga_sgmii_1g/config.tcl similarity index 100% rename from example/KC705/fpga/fpga_sgmii_1g/config.tcl rename to src/eth/example/KC705/fpga/fpga_sgmii_1g/config.tcl diff --git a/example/KC705/fpga/ip/basex_pcs_pma_0.tcl b/src/eth/example/KC705/fpga/ip/basex_pcs_pma_0.tcl similarity index 100% rename from example/KC705/fpga/ip/basex_pcs_pma_0.tcl rename to src/eth/example/KC705/fpga/ip/basex_pcs_pma_0.tcl diff --git a/example/KC705/fpga/ip/sgmii_pcs_pma_0.tcl b/src/eth/example/KC705/fpga/ip/sgmii_pcs_pma_0.tcl similarity index 100% rename from example/KC705/fpga/ip/sgmii_pcs_pma_0.tcl rename to src/eth/example/KC705/fpga/ip/sgmii_pcs_pma_0.tcl diff --git a/src/eth/example/KC705/fpga/lib/taxi b/src/eth/example/KC705/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/KC705/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/KC705/fpga/rtl/fpga.sv b/src/eth/example/KC705/fpga/rtl/fpga.sv similarity index 100% rename from example/KC705/fpga/rtl/fpga.sv rename to src/eth/example/KC705/fpga/rtl/fpga.sv diff --git a/example/KC705/fpga/rtl/fpga_core.sv b/src/eth/example/KC705/fpga/rtl/fpga_core.sv similarity index 100% rename from example/KC705/fpga/rtl/fpga_core.sv rename to src/eth/example/KC705/fpga/rtl/fpga_core.sv diff --git a/example/KC705/fpga/tb/fpga_core/Makefile b/src/eth/example/KC705/fpga/tb/fpga_core/Makefile similarity index 67% rename from example/KC705/fpga/tb/fpga_core/Makefile rename to src/eth/example/KC705/fpga/tb/fpga_core/Makefile index 49d58cb..37a4dd4 100644 --- a/example/KC705/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/KC705/fpga/tb/fpga_core/Makefile @@ -13,21 +13,25 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_gmii_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/example/KC705/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py similarity index 89% rename from example/KC705/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py index 8afac87..253ea88 100644 --- a/example/KC705/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py @@ -173,7 +173,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -197,15 +198,15 @@ def test_fpga_core(request, phy_type): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_gmii_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_rgmii_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_gmii_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/KCU105/fpga/README.md b/src/eth/example/KCU105/fpga/README.md similarity index 100% rename from example/KCU105/fpga/README.md rename to src/eth/example/KCU105/fpga/README.md diff --git a/example/KCU105/fpga/common/vivado.mk b/src/eth/example/KCU105/fpga/common/vivado.mk similarity index 100% rename from example/KCU105/fpga/common/vivado.mk rename to src/eth/example/KCU105/fpga/common/vivado.mk diff --git a/example/KCU105/fpga/fpga.xdc b/src/eth/example/KCU105/fpga/fpga.xdc similarity index 100% rename from example/KCU105/fpga/fpga.xdc rename to src/eth/example/KCU105/fpga/fpga.xdc diff --git a/src/eth/example/KCU105/fpga/fpga_10g/Makefile b/src/eth/example/KCU105/fpga/fpga_10g/Makefile new file mode 100644 index 0000000..de9901e --- /dev/null +++ b/src/eth/example/KCU105/fpga/fpga_10g/Makefile @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcku040-ffva1156-2-e +FPGA_TOP = fpga +FPGA_ARCH = kintexu + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl diff --git a/example/KR260/fpga/fpga_10g/config.tcl b/src/eth/example/KCU105/fpga/fpga_10g/config.tcl similarity index 100% rename from example/KR260/fpga/fpga_10g/config.tcl rename to src/eth/example/KCU105/fpga/fpga_10g/config.tcl diff --git a/example/KCU105/fpga/fpga_1g/Makefile b/src/eth/example/KCU105/fpga/fpga_1g/Makefile similarity index 54% rename from example/KCU105/fpga/fpga_1g/Makefile rename to src/eth/example/KCU105/fpga/fpga_1g/Makefile index 5f803d8..625273e 100644 --- a/example/KCU105/fpga/fpga_1g/Makefile +++ b/src/eth/example/KCU105/fpga/fpga_1g/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xcku040-ffva1156-2-e FPGA_TOP = fpga FPGA_ARCH = kintexu +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl diff --git a/example/KR260/fpga/fpga_1g/config.tcl b/src/eth/example/KCU105/fpga/fpga_1g/config.tcl similarity index 100% rename from example/KR260/fpga/fpga_1g/config.tcl rename to src/eth/example/KCU105/fpga/fpga_1g/config.tcl diff --git a/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl b/src/eth/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl similarity index 100% rename from example/KCU105/fpga/ip/basex_pcs_pma_0.tcl rename to src/eth/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl diff --git a/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl b/src/eth/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl similarity index 100% rename from example/KCU105/fpga/ip/basex_pcs_pma_1.tcl rename to src/eth/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl diff --git a/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl b/src/eth/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl similarity index 100% rename from example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl rename to src/eth/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl diff --git a/src/eth/example/KCU105/fpga/lib/taxi b/src/eth/example/KCU105/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/KCU105/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/KCU105/fpga/rtl/fpga.sv b/src/eth/example/KCU105/fpga/rtl/fpga.sv similarity index 100% rename from example/KCU105/fpga/rtl/fpga.sv rename to src/eth/example/KCU105/fpga/rtl/fpga.sv diff --git a/example/KCU105/fpga/rtl/fpga_core.sv b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv similarity index 100% rename from example/KCU105/fpga/rtl/fpga_core.sv rename to src/eth/example/KCU105/fpga/rtl/fpga_core.sv diff --git a/example/KCU105/fpga/tb/fpga_core/Makefile b/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile similarity index 67% rename from example/KCU105/fpga/tb/fpga_core/Makefile rename to src/eth/example/KCU105/fpga/tb/fpga_core/Makefile index c2a0344..6caf816 100644 --- a/example/KCU105/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile @@ -13,20 +13,24 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/KCU105/fpga/tb/fpga_core/baser.py b/src/eth/example/KCU105/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/KCU105/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py similarity index 91% rename from example/KCU105/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py index 1e70efc..bc5ae55 100644 --- a/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py @@ -230,7 +230,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -254,14 +255,14 @@ def test_fpga_core(request, sfp_rate): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/KR260/fpga/README.md b/src/eth/example/KR260/fpga/README.md similarity index 100% rename from example/KR260/fpga/README.md rename to src/eth/example/KR260/fpga/README.md diff --git a/example/KR260/fpga/common/vivado.mk b/src/eth/example/KR260/fpga/common/vivado.mk similarity index 100% rename from example/KR260/fpga/common/vivado.mk rename to src/eth/example/KR260/fpga/common/vivado.mk diff --git a/example/KR260/fpga/eth_rgmii.xdc b/src/eth/example/KR260/fpga/eth_rgmii.xdc similarity index 100% rename from example/KR260/fpga/eth_rgmii.xdc rename to src/eth/example/KR260/fpga/eth_rgmii.xdc diff --git a/example/KR260/fpga/fpga.xdc b/src/eth/example/KR260/fpga/fpga.xdc similarity index 100% rename from example/KR260/fpga/fpga.xdc rename to src/eth/example/KR260/fpga/fpga.xdc diff --git a/example/KR260/fpga/fpga_10g/Makefile b/src/eth/example/KR260/fpga/fpga_10g/Makefile similarity index 53% rename from example/KR260/fpga/fpga_10g/Makefile rename to src/eth/example/KR260/fpga/fpga_10g/Makefile index db28579..3565c3d 100644 --- a/example/KR260/fpga/fpga_10g/Makefile +++ b/src/eth/example/KR260/fpga/fpga_10g/Makefile @@ -11,25 +11,29 @@ FPGA_PART = xck26-sfvc784-2LV-c FPGA_TOP = fpga FPGA_ARCH = zynquplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga.xdc XDC_FILES += ../eth_rgmii.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_rgmii_phy_if.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ZCU102/fpga/fpga_10g/config.tcl b/src/eth/example/KR260/fpga/fpga_10g/config.tcl similarity index 100% rename from example/ZCU102/fpga/fpga_10g/config.tcl rename to src/eth/example/KR260/fpga/fpga_10g/config.tcl diff --git a/example/KR260/fpga/fpga_1g/Makefile b/src/eth/example/KR260/fpga/fpga_1g/Makefile similarity index 56% rename from example/KR260/fpga/fpga_1g/Makefile rename to src/eth/example/KR260/fpga/fpga_1g/Makefile index d960bbb..9c8e268 100644 --- a/example/KR260/fpga/fpga_1g/Makefile +++ b/src/eth/example/KR260/fpga/fpga_1g/Makefile @@ -11,22 +11,26 @@ FPGA_PART = xck26-sfvc784-2LV-c FPGA_TOP = fpga FPGA_ARCH = zynquplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga.xdc XDC_FILES += ../eth_rgmii.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_rgmii_phy_if.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/basex_pcs_pma_0.tcl diff --git a/example/ZCU102/fpga/fpga_1g/config.tcl b/src/eth/example/KR260/fpga/fpga_1g/config.tcl similarity index 100% rename from example/ZCU102/fpga/fpga_1g/config.tcl rename to src/eth/example/KR260/fpga/fpga_1g/config.tcl diff --git a/example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl b/src/eth/example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl similarity index 100% rename from example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl rename to src/eth/example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl diff --git a/example/KR260/fpga/ip/basex_pcs_pma_0.tcl b/src/eth/example/KR260/fpga/ip/basex_pcs_pma_0.tcl similarity index 100% rename from example/KR260/fpga/ip/basex_pcs_pma_0.tcl rename to src/eth/example/KR260/fpga/ip/basex_pcs_pma_0.tcl diff --git a/src/eth/example/KR260/fpga/lib/taxi b/src/eth/example/KR260/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/KR260/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/KR260/fpga/rtl/fpga.sv b/src/eth/example/KR260/fpga/rtl/fpga.sv similarity index 100% rename from example/KR260/fpga/rtl/fpga.sv rename to src/eth/example/KR260/fpga/rtl/fpga.sv diff --git a/example/KR260/fpga/rtl/fpga_core.sv b/src/eth/example/KR260/fpga/rtl/fpga_core.sv similarity index 100% rename from example/KR260/fpga/rtl/fpga_core.sv rename to src/eth/example/KR260/fpga/rtl/fpga_core.sv diff --git a/example/KR260/fpga/tb/fpga_core/Makefile b/src/eth/example/KR260/fpga/tb/fpga_core/Makefile similarity index 75% rename from example/KR260/fpga/tb/fpga_core/Makefile rename to src/eth/example/KR260/fpga/tb/fpga_core/Makefile index aa22e54..f6cc4e7 100644 --- a/example/KR260/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/KR260/fpga/tb/fpga_core/Makefile @@ -13,17 +13,21 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/KR260/fpga/tb/fpga_core/baser.py b/src/eth/example/KR260/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/KR260/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/KR260/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py similarity index 93% rename from example/KR260/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py index f45a7de..d82875c 100644 --- a/example/KR260/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py @@ -217,7 +217,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -241,11 +242,11 @@ def test_fpga_core(request, sfp_rate): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_rgmii_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/Nexus_K3P_Q/fpga/README.md b/src/eth/example/Nexus_K3P_Q/fpga/README.md similarity index 100% rename from example/Nexus_K3P_Q/fpga/README.md rename to src/eth/example/Nexus_K3P_Q/fpga/README.md diff --git a/example/Nexus_K3P_Q/fpga/common/vivado.mk b/src/eth/example/Nexus_K3P_Q/fpga/common/vivado.mk similarity index 100% rename from example/Nexus_K3P_Q/fpga/common/vivado.mk rename to src/eth/example/Nexus_K3P_Q/fpga/common/vivado.mk diff --git a/example/Nexus_K3P_Q/fpga/fpga.xdc b/src/eth/example/Nexus_K3P_Q/fpga/fpga.xdc similarity index 100% rename from example/Nexus_K3P_Q/fpga/fpga.xdc rename to src/eth/example/Nexus_K3P_Q/fpga/fpga.xdc diff --git a/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile b/src/eth/example/Nexus_K3P_Q/fpga/fpga/Makefile similarity index 52% rename from example/Nexus_K3P_Q/fpga/fpga_10g/Makefile rename to src/eth/example/Nexus_K3P_Q/fpga/fpga/Makefile index ff5ceee..d6cba96 100644 --- a/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile +++ b/src/eth/example/Nexus_K3P_Q/fpga/fpga/Makefile @@ -11,24 +11,28 @@ FPGA_PART = xcku3p-ffvb676-2-e FPGA_TOP = fpga FPGA_ARCH = kintexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Nexus_K3P_Q/fpga/fpga/Makefile b/src/eth/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile similarity index 52% rename from example/Nexus_K3P_Q/fpga/fpga/Makefile rename to src/eth/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile index c0a4edf..68daf95 100644 --- a/example/Nexus_K3P_Q/fpga/fpga/Makefile +++ b/src/eth/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile @@ -11,24 +11,28 @@ FPGA_PART = xcku3p-ffvb676-2-e FPGA_TOP = fpga FPGA_ARCH = kintexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/src/eth/example/Nexus_K3P_Q/fpga/lib/taxi b/src/eth/example/Nexus_K3P_Q/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/Nexus_K3P_Q/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/Nexus_K3P_Q/fpga/rtl/fpga.sv b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga.sv similarity index 100% rename from example/Nexus_K3P_Q/fpga/rtl/fpga.sv rename to src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga.sv diff --git a/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv similarity index 100% rename from example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv rename to src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv diff --git a/example/fb2CG/fpga/tb/fpga_core/Makefile b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile similarity index 77% rename from example/fb2CG/fpga/tb/fpga_core/Makefile rename to src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile index 07349ea..d6308b1 100644 --- a/example/fb2CG/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile @@ -13,17 +13,20 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_led_sreg.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py similarity index 91% rename from example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py index 57188e8..6d4d6eb 100644 --- a/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py @@ -141,7 +141,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -164,10 +165,10 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/Nexus_K3P_S/fpga/README.md b/src/eth/example/Nexus_K3P_S/fpga/README.md similarity index 100% rename from example/Nexus_K3P_S/fpga/README.md rename to src/eth/example/Nexus_K3P_S/fpga/README.md diff --git a/example/Nexus_K3P_S/fpga/common/vivado.mk b/src/eth/example/Nexus_K3P_S/fpga/common/vivado.mk similarity index 100% rename from example/Nexus_K3P_S/fpga/common/vivado.mk rename to src/eth/example/Nexus_K3P_S/fpga/common/vivado.mk diff --git a/example/Nexus_K3P_S/fpga/fpga_K35/Makefile b/src/eth/example/Nexus_K3P_S/fpga/fpga_K35/Makefile similarity index 81% rename from example/Nexus_K3P_S/fpga/fpga_K35/Makefile rename to src/eth/example/Nexus_K3P_S/fpga/fpga_K35/Makefile index ba303b0..d2ad263 100644 --- a/example/Nexus_K3P_S/fpga/fpga_K35/Makefile +++ b/src/eth/example/Nexus_K3P_S/fpga/fpga_K35/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xcku035-fbva676-2-e FPGA_TOP = fpga FPGA_ARCH = kintexu +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_k35.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga_k35.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga_k35.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile similarity index 81% rename from example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile rename to src/eth/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile index 105fb40..da70283 100644 --- a/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile +++ b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xcku3p-ffvb676-2-e FPGA_TOP = fpga FPGA_ARCH = kintexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_k3p.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga_k3p.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga_k3p.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl @@ -82,4 +86,3 @@ flash: $(PROJECT).mcs $(PROJECT).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile similarity index 81% rename from example/Nexus_K3P_S/fpga/fpga_K3P/Makefile rename to src/eth/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile index 9337034..221a86f 100644 --- a/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile +++ b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xcku3p-ffvb676-2-e FPGA_TOP = fpga FPGA_ARCH = kintexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_k3p.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga_k3p.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga_k3p.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl @@ -82,3 +86,4 @@ flash: $(PROJECT).mcs $(PROJECT).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/example/Nexus_K3P_S/fpga/fpga_k35.xdc b/src/eth/example/Nexus_K3P_S/fpga/fpga_k35.xdc similarity index 100% rename from example/Nexus_K3P_S/fpga/fpga_k35.xdc rename to src/eth/example/Nexus_K3P_S/fpga/fpga_k35.xdc diff --git a/example/Nexus_K3P_S/fpga/fpga_k3p.xdc b/src/eth/example/Nexus_K3P_S/fpga/fpga_k3p.xdc similarity index 100% rename from example/Nexus_K3P_S/fpga/fpga_k3p.xdc rename to src/eth/example/Nexus_K3P_S/fpga/fpga_k3p.xdc diff --git a/src/eth/example/Nexus_K3P_S/fpga/lib/taxi b/src/eth/example/Nexus_K3P_S/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/Nexus_K3P_S/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv similarity index 100% rename from example/Nexus_K3P_S/fpga/rtl/fpga_core.sv rename to src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv diff --git a/example/Nexus_K3P_S/fpga/rtl/fpga_k35.sv b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_k35.sv similarity index 100% rename from example/Nexus_K3P_S/fpga/rtl/fpga_k35.sv rename to src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_k35.sv diff --git a/example/Nexus_K3P_S/fpga/rtl/fpga_k3p.sv b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_k3p.sv similarity index 100% rename from example/Nexus_K3P_S/fpga/rtl/fpga_k3p.sv rename to src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_k3p.sv diff --git a/example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/Makefile similarity index 77% rename from example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile rename to src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/Makefile index b42edfd..d6308b1 100644 --- a/example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/Makefile @@ -13,16 +13,20 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py similarity index 91% rename from example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py index 06e04c6..3923c22 100644 --- a/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py @@ -138,7 +138,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -161,10 +162,10 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/VCU108/fpga/README.md b/src/eth/example/VCU108/fpga/README.md similarity index 100% rename from example/VCU108/fpga/README.md rename to src/eth/example/VCU108/fpga/README.md diff --git a/example/VCU108/fpga/common/vivado.mk b/src/eth/example/VCU108/fpga/common/vivado.mk similarity index 100% rename from example/VCU108/fpga/common/vivado.mk rename to src/eth/example/VCU108/fpga/common/vivado.mk diff --git a/example/VCU108/fpga/fpga.xdc b/src/eth/example/VCU108/fpga/fpga.xdc similarity index 100% rename from example/VCU108/fpga/fpga.xdc rename to src/eth/example/VCU108/fpga/fpga.xdc diff --git a/example/VCU108/fpga/fpga/Makefile b/src/eth/example/VCU108/fpga/fpga/Makefile similarity index 76% rename from example/VCU108/fpga/fpga/Makefile rename to src/eth/example/VCU108/fpga/fpga/Makefile index 75dc8e4..48eaac6 100644 --- a/example/VCU108/fpga/fpga/Makefile +++ b/src/eth/example/VCU108/fpga/fpga/Makefile @@ -11,28 +11,32 @@ FPGA_PART = xcvu095-ffva2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexu +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl include ../common/vivado.mk diff --git a/example/VCU108/fpga/fpga_10g/Makefile b/src/eth/example/VCU108/fpga/fpga_10g/Makefile similarity index 76% rename from example/VCU108/fpga/fpga_10g/Makefile rename to src/eth/example/VCU108/fpga/fpga_10g/Makefile index 36d91aa..76bf301 100644 --- a/example/VCU108/fpga/fpga_10g/Makefile +++ b/src/eth/example/VCU108/fpga/fpga_10g/Makefile @@ -11,28 +11,32 @@ FPGA_PART = xcvu095-ffva2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexu +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl include ../common/vivado.mk diff --git a/example/VCU108/fpga/ip/sgmii_pcs_pma_0.tcl b/src/eth/example/VCU108/fpga/ip/sgmii_pcs_pma_0.tcl similarity index 100% rename from example/VCU108/fpga/ip/sgmii_pcs_pma_0.tcl rename to src/eth/example/VCU108/fpga/ip/sgmii_pcs_pma_0.tcl diff --git a/src/eth/example/VCU108/fpga/lib/taxi b/src/eth/example/VCU108/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/VCU108/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/VCU108/fpga/rtl/fpga.sv b/src/eth/example/VCU108/fpga/rtl/fpga.sv similarity index 100% rename from example/VCU108/fpga/rtl/fpga.sv rename to src/eth/example/VCU108/fpga/rtl/fpga.sv diff --git a/example/VCU108/fpga/rtl/fpga_core.sv b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv similarity index 100% rename from example/VCU108/fpga/rtl/fpga_core.sv rename to src/eth/example/VCU108/fpga/rtl/fpga_core.sv diff --git a/example/VCU108/fpga/tb/fpga_core/Makefile b/src/eth/example/VCU108/fpga/tb/fpga_core/Makefile similarity index 67% rename from example/VCU108/fpga/tb/fpga_core/Makefile rename to src/eth/example/VCU108/fpga/tb/fpga_core/Makefile index 9bfa00a..0712d40 100644 --- a/example/VCU108/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/VCU108/fpga/tb/fpga_core/Makefile @@ -13,20 +13,24 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/VCU108/fpga/tb/fpga_core/baser.py b/src/eth/example/VCU108/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/VCU108/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py similarity index 90% rename from example/VCU108/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py index 121253f..93505b3 100644 --- a/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py @@ -205,7 +205,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -228,14 +229,14 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/VCU118/fpga/README.md b/src/eth/example/VCU118/fpga/README.md similarity index 100% rename from example/VCU118/fpga/README.md rename to src/eth/example/VCU118/fpga/README.md diff --git a/example/VCU118/fpga/common/vivado.mk b/src/eth/example/VCU118/fpga/common/vivado.mk similarity index 100% rename from example/VCU118/fpga/common/vivado.mk rename to src/eth/example/VCU118/fpga/common/vivado.mk diff --git a/example/VCU118/fpga/fpga.xdc b/src/eth/example/VCU118/fpga/fpga.xdc similarity index 100% rename from example/VCU118/fpga/fpga.xdc rename to src/eth/example/VCU118/fpga/fpga.xdc diff --git a/example/VCU118/fpga/fpga/Makefile b/src/eth/example/VCU118/fpga/fpga/Makefile similarity index 76% rename from example/VCU118/fpga/fpga/Makefile rename to src/eth/example/VCU118/fpga/fpga/Makefile index 6e2ea36..3cce2d4 100644 --- a/example/VCU118/fpga/fpga/Makefile +++ b/src/eth/example/VCU118/fpga/fpga/Makefile @@ -11,29 +11,33 @@ FPGA_PART = xcvu9p-flga2104-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_mdio_master.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_mdio_master.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl include ../common/vivado.mk diff --git a/example/VCU118/fpga/fpga_10g/Makefile b/src/eth/example/VCU118/fpga/fpga_10g/Makefile similarity index 76% rename from example/VCU118/fpga/fpga_10g/Makefile rename to src/eth/example/VCU118/fpga/fpga_10g/Makefile index 087478e..438637c 100644 --- a/example/VCU118/fpga/fpga_10g/Makefile +++ b/src/eth/example/VCU118/fpga/fpga_10g/Makefile @@ -11,29 +11,33 @@ FPGA_PART = xcvu9p-flga2104-2L-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_mdio_master.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_mdio_master.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl include ../common/vivado.mk diff --git a/example/VCU118/fpga/ip/sgmii_pcs_pma_0.tcl b/src/eth/example/VCU118/fpga/ip/sgmii_pcs_pma_0.tcl similarity index 100% rename from example/VCU118/fpga/ip/sgmii_pcs_pma_0.tcl rename to src/eth/example/VCU118/fpga/ip/sgmii_pcs_pma_0.tcl diff --git a/src/eth/example/VCU118/fpga/lib/taxi b/src/eth/example/VCU118/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/VCU118/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/VCU118/fpga/rtl/fpga.sv b/src/eth/example/VCU118/fpga/rtl/fpga.sv similarity index 100% rename from example/VCU118/fpga/rtl/fpga.sv rename to src/eth/example/VCU118/fpga/rtl/fpga.sv diff --git a/example/VCU118/fpga/rtl/fpga_core.sv b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv similarity index 100% rename from example/VCU118/fpga/rtl/fpga_core.sv rename to src/eth/example/VCU118/fpga/rtl/fpga_core.sv diff --git a/example/VCU118/fpga/tb/fpga_core/Makefile b/src/eth/example/VCU118/fpga/tb/fpga_core/Makefile similarity index 65% rename from example/VCU118/fpga/tb/fpga_core/Makefile rename to src/eth/example/VCU118/fpga/tb/fpga_core/Makefile index 769706d..8cb7096 100644 --- a/example/VCU118/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/VCU118/fpga/tb/fpga_core/Makefile @@ -13,21 +13,25 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_mdio_master.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lss/rtl/taxi_mdio_master.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/VCU118/fpga/tb/fpga_core/baser.py b/src/eth/example/VCU118/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/VCU118/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py similarity index 89% rename from example/VCU118/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py index f1721d6..771acdf 100644 --- a/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py @@ -206,7 +206,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -229,15 +230,15 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_mdio_master.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "lss", "rtl", "taxi_mdio_master.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/XUPP3R/fpga/README.md b/src/eth/example/XUPP3R/fpga/README.md similarity index 100% rename from example/XUPP3R/fpga/README.md rename to src/eth/example/XUPP3R/fpga/README.md diff --git a/example/XUPP3R/fpga/common/vivado.mk b/src/eth/example/XUPP3R/fpga/common/vivado.mk similarity index 100% rename from example/XUPP3R/fpga/common/vivado.mk rename to src/eth/example/XUPP3R/fpga/common/vivado.mk diff --git a/example/XUPP3R/fpga/fpga_XUPP3R/Makefile b/src/eth/example/XUPP3R/fpga/fpga_XUPP3R/Makefile similarity index 88% rename from example/XUPP3R/fpga/fpga_XUPP3R/Makefile rename to src/eth/example/XUPP3R/fpga/fpga_XUPP3R/Makefile index f28122d..e612203 100644 --- a/example/XUPP3R/fpga/fpga_XUPP3R/Makefile +++ b/src/eth/example/XUPP3R/fpga/fpga_XUPP3R/Makefile @@ -11,26 +11,30 @@ FPGA_PART = xcvu9p-flgb2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_xupp3r.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga_xupp3r.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga_xupp3r.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_322.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl # Configuration #CONFIG_TCL_FILES = config.tcl diff --git a/example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile b/src/eth/example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile similarity index 88% rename from example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile rename to src/eth/example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile index fe6a622..b85ab0a 100644 --- a/example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile +++ b/src/eth/example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile @@ -11,26 +11,30 @@ FPGA_PART = xcvu9p-flgb2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_xupp3r.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga_xupp3r.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga_xupp3r.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_322.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl # Configuration #CONFIG_TCL_FILES = config.tcl diff --git a/example/XUPP3R/fpga/fpga_XUSP3S/Makefile b/src/eth/example/XUPP3R/fpga/fpga_XUSP3S/Makefile similarity index 88% rename from example/XUPP3R/fpga/fpga_XUSP3S/Makefile rename to src/eth/example/XUPP3R/fpga/fpga_XUSP3S/Makefile index c0002ce..10f5a26 100644 --- a/example/XUPP3R/fpga/fpga_XUSP3S/Makefile +++ b/src/eth/example/XUPP3R/fpga/fpga_XUSP3S/Makefile @@ -11,26 +11,30 @@ FPGA_PART = xcvu095-ffvb2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexu +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_xusp3s.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga_xusp3s.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga_xusp3s.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_322.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl # Configuration #CONFIG_TCL_FILES = config.tcl diff --git a/example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile b/src/eth/example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile similarity index 88% rename from example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile rename to src/eth/example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile index 8518251..3c36687 100644 --- a/example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile +++ b/src/eth/example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile @@ -11,26 +11,30 @@ FPGA_PART = xcvu095-ffvb2104-2-e FPGA_TOP = fpga FPGA_ARCH = virtexu +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga_xusp3s.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES = $(RTL_DIR)/fpga_xusp3s.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files XDC_FILES = ../fpga_xusp3s.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_322.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl # Configuration #CONFIG_TCL_FILES = config.tcl diff --git a/example/XUPP3R/fpga/fpga_xupp3r.xdc b/src/eth/example/XUPP3R/fpga/fpga_xupp3r.xdc similarity index 100% rename from example/XUPP3R/fpga/fpga_xupp3r.xdc rename to src/eth/example/XUPP3R/fpga/fpga_xupp3r.xdc diff --git a/example/XUPP3R/fpga/fpga_xusp3s.xdc b/src/eth/example/XUPP3R/fpga/fpga_xusp3s.xdc similarity index 100% rename from example/XUPP3R/fpga/fpga_xusp3s.xdc rename to src/eth/example/XUPP3R/fpga/fpga_xusp3s.xdc diff --git a/src/eth/example/XUPP3R/fpga/lib/taxi b/src/eth/example/XUPP3R/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/XUPP3R/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/XUPP3R/fpga/rtl/fpga_core.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv similarity index 100% rename from example/XUPP3R/fpga/rtl/fpga_core.sv rename to src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv diff --git a/example/XUPP3R/fpga/rtl/fpga_xupp3r.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_xupp3r.sv similarity index 100% rename from example/XUPP3R/fpga/rtl/fpga_xupp3r.sv rename to src/eth/example/XUPP3R/fpga/rtl/fpga_xupp3r.sv diff --git a/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv similarity index 100% rename from example/XUPP3R/fpga/rtl/fpga_xusp3s.sv rename to src/eth/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv diff --git a/example/XUPP3R/fpga/tb/fpga_core/Makefile b/src/eth/example/XUPP3R/fpga/tb/fpga_core/Makefile similarity index 70% rename from example/XUPP3R/fpga/tb/fpga_core/Makefile rename to src/eth/example/XUPP3R/fpga/tb/fpga_core/Makefile index c6e2d4a..3d1092f 100644 --- a/example/XUPP3R/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/XUPP3R/fpga/tb/fpga_core/Makefile @@ -13,19 +13,23 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/XUPP3R/fpga/tb/fpga_core/baser.py b/src/eth/example/XUPP3R/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/XUPP3R/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py similarity index 88% rename from example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py index 17a8178..1cda9a5 100644 --- a/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py @@ -145,7 +145,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -168,13 +169,13 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/ZCU102/fpga/README.md b/src/eth/example/ZCU102/fpga/README.md similarity index 100% rename from example/ZCU102/fpga/README.md rename to src/eth/example/ZCU102/fpga/README.md diff --git a/example/ZCU102/fpga/common/vivado.mk b/src/eth/example/ZCU102/fpga/common/vivado.mk similarity index 100% rename from example/ZCU102/fpga/common/vivado.mk rename to src/eth/example/ZCU102/fpga/common/vivado.mk diff --git a/example/ZCU102/fpga/fpga.xdc b/src/eth/example/ZCU102/fpga/fpga.xdc similarity index 100% rename from example/ZCU102/fpga/fpga.xdc rename to src/eth/example/ZCU102/fpga/fpga.xdc diff --git a/src/eth/example/ZCU102/fpga/fpga_10g/Makefile b/src/eth/example/ZCU102/fpga/fpga_10g/Makefile new file mode 100644 index 0000000..5209f89 --- /dev/null +++ b/src/eth/example/ZCU102/fpga/fpga_10g/Makefile @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xczu9eg-ffvb1156-2-e +FPGA_TOP = fpga +FPGA_ARCH = zynquplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + diff --git a/example/ZCU106/fpga/fpga_10g/config.tcl b/src/eth/example/ZCU102/fpga/fpga_10g/config.tcl similarity index 100% rename from example/ZCU106/fpga/fpga_10g/config.tcl rename to src/eth/example/ZCU102/fpga/fpga_10g/config.tcl diff --git a/example/ZCU102/fpga/fpga_1g/Makefile b/src/eth/example/ZCU102/fpga/fpga_1g/Makefile similarity index 53% rename from example/ZCU102/fpga/fpga_1g/Makefile rename to src/eth/example/ZCU102/fpga/fpga_1g/Makefile index 87edede..391cb54 100644 --- a/example/ZCU102/fpga/fpga_1g/Makefile +++ b/src/eth/example/ZCU102/fpga/fpga_1g/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xczu9eg-ffvb1156-2-e FPGA_TOP = fpga FPGA_ARCH = zynquplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/basex_pcs_pma_0.tcl diff --git a/example/ZCU106/fpga/fpga_1g/config.tcl b/src/eth/example/ZCU102/fpga/fpga_1g/config.tcl similarity index 100% rename from example/ZCU106/fpga/fpga_1g/config.tcl rename to src/eth/example/ZCU102/fpga/fpga_1g/config.tcl diff --git a/example/ZCU102/fpga/ip/basex_pcs_pma_0.tcl b/src/eth/example/ZCU102/fpga/ip/basex_pcs_pma_0.tcl similarity index 100% rename from example/ZCU102/fpga/ip/basex_pcs_pma_0.tcl rename to src/eth/example/ZCU102/fpga/ip/basex_pcs_pma_0.tcl diff --git a/example/ZCU102/fpga/ip/basex_pcs_pma_1.tcl b/src/eth/example/ZCU102/fpga/ip/basex_pcs_pma_1.tcl similarity index 100% rename from example/ZCU102/fpga/ip/basex_pcs_pma_1.tcl rename to src/eth/example/ZCU102/fpga/ip/basex_pcs_pma_1.tcl diff --git a/src/eth/example/ZCU102/fpga/lib/taxi b/src/eth/example/ZCU102/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/ZCU102/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/ZCU102/fpga/rtl/fpga.sv b/src/eth/example/ZCU102/fpga/rtl/fpga.sv similarity index 100% rename from example/ZCU102/fpga/rtl/fpga.sv rename to src/eth/example/ZCU102/fpga/rtl/fpga.sv diff --git a/example/ZCU102/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv similarity index 100% rename from example/ZCU102/fpga/rtl/fpga_core.sv rename to src/eth/example/ZCU102/fpga/rtl/fpga_core.sv diff --git a/example/ZCU102/fpga/tb/fpga_core/Makefile b/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile similarity index 67% rename from example/ZCU102/fpga/tb/fpga_core/Makefile rename to src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile index 16a4471..9dce2bc 100644 --- a/example/ZCU102/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile @@ -13,20 +13,24 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/ZCU102/fpga/tb/fpga_core/baser.py b/src/eth/example/ZCU102/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py similarity index 92% rename from example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 79c5246..d448588 100644 --- a/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -233,7 +233,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -257,14 +258,14 @@ def test_fpga_core(request, sfp_rate): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/ZCU106/fpga/README.md b/src/eth/example/ZCU106/fpga/README.md similarity index 100% rename from example/ZCU106/fpga/README.md rename to src/eth/example/ZCU106/fpga/README.md diff --git a/example/ZCU106/fpga/common/vivado.mk b/src/eth/example/ZCU106/fpga/common/vivado.mk similarity index 100% rename from example/ZCU106/fpga/common/vivado.mk rename to src/eth/example/ZCU106/fpga/common/vivado.mk diff --git a/example/ZCU106/fpga/fpga.xdc b/src/eth/example/ZCU106/fpga/fpga.xdc similarity index 100% rename from example/ZCU106/fpga/fpga.xdc rename to src/eth/example/ZCU106/fpga/fpga.xdc diff --git a/src/eth/example/ZCU106/fpga/fpga_10g/Makefile b/src/eth/example/ZCU106/fpga/fpga_10g/Makefile new file mode 100644 index 0000000..8c9416c --- /dev/null +++ b/src/eth/example/ZCU106/fpga/fpga_10g/Makefile @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xczu7ev-ffvc1156-2-e +FPGA_TOP = fpga +FPGA_ARCH = zynquplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + diff --git a/src/eth/example/ZCU106/fpga/fpga_10g/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g/config.tcl new file mode 100644 index 0000000..fe5171b --- /dev/null +++ b/src/eth/example/ZCU106/fpga/fpga_10g/config.tcl @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# SFP+ rate +# 0 for 1G, 1 for 10G +dict set params SFP_RATE "1" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/example/ZCU106/fpga/fpga_1g/Makefile b/src/eth/example/ZCU106/fpga/fpga_1g/Makefile similarity index 53% rename from example/ZCU106/fpga/fpga_1g/Makefile rename to src/eth/example/ZCU106/fpga/fpga_1g/Makefile index 9ab1818..5aa46a4 100644 --- a/example/ZCU106/fpga/fpga_1g/Makefile +++ b/src/eth/example/ZCU106/fpga/fpga_1g/Makefile @@ -11,23 +11,27 @@ FPGA_PART = xczu7ev-ffvc1156-2-e FPGA_TOP = fpga FPGA_ARCH = zynquplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/basex_pcs_pma_0.tcl diff --git a/src/eth/example/ZCU106/fpga/fpga_1g/config.tcl b/src/eth/example/ZCU106/fpga/fpga_1g/config.tcl new file mode 100644 index 0000000..168762b --- /dev/null +++ b/src/eth/example/ZCU106/fpga/fpga_1g/config.tcl @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# SFP+ rate +# 0 for 1G, 1 for 10G +dict set params SFP_RATE "0" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/example/ZCU106/fpga/ip/basex_pcs_pma_0.tcl b/src/eth/example/ZCU106/fpga/ip/basex_pcs_pma_0.tcl similarity index 100% rename from example/ZCU106/fpga/ip/basex_pcs_pma_0.tcl rename to src/eth/example/ZCU106/fpga/ip/basex_pcs_pma_0.tcl diff --git a/example/ZCU106/fpga/ip/basex_pcs_pma_1.tcl b/src/eth/example/ZCU106/fpga/ip/basex_pcs_pma_1.tcl similarity index 100% rename from example/ZCU106/fpga/ip/basex_pcs_pma_1.tcl rename to src/eth/example/ZCU106/fpga/ip/basex_pcs_pma_1.tcl diff --git a/src/eth/example/ZCU106/fpga/lib/taxi b/src/eth/example/ZCU106/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/ZCU106/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/ZCU106/fpga/rtl/fpga.sv b/src/eth/example/ZCU106/fpga/rtl/fpga.sv similarity index 100% rename from example/ZCU106/fpga/rtl/fpga.sv rename to src/eth/example/ZCU106/fpga/rtl/fpga.sv diff --git a/example/ZCU106/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv similarity index 100% rename from example/ZCU106/fpga/rtl/fpga_core.sv rename to src/eth/example/ZCU106/fpga/rtl/fpga_core.sv diff --git a/example/ZCU106/fpga/tb/fpga_core/Makefile b/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile similarity index 67% rename from example/ZCU106/fpga/tb/fpga_core/Makefile rename to src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile index 16a4471..9dce2bc 100644 --- a/example/ZCU106/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile @@ -13,20 +13,24 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/ZCU106/fpga/tb/fpga_core/baser.py b/src/eth/example/ZCU106/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py similarity index 91% rename from example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py index a8c0d81..d4ccfd6 100644 --- a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py @@ -215,7 +215,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -239,14 +240,14 @@ def test_fpga_core(request, sfp_rate): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/ZCU111/fpga/README.md b/src/eth/example/ZCU111/fpga/README.md similarity index 100% rename from example/ZCU111/fpga/README.md rename to src/eth/example/ZCU111/fpga/README.md diff --git a/example/ZCU111/fpga/common/vivado.mk b/src/eth/example/ZCU111/fpga/common/vivado.mk similarity index 100% rename from example/ZCU111/fpga/common/vivado.mk rename to src/eth/example/ZCU111/fpga/common/vivado.mk diff --git a/example/ZCU111/fpga/fpga.xdc b/src/eth/example/ZCU111/fpga/fpga.xdc similarity index 100% rename from example/ZCU111/fpga/fpga.xdc rename to src/eth/example/ZCU111/fpga/fpga.xdc diff --git a/src/eth/example/ZCU111/fpga/fpga/Makefile b/src/eth/example/ZCU111/fpga/fpga/Makefile new file mode 100644 index 0000000..408a583 --- /dev/null +++ b/src/eth/example/ZCU111/fpga/fpga/Makefile @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xczu28dr-ffvg1517-2-e +FPGA_TOP = fpga +FPGA_ARCH = zynquplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl + +# Configuration +#CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + diff --git a/src/eth/example/ZCU111/fpga/fpga_10g/Makefile b/src/eth/example/ZCU111/fpga/fpga_10g/Makefile new file mode 100644 index 0000000..7091d67 --- /dev/null +++ b/src/eth/example/ZCU111/fpga/fpga_10g/Makefile @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xczu28dr-ffvg1517-2-e +FPGA_TOP = fpga +FPGA_ARCH = zynquplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl + +# Configuration +#CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + diff --git a/src/eth/example/ZCU111/fpga/lib/taxi b/src/eth/example/ZCU111/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/ZCU111/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/ZCU111/fpga/rtl/fpga.sv b/src/eth/example/ZCU111/fpga/rtl/fpga.sv similarity index 100% rename from example/ZCU111/fpga/rtl/fpga.sv rename to src/eth/example/ZCU111/fpga/rtl/fpga.sv diff --git a/example/ZCU111/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv similarity index 100% rename from example/ZCU111/fpga/rtl/fpga_core.sv rename to src/eth/example/ZCU111/fpga/rtl/fpga_core.sv diff --git a/example/ZCU111/fpga/tb/fpga_core/Makefile b/src/eth/example/ZCU111/fpga/tb/fpga_core/Makefile similarity index 67% rename from example/ZCU111/fpga/tb/fpga_core/Makefile rename to src/eth/example/ZCU111/fpga/tb/fpga_core/Makefile index 8d49e56..5ae5899 100644 --- a/example/ZCU111/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/ZCU111/fpga/tb/fpga_core/Makefile @@ -13,20 +13,24 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f -VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/ZCU111/fpga/tb/fpga_core/baser.py b/src/eth/example/ZCU111/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/ZCU111/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py similarity index 87% rename from example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py index a1980c2..3dc9948 100644 --- a/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py @@ -147,7 +147,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -170,14 +171,14 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), - os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/example/fb2CG/fpga/README.md b/src/eth/example/fb2CG/fpga/README.md similarity index 100% rename from example/fb2CG/fpga/README.md rename to src/eth/example/fb2CG/fpga/README.md diff --git a/example/fb2CG/fpga/common/vivado.mk b/src/eth/example/fb2CG/fpga/common/vivado.mk similarity index 100% rename from example/fb2CG/fpga/common/vivado.mk rename to src/eth/example/fb2CG/fpga/common/vivado.mk diff --git a/example/fb2CG/fpga/fpga.xdc b/src/eth/example/fb2CG/fpga/fpga.xdc similarity index 100% rename from example/fb2CG/fpga/fpga.xdc rename to src/eth/example/fb2CG/fpga/fpga.xdc diff --git a/example/fb2CG/fpga/fpga_10g/Makefile b/src/eth/example/fb2CG/fpga/fpga/Makefile similarity index 79% rename from example/fb2CG/fpga/fpga_10g/Makefile rename to src/eth/example/fb2CG/fpga/fpga/Makefile index a6bdd09..b1ef597 100644 --- a/example/fb2CG/fpga/fpga_10g/Makefile +++ b/src/eth/example/fb2CG/fpga/fpga/Makefile @@ -11,24 +11,28 @@ FPGA_PART = xcku15p-ffve1760-2-e FPGA_TOP = fpga FPGA_ARCH = kintexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_led_sreg.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_led_sreg.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/fb2CG/fpga/fpga/Makefile b/src/eth/example/fb2CG/fpga/fpga_10g/Makefile similarity index 79% rename from example/fb2CG/fpga/fpga/Makefile rename to src/eth/example/fb2CG/fpga/fpga_10g/Makefile index 18e8464..ef2ead5 100644 --- a/example/fb2CG/fpga/fpga/Makefile +++ b/src/eth/example/fb2CG/fpga/fpga_10g/Makefile @@ -11,24 +11,28 @@ FPGA_PART = xcku15p-ffve1760-2-e FPGA_TOP = fpga FPGA_ARCH = kintexuplus +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + # Files for synthesis -SYN_FILES = ../rtl/fpga.sv -SYN_FILES += ../rtl/fpga_core.sv -SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv -SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv -SYN_FILES += ../lib/taxi/rtl/io/taxi_led_sreg.sv +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_led_sreg.sv # XDC files XDC_FILES = ../fpga.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl -XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/src/eth/example/fb2CG/fpga/lib/taxi b/src/eth/example/fb2CG/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/fb2CG/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/example/fb2CG/fpga/rtl/fpga.sv b/src/eth/example/fb2CG/fpga/rtl/fpga.sv similarity index 100% rename from example/fb2CG/fpga/rtl/fpga.sv rename to src/eth/example/fb2CG/fpga/rtl/fpga.sv diff --git a/example/fb2CG/fpga/rtl/fpga_core.sv b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv similarity index 100% rename from example/fb2CG/fpga/rtl/fpga_core.sv rename to src/eth/example/fb2CG/fpga/rtl/fpga_core.sv diff --git a/example/Nexus_K3P_S/fpga/tb/fpga_core/Makefile b/src/eth/example/fb2CG/fpga/tb/fpga_core/Makefile similarity index 75% rename from example/Nexus_K3P_S/fpga/tb/fpga_core/Makefile rename to src/eth/example/fb2CG/fpga/tb/fpga_core/Makefile index b42edfd..ad83ed9 100644 --- a/example/Nexus_K3P_S/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/fb2CG/fpga/tb/fpga_core/Makefile @@ -13,16 +13,21 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = fpga_core COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../rtl/$(DUT).sv -VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv -VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_led_sreg.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/src/eth/example/fb2CG/fpga/tb/fpga_core/baser.py b/src/eth/example/fb2CG/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/fb2CG/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py similarity index 89% rename from example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py rename to src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py index f344c66..cf67911 100644 --- a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py @@ -142,7 +142,8 @@ async def run_test(dut): tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -165,12 +166,12 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), - os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), - os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_led_sreg.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_led_sreg.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/src/eth/lib/taxi b/src/eth/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/eth/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/rtl/eth/taxi_axis_baser_rx_64.sv b/src/eth/rtl/taxi_axis_baser_rx_64.sv similarity index 100% rename from rtl/eth/taxi_axis_baser_rx_64.sv rename to src/eth/rtl/taxi_axis_baser_rx_64.sv diff --git a/rtl/eth/taxi_axis_baser_tx_64.sv b/src/eth/rtl/taxi_axis_baser_tx_64.sv similarity index 100% rename from rtl/eth/taxi_axis_baser_tx_64.sv rename to src/eth/rtl/taxi_axis_baser_tx_64.sv diff --git a/rtl/eth/taxi_axis_gmii_rx.sv b/src/eth/rtl/taxi_axis_gmii_rx.sv similarity index 100% rename from rtl/eth/taxi_axis_gmii_rx.sv rename to src/eth/rtl/taxi_axis_gmii_rx.sv diff --git a/rtl/eth/taxi_axis_gmii_tx.sv b/src/eth/rtl/taxi_axis_gmii_tx.sv similarity index 100% rename from rtl/eth/taxi_axis_gmii_tx.sv rename to src/eth/rtl/taxi_axis_gmii_tx.sv diff --git a/rtl/eth/taxi_axis_xgmii_rx_32.sv b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv similarity index 100% rename from rtl/eth/taxi_axis_xgmii_rx_32.sv rename to src/eth/rtl/taxi_axis_xgmii_rx_32.sv diff --git a/rtl/eth/taxi_axis_xgmii_rx_64.sv b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv similarity index 100% rename from rtl/eth/taxi_axis_xgmii_rx_64.sv rename to src/eth/rtl/taxi_axis_xgmii_rx_64.sv diff --git a/rtl/eth/taxi_axis_xgmii_tx_32.sv b/src/eth/rtl/taxi_axis_xgmii_tx_32.sv similarity index 100% rename from rtl/eth/taxi_axis_xgmii_tx_32.sv rename to src/eth/rtl/taxi_axis_xgmii_tx_32.sv diff --git a/rtl/eth/taxi_axis_xgmii_tx_64.sv b/src/eth/rtl/taxi_axis_xgmii_tx_64.sv similarity index 100% rename from rtl/eth/taxi_axis_xgmii_tx_64.sv rename to src/eth/rtl/taxi_axis_xgmii_tx_64.sv diff --git a/rtl/eth/taxi_eth_mac_10g.f b/src/eth/rtl/taxi_eth_mac_10g.f similarity index 65% rename from rtl/eth/taxi_eth_mac_10g.f rename to src/eth/rtl/taxi_eth_mac_10g.f index 5d5508a..7e84572 100644 --- a/rtl/eth/taxi_eth_mac_10g.f +++ b/src/eth/rtl/taxi_eth_mac_10g.f @@ -8,6 +8,6 @@ taxi_mac_ctrl_tx.sv taxi_mac_ctrl_rx.sv taxi_mac_pause_ctrl_tx.sv taxi_mac_pause_ctrl_rx.sv -../lfsr/taxi_lfsr.sv -../axis/taxi_axis_if.sv -../sync/taxi_sync_signal.sv +../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv +../lib/taxi/src/sync/rtl/taxi_sync_signal.sv diff --git a/rtl/eth/taxi_eth_mac_10g.sv b/src/eth/rtl/taxi_eth_mac_10g.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_10g.sv rename to src/eth/rtl/taxi_eth_mac_10g.sv diff --git a/src/eth/rtl/taxi_eth_mac_10g_fifo.f b/src/eth/rtl/taxi_eth_mac_10g_fifo.f new file mode 100644 index 0000000..567e92f --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_10g_fifo.f @@ -0,0 +1,4 @@ +taxi_eth_mac_10g_fifo.sv +taxi_eth_mac_10g.f +../lib/taxi/src/ptp/rtl/taxi_ptp_clock_cdc.sv +../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_10g_fifo.sv b/src/eth/rtl/taxi_eth_mac_10g_fifo.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_10g_fifo.sv rename to src/eth/rtl/taxi_eth_mac_10g_fifo.sv diff --git a/rtl/eth/taxi_eth_mac_1g.f b/src/eth/rtl/taxi_eth_mac_1g.f similarity index 58% rename from rtl/eth/taxi_eth_mac_1g.f rename to src/eth/rtl/taxi_eth_mac_1g.f index 1d67ac7..8c6ce1d 100644 --- a/rtl/eth/taxi_eth_mac_1g.f +++ b/src/eth/rtl/taxi_eth_mac_1g.f @@ -6,6 +6,6 @@ taxi_mac_ctrl_tx.sv taxi_mac_ctrl_rx.sv taxi_mac_pause_ctrl_tx.sv taxi_mac_pause_ctrl_rx.sv -../lfsr/taxi_lfsr.sv -../axis/taxi_axis_if.sv -../sync/taxi_sync_signal.sv +../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv +../lib/taxi/src/sync/rtl/taxi_sync_signal.sv diff --git a/rtl/eth/taxi_eth_mac_1g.sv b/src/eth/rtl/taxi_eth_mac_1g.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_1g.sv rename to src/eth/rtl/taxi_eth_mac_1g.sv diff --git a/src/eth/rtl/taxi_eth_mac_1g_fifo.f b/src/eth/rtl/taxi_eth_mac_1g_fifo.f new file mode 100644 index 0000000..c7070a9 --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_1g_fifo.f @@ -0,0 +1,3 @@ +taxi_eth_mac_1g_fifo.sv +taxi_eth_mac_1g.f +../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_1g_fifo.sv b/src/eth/rtl/taxi_eth_mac_1g_fifo.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_1g_fifo.sv rename to src/eth/rtl/taxi_eth_mac_1g_fifo.sv diff --git a/rtl/eth/taxi_eth_mac_1g_gmii.f b/src/eth/rtl/taxi_eth_mac_1g_gmii.f similarity index 100% rename from rtl/eth/taxi_eth_mac_1g_gmii.f rename to src/eth/rtl/taxi_eth_mac_1g_gmii.f diff --git a/rtl/eth/taxi_eth_mac_1g_gmii.sv b/src/eth/rtl/taxi_eth_mac_1g_gmii.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_1g_gmii.sv rename to src/eth/rtl/taxi_eth_mac_1g_gmii.sv diff --git a/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f b/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f new file mode 100644 index 0000000..45753c5 --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f @@ -0,0 +1,3 @@ +taxi_eth_mac_1g_gmii_fifo.sv +taxi_eth_mac_1g_gmii.f +../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv b/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv rename to src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii.f b/src/eth/rtl/taxi_eth_mac_1g_rgmii.f similarity index 100% rename from rtl/eth/taxi_eth_mac_1g_rgmii.f rename to src/eth/rtl/taxi_eth_mac_1g_rgmii.f diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii.sv b/src/eth/rtl/taxi_eth_mac_1g_rgmii.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_1g_rgmii.sv rename to src/eth/rtl/taxi_eth_mac_1g_rgmii.sv diff --git a/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f b/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f new file mode 100644 index 0000000..ff8c144 --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f @@ -0,0 +1,3 @@ +taxi_eth_mac_1g_rgmii_fifo.sv +taxi_eth_mac_1g_rgmii.f +../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv b/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv rename to src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv diff --git a/rtl/eth/taxi_eth_mac_mii.f b/src/eth/rtl/taxi_eth_mac_mii.f similarity index 100% rename from rtl/eth/taxi_eth_mac_mii.f rename to src/eth/rtl/taxi_eth_mac_mii.f diff --git a/rtl/eth/taxi_eth_mac_mii.sv b/src/eth/rtl/taxi_eth_mac_mii.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_mii.sv rename to src/eth/rtl/taxi_eth_mac_mii.sv diff --git a/src/eth/rtl/taxi_eth_mac_mii_fifo.f b/src/eth/rtl/taxi_eth_mac_mii_fifo.f new file mode 100644 index 0000000..ac4e09d --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_mii_fifo.f @@ -0,0 +1,3 @@ +taxi_eth_mac_mii_fifo.sv +taxi_eth_mac_mii.f +../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_mii_fifo.sv b/src/eth/rtl/taxi_eth_mac_mii_fifo.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_mii_fifo.sv rename to src/eth/rtl/taxi_eth_mac_mii_fifo.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g.f b/src/eth/rtl/taxi_eth_mac_phy_10g.f similarity index 80% rename from rtl/eth/taxi_eth_mac_phy_10g.f rename to src/eth/rtl/taxi_eth_mac_phy_10g.f index 6749f8a..e07e525 100644 --- a/rtl/eth/taxi_eth_mac_phy_10g.f +++ b/src/eth/rtl/taxi_eth_mac_phy_10g.f @@ -6,4 +6,4 @@ taxi_mac_ctrl_tx.sv taxi_mac_ctrl_rx.sv taxi_mac_pause_ctrl_tx.sv taxi_mac_pause_ctrl_rx.sv -../sync/taxi_sync_signal.sv +../lib/taxi/src/sync/rtl/taxi_sync_signal.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g.sv b/src/eth/rtl/taxi_eth_mac_phy_10g.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_phy_10g.sv rename to src/eth/rtl/taxi_eth_mac_phy_10g.sv diff --git a/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.f b/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.f new file mode 100644 index 0000000..68d3bba --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.f @@ -0,0 +1,4 @@ +taxi_eth_mac_phy_10g_fifo.sv +taxi_eth_mac_phy_10g.f +../lib/taxi/src/ptp/rtl/taxi_ptp_clock_cdc.sv +../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_phy_10g_fifo.sv b/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_phy_10g_fifo.sv rename to src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv diff --git a/src/eth/rtl/taxi_eth_mac_phy_10g_rx.f b/src/eth/rtl/taxi_eth_mac_phy_10g_rx.f new file mode 100644 index 0000000..7d9a7a3 --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_phy_10g_rx.f @@ -0,0 +1,5 @@ +taxi_eth_mac_phy_10g_rx.sv +taxi_eth_phy_10g_rx_if.f +taxi_axis_baser_rx_64.sv +../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g_rx.sv b/src/eth/rtl/taxi_eth_mac_phy_10g_rx.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_phy_10g_rx.sv rename to src/eth/rtl/taxi_eth_mac_phy_10g_rx.sv diff --git a/src/eth/rtl/taxi_eth_mac_phy_10g_tx.f b/src/eth/rtl/taxi_eth_mac_phy_10g_tx.f new file mode 100644 index 0000000..f39171d --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_phy_10g_tx.f @@ -0,0 +1,5 @@ +taxi_eth_mac_phy_10g_tx.sv +taxi_eth_phy_10g_tx_if.f +taxi_axis_baser_tx_64.sv +../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g_tx.sv b/src/eth/rtl/taxi_eth_mac_phy_10g_tx.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_phy_10g_tx.sv rename to src/eth/rtl/taxi_eth_mac_phy_10g_tx.sv diff --git a/src/eth/rtl/taxi_eth_mac_stats.f b/src/eth/rtl/taxi_eth_mac_stats.f new file mode 100644 index 0000000..bcc57c2 --- /dev/null +++ b/src/eth/rtl/taxi_eth_mac_stats.f @@ -0,0 +1,4 @@ +taxi_eth_mac_stats.sv +../lib/taxi/src/axis/rtl/taxi_axis_async_fifo.f +../lib/taxi/src/axis/rtl/taxi_axis_arb_mux.f +../lib/taxi/src/stats/rtl/taxi_stats_collect.sv diff --git a/rtl/eth/taxi_eth_mac_stats.sv b/src/eth/rtl/taxi_eth_mac_stats.sv similarity index 100% rename from rtl/eth/taxi_eth_mac_stats.sv rename to src/eth/rtl/taxi_eth_mac_stats.sv diff --git a/rtl/eth/taxi_eth_phy_10g.f b/src/eth/rtl/taxi_eth_phy_10g.f similarity index 100% rename from rtl/eth/taxi_eth_phy_10g.f rename to src/eth/rtl/taxi_eth_phy_10g.f diff --git a/rtl/eth/taxi_eth_phy_10g.sv b/src/eth/rtl/taxi_eth_phy_10g.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g.sv rename to src/eth/rtl/taxi_eth_phy_10g.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx.f b/src/eth/rtl/taxi_eth_phy_10g_rx.f similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_rx.f rename to src/eth/rtl/taxi_eth_phy_10g_rx.f diff --git a/rtl/eth/taxi_eth_phy_10g_rx.sv b/src/eth/rtl/taxi_eth_phy_10g_rx.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_rx.sv rename to src/eth/rtl/taxi_eth_phy_10g_rx.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv b/src/eth/rtl/taxi_eth_phy_10g_rx_ber_mon.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv rename to src/eth/rtl/taxi_eth_phy_10g_rx_ber_mon.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv b/src/eth/rtl/taxi_eth_phy_10g_rx_frame_sync.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv rename to src/eth/rtl/taxi_eth_phy_10g_rx_frame_sync.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx_if.f b/src/eth/rtl/taxi_eth_phy_10g_rx_if.f similarity index 76% rename from rtl/eth/taxi_eth_phy_10g_rx_if.f rename to src/eth/rtl/taxi_eth_phy_10g_rx_if.f index a3453b3..9da31bc 100644 --- a/rtl/eth/taxi_eth_phy_10g_rx_if.f +++ b/src/eth/rtl/taxi_eth_phy_10g_rx_if.f @@ -2,4 +2,4 @@ taxi_eth_phy_10g_rx_if.sv taxi_eth_phy_10g_rx_ber_mon.sv taxi_eth_phy_10g_rx_frame_sync.sv taxi_eth_phy_10g_rx_watchdog.sv -../lfsr/taxi_lfsr.sv +../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx_if.sv b/src/eth/rtl/taxi_eth_phy_10g_rx_if.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_rx_if.sv rename to src/eth/rtl/taxi_eth_phy_10g_rx_if.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv b/src/eth/rtl/taxi_eth_phy_10g_rx_watchdog.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv rename to src/eth/rtl/taxi_eth_phy_10g_rx_watchdog.sv diff --git a/rtl/eth/taxi_eth_phy_10g_tx.f b/src/eth/rtl/taxi_eth_phy_10g_tx.f similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_tx.f rename to src/eth/rtl/taxi_eth_phy_10g_tx.f diff --git a/rtl/eth/taxi_eth_phy_10g_tx.sv b/src/eth/rtl/taxi_eth_phy_10g_tx.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_tx.sv rename to src/eth/rtl/taxi_eth_phy_10g_tx.sv diff --git a/src/eth/rtl/taxi_eth_phy_10g_tx_if.f b/src/eth/rtl/taxi_eth_phy_10g_tx_if.f new file mode 100644 index 0000000..a077799 --- /dev/null +++ b/src/eth/rtl/taxi_eth_phy_10g_tx_if.f @@ -0,0 +1,2 @@ +taxi_eth_phy_10g_tx_if.sv +../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv diff --git a/rtl/eth/taxi_eth_phy_10g_tx_if.sv b/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv similarity index 100% rename from rtl/eth/taxi_eth_phy_10g_tx_if.sv rename to src/eth/rtl/taxi_eth_phy_10g_tx_if.sv diff --git a/src/eth/rtl/taxi_gmii_phy_if.f b/src/eth/rtl/taxi_gmii_phy_if.f new file mode 100644 index 0000000..9015aab --- /dev/null +++ b/src/eth/rtl/taxi_gmii_phy_if.f @@ -0,0 +1,5 @@ +taxi_gmii_phy_if.sv +../lib/taxi/src/io/rtl/taxi_ssio_sdr_in.sv +../lib/taxi/src/io/rtl/taxi_ssio_sdr_out.sv +../lib/taxi/src/io/rtl/taxi_oddr.sv +../lib/taxi/src/sync/rtl/taxi_sync_reset.sv diff --git a/rtl/eth/taxi_gmii_phy_if.sv b/src/eth/rtl/taxi_gmii_phy_if.sv similarity index 100% rename from rtl/eth/taxi_gmii_phy_if.sv rename to src/eth/rtl/taxi_gmii_phy_if.sv diff --git a/rtl/eth/taxi_mac_ctrl_rx.sv b/src/eth/rtl/taxi_mac_ctrl_rx.sv similarity index 100% rename from rtl/eth/taxi_mac_ctrl_rx.sv rename to src/eth/rtl/taxi_mac_ctrl_rx.sv diff --git a/rtl/eth/taxi_mac_ctrl_tx.sv b/src/eth/rtl/taxi_mac_ctrl_tx.sv similarity index 100% rename from rtl/eth/taxi_mac_ctrl_tx.sv rename to src/eth/rtl/taxi_mac_ctrl_tx.sv diff --git a/rtl/eth/taxi_mac_pause_ctrl_rx.sv b/src/eth/rtl/taxi_mac_pause_ctrl_rx.sv similarity index 100% rename from rtl/eth/taxi_mac_pause_ctrl_rx.sv rename to src/eth/rtl/taxi_mac_pause_ctrl_rx.sv diff --git a/rtl/eth/taxi_mac_pause_ctrl_tx.sv b/src/eth/rtl/taxi_mac_pause_ctrl_tx.sv similarity index 100% rename from rtl/eth/taxi_mac_pause_ctrl_tx.sv rename to src/eth/rtl/taxi_mac_pause_ctrl_tx.sv diff --git a/src/eth/rtl/taxi_mii_phy_if.f b/src/eth/rtl/taxi_mii_phy_if.f new file mode 100644 index 0000000..79bb5b8 --- /dev/null +++ b/src/eth/rtl/taxi_mii_phy_if.f @@ -0,0 +1,3 @@ +taxi_mii_phy_if.sv +../lib/taxi/src/io/rtl/taxi_ssio_sdr_in.sv +../lib/taxi/src/sync/rtl/taxi_sync_reset.sv diff --git a/rtl/eth/taxi_mii_phy_if.sv b/src/eth/rtl/taxi_mii_phy_if.sv similarity index 100% rename from rtl/eth/taxi_mii_phy_if.sv rename to src/eth/rtl/taxi_mii_phy_if.sv diff --git a/src/eth/rtl/taxi_rgmii_phy_if.f b/src/eth/rtl/taxi_rgmii_phy_if.f new file mode 100644 index 0000000..2f0606e --- /dev/null +++ b/src/eth/rtl/taxi_rgmii_phy_if.f @@ -0,0 +1,5 @@ +taxi_rgmii_phy_if.sv +../lib/taxi/src/io/rtl/taxi_ssio_ddr_in.sv +../lib/taxi/src/io/rtl/taxi_iddr.sv +../lib/taxi/src/io/rtl/taxi_oddr.sv +../lib/taxi/src/sync/rtl/taxi_sync_reset.sv diff --git a/rtl/eth/taxi_rgmii_phy_if.sv b/src/eth/rtl/taxi_rgmii_phy_if.sv similarity index 100% rename from rtl/eth/taxi_rgmii_phy_if.sv rename to src/eth/rtl/taxi_rgmii_phy_if.sv diff --git a/rtl/eth/taxi_xgmii_baser_dec_64.sv b/src/eth/rtl/taxi_xgmii_baser_dec_64.sv similarity index 100% rename from rtl/eth/taxi_xgmii_baser_dec_64.sv rename to src/eth/rtl/taxi_xgmii_baser_dec_64.sv diff --git a/rtl/eth/taxi_xgmii_baser_enc_64.sv b/src/eth/rtl/taxi_xgmii_baser_enc_64.sv similarity index 100% rename from rtl/eth/taxi_xgmii_baser_enc_64.sv rename to src/eth/rtl/taxi_xgmii_baser_enc_64.sv diff --git a/rtl/eth/us/taxi_eth_mac_25g_us.f b/src/eth/rtl/us/taxi_eth_mac_25g_us.f similarity index 100% rename from rtl/eth/us/taxi_eth_mac_25g_us.f rename to src/eth/rtl/us/taxi_eth_mac_25g_us.f diff --git a/rtl/eth/us/taxi_eth_mac_25g_us.sv b/src/eth/rtl/us/taxi_eth_mac_25g_us.sv similarity index 100% rename from rtl/eth/us/taxi_eth_mac_25g_us.sv rename to src/eth/rtl/us/taxi_eth_mac_25g_us.sv diff --git a/rtl/eth/us/taxi_eth_mac_25g_us_ch.sv b/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv similarity index 100% rename from rtl/eth/us/taxi_eth_mac_25g_us_ch.sv rename to src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f new file mode 100644 index 0000000..83f7d41 --- /dev/null +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f @@ -0,0 +1,2 @@ +taxi_eth_phy_25g_us_gt.sv +../lib/taxi/src/sync/rtl/taxi_sync_reset.sv diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gt.sv b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gt.sv rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_161.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_322.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_322.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl diff --git a/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl similarity index 100% rename from rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_322.tcl rename to src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl diff --git a/syn/vivado/taxi_eth_mac_fifo.tcl b/src/eth/syn/vivado/taxi_eth_mac_fifo.tcl similarity index 100% rename from syn/vivado/taxi_eth_mac_fifo.tcl rename to src/eth/syn/vivado/taxi_eth_mac_fifo.tcl diff --git a/syn/vivado/taxi_rgmii_phy_if.tcl b/src/eth/syn/vivado/taxi_rgmii_phy_if.tcl similarity index 100% rename from syn/vivado/taxi_rgmii_phy_if.tcl rename to src/eth/syn/vivado/taxi_rgmii_phy_if.tcl diff --git a/tb/eth/baser.py b/src/eth/tb/baser.py similarity index 100% rename from tb/eth/baser.py rename to src/eth/tb/baser.py diff --git a/tb/eth/taxi_axis_baser_rx_64/Makefile b/src/eth/tb/taxi_axis_baser_rx_64/Makefile similarity index 85% rename from tb/eth/taxi_axis_baser_rx_64/Makefile rename to src/eth/tb/taxi_axis_baser_rx_64/Makefile index 61c9fc8..04318b8 100644 --- a/tb/eth/taxi_axis_baser_rx_64/Makefile +++ b/src/eth/tb/taxi_axis_baser_rx_64/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_baser_rx_64 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_baser_rx_64/baser.py b/src/eth/tb/taxi_axis_baser_rx_64/baser.py similarity index 100% rename from tb/eth/taxi_axis_baser_rx_64/baser.py rename to src/eth/tb/taxi_axis_baser_rx_64/baser.py diff --git a/tb/eth/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py b/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py similarity index 96% rename from tb/eth/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py rename to src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py index 700495d..1b6a045 100644 --- a/tb/eth/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py +++ b/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py @@ -282,7 +282,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -305,9 +307,9 @@ def test_taxi_axis_baser_rx_64(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv b/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv similarity index 100% rename from tb/eth/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv rename to src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv diff --git a/tb/eth/taxi_axis_baser_tx_64/Makefile b/src/eth/tb/taxi_axis_baser_tx_64/Makefile similarity index 87% rename from tb/eth/taxi_axis_baser_tx_64/Makefile rename to src/eth/tb/taxi_axis_baser_tx_64/Makefile index 3b5ebd9..805abee 100644 --- a/tb/eth/taxi_axis_baser_tx_64/Makefile +++ b/src/eth/tb/taxi_axis_baser_tx_64/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_baser_tx_64 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_baser_tx_64/baser.py b/src/eth/tb/taxi_axis_baser_tx_64/baser.py similarity index 100% rename from tb/eth/taxi_axis_baser_tx_64/baser.py rename to src/eth/tb/taxi_axis_baser_tx_64/baser.py diff --git a/tb/eth/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py b/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py similarity index 97% rename from tb/eth/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py rename to src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py index c26e42b..21385f8 100644 --- a/tb/eth/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py +++ b/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py @@ -497,7 +497,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -521,9 +523,9 @@ def test_taxi_axis_baser_tx_64(request, dic_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv b/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv similarity index 100% rename from tb/eth/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv rename to src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv diff --git a/tb/eth/taxi_axis_gmii_rx/Makefile b/src/eth/tb/taxi_axis_gmii_rx/Makefile similarity index 85% rename from tb/eth/taxi_axis_gmii_rx/Makefile rename to src/eth/tb/taxi_axis_gmii_rx/Makefile index fc1c7d2..7fb19e6 100644 --- a/tb/eth/taxi_axis_gmii_rx/Makefile +++ b/src/eth/tb/taxi_axis_gmii_rx/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_gmii_rx COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py b/src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py similarity index 96% rename from tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py rename to src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py index 79c93cb..4bd1acc 100644 --- a/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py +++ b/src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py @@ -306,7 +306,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -329,9 +331,9 @@ def test_axis_gmii_rx(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv b/src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv similarity index 100% rename from tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv rename to src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv diff --git a/tb/eth/taxi_axis_gmii_tx/Makefile b/src/eth/tb/taxi_axis_gmii_tx/Makefile similarity index 86% rename from tb/eth/taxi_axis_gmii_tx/Makefile rename to src/eth/tb/taxi_axis_gmii_tx/Makefile index 5a0b33a..bfe2b95 100644 --- a/tb/eth/taxi_axis_gmii_tx/Makefile +++ b/src/eth/tb/taxi_axis_gmii_tx/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_gmii_tx COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.py b/src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.py similarity index 97% rename from tb/eth/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.py rename to src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.py index 74389a4..25f364c 100644 --- a/tb/eth/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.py +++ b/src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.py @@ -420,7 +420,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -443,9 +445,9 @@ def test_taxi_axis_gmii_tx(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.sv b/src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.sv similarity index 100% rename from tb/eth/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.sv rename to src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.sv diff --git a/tb/eth/taxi_axis_xgmii_rx_32/Makefile b/src/eth/tb/taxi_axis_xgmii_rx_32/Makefile similarity index 85% rename from tb/eth/taxi_axis_xgmii_rx_32/Makefile rename to src/eth/tb/taxi_axis_xgmii_rx_32/Makefile index 3db3c8d..0490b87 100644 --- a/tb/eth/taxi_axis_xgmii_rx_32/Makefile +++ b/src/eth/tb/taxi_axis_xgmii_rx_32/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_xgmii_rx_32 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py b/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py similarity index 96% rename from tb/eth/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py rename to src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py index e2e5112..256f060 100644 --- a/tb/eth/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py +++ b/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py @@ -270,7 +270,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -293,9 +295,9 @@ def test_taxi_axis_xgmii_rx_32(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv b/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv similarity index 100% rename from tb/eth/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv rename to src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv diff --git a/tb/eth/taxi_axis_xgmii_rx_64/Makefile b/src/eth/tb/taxi_axis_xgmii_rx_64/Makefile similarity index 86% rename from tb/eth/taxi_axis_xgmii_rx_64/Makefile rename to src/eth/tb/taxi_axis_xgmii_rx_64/Makefile index af7e63f..1c855dc 100644 --- a/tb/eth/taxi_axis_xgmii_rx_64/Makefile +++ b/src/eth/tb/taxi_axis_xgmii_rx_64/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_xgmii_rx_64 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py b/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py similarity index 96% rename from tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py rename to src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py index ae5b09f..8ce8bd6 100644 --- a/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py +++ b/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py @@ -271,7 +271,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -294,9 +296,9 @@ def test_taxi_axis_xgmii_rx_64(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv b/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv similarity index 100% rename from tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv rename to src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv diff --git a/tb/eth/taxi_axis_xgmii_tx_32/Makefile b/src/eth/tb/taxi_axis_xgmii_tx_32/Makefile similarity index 86% rename from tb/eth/taxi_axis_xgmii_tx_32/Makefile rename to src/eth/tb/taxi_axis_xgmii_tx_32/Makefile index da1281c..cb48932 100644 --- a/tb/eth/taxi_axis_xgmii_tx_32/Makefile +++ b/src/eth/tb/taxi_axis_xgmii_tx_32/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_xgmii_tx_32 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py b/src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py similarity index 97% rename from tb/eth/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py rename to src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py index fb4f85f..67e0e25 100644 --- a/tb/eth/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py +++ b/src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py @@ -484,7 +484,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -508,9 +510,9 @@ def test_taxi_axis_xgmii_tx_32(request, dic_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv b/src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv similarity index 100% rename from tb/eth/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv rename to src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv diff --git a/tb/eth/taxi_axis_xgmii_tx_64/Makefile b/src/eth/tb/taxi_axis_xgmii_tx_64/Makefile similarity index 87% rename from tb/eth/taxi_axis_xgmii_tx_64/Makefile rename to src/eth/tb/taxi_axis_xgmii_tx_64/Makefile index 74195b3..56a8c32 100644 --- a/tb/eth/taxi_axis_xgmii_tx_64/Makefile +++ b/src/eth/tb/taxi_axis_xgmii_tx_64/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_axis_xgmii_tx_64 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.py b/src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.py similarity index 97% rename from tb/eth/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.py rename to src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.py index 36b1a22..3a38801 100644 --- a/tb/eth/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.py +++ b/src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.py @@ -486,7 +486,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -510,9 +512,9 @@ def test_taxi_axis_xgmii_tx_64(request, enable_dic): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.sv b/src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.sv similarity index 100% rename from tb/eth/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.sv rename to src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.sv diff --git a/tb/eth/taxi_eth_mac_10g/Makefile b/src/eth/tb/taxi_eth_mac_10g/Makefile similarity index 94% rename from tb/eth/taxi_eth_mac_10g/Makefile rename to src/eth/tb/taxi_eth_mac_10g/Makefile index a2274bd..c7e88b2 100644 --- a/tb/eth/taxi_eth_mac_10g/Makefile +++ b/src/eth/tb/taxi_eth_mac_10g/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_10g COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py b/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py similarity index 98% rename from tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py rename to src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py index ac6372d..2e3c750 100644 --- a/tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py +++ b/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py @@ -712,7 +712,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -737,7 +739,7 @@ def test_taxi_eth_mac_10g(request, data_w, dic_en, pfc_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv b/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv similarity index 100% rename from tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv rename to src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv diff --git a/tb/eth/taxi_eth_mac_10g_fifo/Makefile b/src/eth/tb/taxi_eth_mac_10g_fifo/Makefile similarity index 95% rename from tb/eth/taxi_eth_mac_10g_fifo/Makefile rename to src/eth/tb/taxi_eth_mac_10g_fifo/Makefile index 49e256b..a935316 100644 --- a/tb/eth/taxi_eth_mac_10g_fifo/Makefile +++ b/src/eth/tb/taxi_eth_mac_10g_fifo/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_10g_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py b/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py similarity index 98% rename from tb/eth/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py rename to src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py index 548e899..8a5ba7b 100644 --- a/tb/eth/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py +++ b/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py @@ -311,7 +311,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -336,7 +338,7 @@ def test_taxi_eth_mac_10g_fifo(request, data_w, dic_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv b/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv similarity index 100% rename from tb/eth/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv rename to src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv diff --git a/tb/eth/taxi_eth_mac_1g/Makefile b/src/eth/tb/taxi_eth_mac_1g/Makefile similarity index 93% rename from tb/eth/taxi_eth_mac_1g/Makefile rename to src/eth/tb/taxi_eth_mac_1g/Makefile index 4694234..c6fef87 100644 --- a/tb/eth/taxi_eth_mac_1g/Makefile +++ b/src/eth/tb/taxi_eth_mac_1g/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_1g COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py b/src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py similarity index 99% rename from tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py rename to src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py index 32502d4..e574637 100644 --- a/tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py +++ b/src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py @@ -800,7 +800,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -824,7 +826,7 @@ def test_taxi_eth_mac_1g(request, pfc_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv b/src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv similarity index 100% rename from tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv rename to src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv diff --git a/tb/eth/taxi_eth_mac_1g_fifo/Makefile b/src/eth/tb/taxi_eth_mac_1g_fifo/Makefile similarity index 95% rename from tb/eth/taxi_eth_mac_1g_fifo/Makefile rename to src/eth/tb/taxi_eth_mac_1g_fifo/Makefile index 318e5ed..3db6189 100644 --- a/tb/eth/taxi_eth_mac_1g_fifo/Makefile +++ b/src/eth/tb/taxi_eth_mac_1g_fifo/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_1g_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py b/src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py similarity index 97% rename from tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py rename to src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py index 285367a..6da5e09 100644 --- a/tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py +++ b/src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py @@ -220,7 +220,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -243,7 +245,7 @@ def test_taxi_eth_mac_1g_fifo(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv b/src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv similarity index 100% rename from tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv rename to src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv diff --git a/tb/eth/taxi_eth_mac_1g_gmii/Makefile b/src/eth/tb/taxi_eth_mac_1g_gmii/Makefile similarity index 94% rename from tb/eth/taxi_eth_mac_1g_gmii/Makefile rename to src/eth/tb/taxi_eth_mac_1g_gmii/Makefile index 81124be..ba96ac9 100644 --- a/tb/eth/taxi_eth_mac_1g_gmii/Makefile +++ b/src/eth/tb/taxi_eth_mac_1g_gmii/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_1g_gmii COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py b/src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py similarity index 98% rename from tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py rename to src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py index 74992ed..9aee26c 100644 --- a/tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py +++ b/src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py @@ -649,7 +649,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -673,7 +675,7 @@ def test_taxi_eth_mac_1g_gmii(request, pfc_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv b/src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv similarity index 100% rename from tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv rename to src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv diff --git a/tb/eth/taxi_eth_mac_1g_gmii_fifo/Makefile b/src/eth/tb/taxi_eth_mac_1g_gmii_fifo/Makefile similarity index 95% rename from tb/eth/taxi_eth_mac_1g_gmii_fifo/Makefile rename to src/eth/tb/taxi_eth_mac_1g_gmii_fifo/Makefile index 5360c81..ea9f45d 100644 --- a/tb/eth/taxi_eth_mac_1g_gmii_fifo/Makefile +++ b/src/eth/tb/taxi_eth_mac_1g_gmii_fifo/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_1g_gmii_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py b/src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py similarity index 96% rename from tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py rename to src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py index e1b54ab..6e7349d 100644 --- a/tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py +++ b/src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py @@ -173,7 +173,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -196,7 +198,7 @@ def test_taxi_eth_mac_1g_gmii_fifo(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv b/src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv similarity index 100% rename from tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv rename to src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv diff --git a/tb/eth/taxi_eth_mac_1g_rgmii/Makefile b/src/eth/tb/taxi_eth_mac_1g_rgmii/Makefile similarity index 94% rename from tb/eth/taxi_eth_mac_1g_rgmii/Makefile rename to src/eth/tb/taxi_eth_mac_1g_rgmii/Makefile index c15904a..8e7b5cf 100644 --- a/tb/eth/taxi_eth_mac_1g_rgmii/Makefile +++ b/src/eth/tb/taxi_eth_mac_1g_rgmii/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_1g_rgmii COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py b/src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py similarity index 98% rename from tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py rename to src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py index 686df17..efeeb08 100644 --- a/tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py +++ b/src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py @@ -653,7 +653,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -677,7 +679,7 @@ def test_taxi_eth_mac_1g_rgmii(request, pfc_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv b/src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv similarity index 100% rename from tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv rename to src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv diff --git a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile b/src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/Makefile similarity index 95% rename from tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile rename to src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/Makefile index 121bb73..8d7aea7 100644 --- a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile +++ b/src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_1g_rgmii_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py b/src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py similarity index 96% rename from tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py rename to src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py index 07f5891..5312682 100644 --- a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py +++ b/src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py @@ -189,7 +189,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -212,7 +214,7 @@ def test_taxi_eth_mac_1g_rgmii_fifo(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv b/src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv similarity index 100% rename from tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv rename to src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv diff --git a/tb/eth/taxi_eth_mac_mii/Makefile b/src/eth/tb/taxi_eth_mac_mii/Makefile similarity index 94% rename from tb/eth/taxi_eth_mac_mii/Makefile rename to src/eth/tb/taxi_eth_mac_mii/Makefile index 7b11ffd..740fa0b 100644 --- a/tb/eth/taxi_eth_mac_mii/Makefile +++ b/src/eth/tb/taxi_eth_mac_mii/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_mii COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py b/src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py similarity index 98% rename from tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py rename to src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py index 89c51d8..6d437fe 100644 --- a/tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py +++ b/src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py @@ -612,7 +612,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -636,7 +638,7 @@ def test_taxi_eth_mac_mii(request, pfc_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv b/src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv similarity index 100% rename from tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv rename to src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv diff --git a/tb/eth/taxi_eth_mac_mii_fifo/Makefile b/src/eth/tb/taxi_eth_mac_mii_fifo/Makefile similarity index 95% rename from tb/eth/taxi_eth_mac_mii_fifo/Makefile rename to src/eth/tb/taxi_eth_mac_mii_fifo/Makefile index ee74587..b341b27 100644 --- a/tb/eth/taxi_eth_mac_mii_fifo/Makefile +++ b/src/eth/tb/taxi_eth_mac_mii_fifo/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_mii_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py b/src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py similarity index 96% rename from tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py rename to src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py index b94be81..800e513 100644 --- a/tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py +++ b/src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py @@ -149,7 +149,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -172,7 +174,7 @@ def test_taxi_eth_mac_mii_fifo(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv b/src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv similarity index 100% rename from tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv rename to src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv diff --git a/tb/eth/taxi_eth_mac_phy_10g/Makefile b/src/eth/tb/taxi_eth_mac_phy_10g/Makefile similarity index 94% rename from tb/eth/taxi_eth_mac_phy_10g/Makefile rename to src/eth/tb/taxi_eth_mac_phy_10g/Makefile index 55ca08a..3d72df3 100644 --- a/tb/eth/taxi_eth_mac_phy_10g/Makefile +++ b/src/eth/tb/taxi_eth_mac_phy_10g/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_phy_10g COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_phy_10g/baser.py b/src/eth/tb/taxi_eth_mac_phy_10g/baser.py similarity index 100% rename from tb/eth/taxi_eth_mac_phy_10g/baser.py rename to src/eth/tb/taxi_eth_mac_phy_10g/baser.py diff --git a/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py b/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py similarity index 99% rename from tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py rename to src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py index 0040ca5..770bf68 100644 --- a/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py +++ b/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py @@ -776,7 +776,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -801,7 +803,7 @@ def test_taxi_eth_mac_phy_10g(request, data_w, dic_en, pfc_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv b/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv similarity index 100% rename from tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv rename to src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv diff --git a/tb/eth/taxi_eth_mac_phy_10g_fifo/Makefile b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/Makefile similarity index 96% rename from tb/eth/taxi_eth_mac_phy_10g_fifo/Makefile rename to src/eth/tb/taxi_eth_mac_phy_10g_fifo/Makefile index 36c758a..9bd174e 100644 --- a/tb/eth/taxi_eth_mac_phy_10g_fifo/Makefile +++ b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_eth_mac_phy_10g_fifo COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_mac_phy_10g_fifo/baser.py b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/baser.py similarity index 100% rename from tb/eth/taxi_eth_mac_phy_10g_fifo/baser.py rename to src/eth/tb/taxi_eth_mac_phy_10g_fifo/baser.py diff --git a/tb/eth/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py similarity index 98% rename from tb/eth/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py rename to src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py index 5913355..52e133f 100644 --- a/tb/eth/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py +++ b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py @@ -372,7 +372,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -397,7 +399,7 @@ def test_taxi_eth_mac_phy_10g_fifo(request, data_w, dic_en): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv similarity index 100% rename from tb/eth/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv rename to src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv diff --git a/tb/eth/taxi_eth_phy_10g/Makefile b/src/eth/tb/taxi_eth_phy_10g/Makefile similarity index 93% rename from tb/eth/taxi_eth_phy_10g/Makefile rename to src/eth/tb/taxi_eth_phy_10g/Makefile index 8cd225c..7e9ecee 100644 --- a/tb/eth/taxi_eth_phy_10g/Makefile +++ b/src/eth/tb/taxi_eth_phy_10g/Makefile @@ -12,14 +12,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps -export COCOTB_RESOLVE_X ?= RANDOM + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src DUT = taxi_eth_phy_10g COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_eth_phy_10g/baser.py b/src/eth/tb/taxi_eth_phy_10g/baser.py similarity index 100% rename from tb/eth/taxi_eth_phy_10g/baser.py rename to src/eth/tb/taxi_eth_phy_10g/baser.py diff --git a/tb/eth/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py b/src/eth/tb/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py similarity index 96% rename from tb/eth/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py rename to src/eth/tb/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py index 83875f9..8dfdcaf 100644 --- a/tb/eth/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py +++ b/src/eth/tb/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py @@ -196,7 +196,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -219,7 +221,7 @@ def test_taxi_eth_phy_10g(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_mac_ctrl_rx/Makefile b/src/eth/tb/taxi_mac_ctrl_rx/Makefile similarity index 89% rename from tb/eth/taxi_mac_ctrl_rx/Makefile rename to src/eth/tb/taxi_mac_ctrl_rx/Makefile index cc987ee..441251e 100644 --- a/tb/eth/taxi_mac_ctrl_rx/Makefile +++ b/src/eth/tb/taxi_mac_ctrl_rx/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_mac_ctrl_rx COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.py b/src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.py similarity index 98% rename from tb/eth/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.py rename to src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.py index 4d6e278..632a1c5 100644 --- a/tb/eth/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.py +++ b/src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.py @@ -536,7 +536,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -560,8 +562,8 @@ def test_taxi_mac_ctrl_rx(request, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.sv b/src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.sv similarity index 100% rename from tb/eth/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.sv rename to src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.sv diff --git a/tb/eth/taxi_mac_ctrl_tx/Makefile b/src/eth/tb/taxi_mac_ctrl_tx/Makefile similarity index 88% rename from tb/eth/taxi_mac_ctrl_tx/Makefile rename to src/eth/tb/taxi_mac_ctrl_tx/Makefile index 0f07ca9..686d918 100644 --- a/tb/eth/taxi_mac_ctrl_tx/Makefile +++ b/src/eth/tb/taxi_mac_ctrl_tx/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_mac_ctrl_tx COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.py b/src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.py similarity index 97% rename from tb/eth/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.py rename to src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.py index 43e9880..ea73734 100644 --- a/tb/eth/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.py +++ b/src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.py @@ -418,7 +418,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -442,8 +444,8 @@ def test_taxi_mac_ctrl_tx(request, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "eth", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.sv b/src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.sv similarity index 100% rename from tb/eth/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.sv rename to src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.sv diff --git a/tb/eth/taxi_mac_pause_ctrl_rx/Makefile b/src/eth/tb/taxi_mac_pause_ctrl_rx/Makefile similarity index 91% rename from tb/eth/taxi_mac_pause_ctrl_rx/Makefile rename to src/eth/tb/taxi_mac_pause_ctrl_rx/Makefile index 4f4aa6b..2cb3560 100644 --- a/tb/eth/taxi_mac_pause_ctrl_rx/Makefile +++ b/src/eth/tb/taxi_mac_pause_ctrl_rx/Makefile @@ -13,12 +13,16 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_mac_pause_ctrl_rx COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py b/src/eth/tb/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py similarity index 97% rename from tb/eth/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py rename to src/eth/tb/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py index c164b93..8c43584 100644 --- a/tb/eth/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py +++ b/src/eth/tb/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py @@ -375,7 +375,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -397,7 +399,7 @@ def test_taxi_mac_pause_ctrl_rx(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "eth", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_mac_pause_ctrl_tx/Makefile b/src/eth/tb/taxi_mac_pause_ctrl_tx/Makefile similarity index 91% rename from tb/eth/taxi_mac_pause_ctrl_tx/Makefile rename to src/eth/tb/taxi_mac_pause_ctrl_tx/Makefile index 671fe9d..4645e2c 100644 --- a/tb/eth/taxi_mac_pause_ctrl_tx/Makefile +++ b/src/eth/tb/taxi_mac_pause_ctrl_tx/Makefile @@ -13,12 +13,16 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_mac_pause_ctrl_tx COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py b/src/eth/tb/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py similarity index 97% rename from tb/eth/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py rename to src/eth/tb/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py index 5349578..de944a0 100644 --- a/tb/eth/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py +++ b/src/eth/tb/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py @@ -326,7 +326,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -348,7 +350,7 @@ def test_taxi_mac_pause_ctrl_tx(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "eth", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_xgmii_baser_dec_64/Makefile b/src/eth/tb/taxi_xgmii_baser_dec_64/Makefile similarity index 92% rename from tb/eth/taxi_xgmii_baser_dec_64/Makefile rename to src/eth/tb/taxi_xgmii_baser_dec_64/Makefile index 5aba5af..5579107 100644 --- a/tb/eth/taxi_xgmii_baser_dec_64/Makefile +++ b/src/eth/tb/taxi_xgmii_baser_dec_64/Makefile @@ -12,14 +12,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps -export COCOTB_RESOLVE_X ?= RANDOM + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src DUT = taxi_xgmii_baser_dec_64 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_xgmii_baser_dec_64/baser.py b/src/eth/tb/taxi_xgmii_baser_dec_64/baser.py similarity index 100% rename from tb/eth/taxi_xgmii_baser_dec_64/baser.py rename to src/eth/tb/taxi_xgmii_baser_dec_64/baser.py diff --git a/tb/eth/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py b/src/eth/tb/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py similarity index 96% rename from tb/eth/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py rename to src/eth/tb/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py index ce2e2b9..d737e8b 100644 --- a/tb/eth/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py +++ b/src/eth/tb/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py @@ -193,7 +193,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -215,7 +217,7 @@ def test_taxi_xgmii_baser_dec_64(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "eth", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/eth/taxi_xgmii_baser_enc_64/Makefile b/src/eth/tb/taxi_xgmii_baser_enc_64/Makefile similarity index 92% rename from tb/eth/taxi_xgmii_baser_enc_64/Makefile rename to src/eth/tb/taxi_xgmii_baser_enc_64/Makefile index 26fd6e2..4673fc6 100644 --- a/tb/eth/taxi_xgmii_baser_enc_64/Makefile +++ b/src/eth/tb/taxi_xgmii_baser_enc_64/Makefile @@ -12,14 +12,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps -export COCOTB_RESOLVE_X ?= RANDOM + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src DUT = taxi_xgmii_baser_enc_64 COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/eth/taxi_xgmii_baser_enc_64/baser.py b/src/eth/tb/taxi_xgmii_baser_enc_64/baser.py similarity index 100% rename from tb/eth/taxi_xgmii_baser_enc_64/baser.py rename to src/eth/tb/taxi_xgmii_baser_enc_64/baser.py diff --git a/tb/eth/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py b/src/eth/tb/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py similarity index 96% rename from tb/eth/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py rename to src/eth/tb/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py index 4aea435..da943ce 100644 --- a/tb/eth/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py +++ b/src/eth/tb/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py @@ -193,7 +193,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -215,7 +217,7 @@ def test_taxi_xgmii_baser_enc_64(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "eth", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/rtl/hip/us/taxi_mmcm_frac.sv b/src/hip/rtl/us/taxi_mmcm_frac.sv similarity index 100% rename from rtl/hip/us/taxi_mmcm_frac.sv rename to src/hip/rtl/us/taxi_mmcm_frac.sv diff --git a/rtl/io/taxi_debounce_switch.sv b/src/io/rtl/taxi_debounce_switch.sv similarity index 100% rename from rtl/io/taxi_debounce_switch.sv rename to src/io/rtl/taxi_debounce_switch.sv diff --git a/rtl/io/taxi_iddr.sv b/src/io/rtl/taxi_iddr.sv similarity index 100% rename from rtl/io/taxi_iddr.sv rename to src/io/rtl/taxi_iddr.sv diff --git a/rtl/io/taxi_led_sreg.sv b/src/io/rtl/taxi_led_sreg.sv similarity index 100% rename from rtl/io/taxi_led_sreg.sv rename to src/io/rtl/taxi_led_sreg.sv diff --git a/rtl/io/taxi_oddr.sv b/src/io/rtl/taxi_oddr.sv similarity index 100% rename from rtl/io/taxi_oddr.sv rename to src/io/rtl/taxi_oddr.sv diff --git a/rtl/io/taxi_ssio_ddr_in.sv b/src/io/rtl/taxi_ssio_ddr_in.sv similarity index 100% rename from rtl/io/taxi_ssio_ddr_in.sv rename to src/io/rtl/taxi_ssio_ddr_in.sv diff --git a/rtl/io/taxi_ssio_ddr_in_diff.sv b/src/io/rtl/taxi_ssio_ddr_in_diff.sv similarity index 100% rename from rtl/io/taxi_ssio_ddr_in_diff.sv rename to src/io/rtl/taxi_ssio_ddr_in_diff.sv diff --git a/rtl/io/taxi_ssio_ddr_out.sv b/src/io/rtl/taxi_ssio_ddr_out.sv similarity index 100% rename from rtl/io/taxi_ssio_ddr_out.sv rename to src/io/rtl/taxi_ssio_ddr_out.sv diff --git a/rtl/io/taxi_ssio_ddr_out_diff.sv b/src/io/rtl/taxi_ssio_ddr_out_diff.sv similarity index 100% rename from rtl/io/taxi_ssio_ddr_out_diff.sv rename to src/io/rtl/taxi_ssio_ddr_out_diff.sv diff --git a/rtl/io/taxi_ssio_sdr_in.sv b/src/io/rtl/taxi_ssio_sdr_in.sv similarity index 100% rename from rtl/io/taxi_ssio_sdr_in.sv rename to src/io/rtl/taxi_ssio_sdr_in.sv diff --git a/rtl/io/taxi_ssio_sdr_in_diff.sv b/src/io/rtl/taxi_ssio_sdr_in_diff.sv similarity index 100% rename from rtl/io/taxi_ssio_sdr_in_diff.sv rename to src/io/rtl/taxi_ssio_sdr_in_diff.sv diff --git a/rtl/io/taxi_ssio_sdr_out.sv b/src/io/rtl/taxi_ssio_sdr_out.sv similarity index 100% rename from rtl/io/taxi_ssio_sdr_out.sv rename to src/io/rtl/taxi_ssio_sdr_out.sv diff --git a/rtl/io/taxi_ssio_sdr_out_diff.sv b/src/io/rtl/taxi_ssio_sdr_out_diff.sv similarity index 100% rename from rtl/io/taxi_ssio_sdr_out_diff.sv rename to src/io/rtl/taxi_ssio_sdr_out_diff.sv diff --git a/rtl/lfsr/taxi_lfsr.sv b/src/lfsr/rtl/taxi_lfsr.sv similarity index 100% rename from rtl/lfsr/taxi_lfsr.sv rename to src/lfsr/rtl/taxi_lfsr.sv diff --git a/rtl/lfsr/taxi_lfsr_crc.sv b/src/lfsr/rtl/taxi_lfsr_crc.sv similarity index 100% rename from rtl/lfsr/taxi_lfsr_crc.sv rename to src/lfsr/rtl/taxi_lfsr_crc.sv diff --git a/rtl/lfsr/taxi_lfsr_descramble.sv b/src/lfsr/rtl/taxi_lfsr_descramble.sv similarity index 100% rename from rtl/lfsr/taxi_lfsr_descramble.sv rename to src/lfsr/rtl/taxi_lfsr_descramble.sv diff --git a/rtl/lfsr/taxi_lfsr_prbs_check.sv b/src/lfsr/rtl/taxi_lfsr_prbs_check.sv similarity index 100% rename from rtl/lfsr/taxi_lfsr_prbs_check.sv rename to src/lfsr/rtl/taxi_lfsr_prbs_check.sv diff --git a/rtl/lfsr/taxi_lfsr_prbs_gen.sv b/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv similarity index 100% rename from rtl/lfsr/taxi_lfsr_prbs_gen.sv rename to src/lfsr/rtl/taxi_lfsr_prbs_gen.sv diff --git a/rtl/lfsr/taxi_lfsr_scramble.sv b/src/lfsr/rtl/taxi_lfsr_scramble.sv similarity index 100% rename from rtl/lfsr/taxi_lfsr_scramble.sv rename to src/lfsr/rtl/taxi_lfsr_scramble.sv diff --git a/tb/lfsr/taxi_lfsr/Makefile b/src/lfsr/tb/taxi_lfsr/Makefile similarity index 95% rename from tb/lfsr/taxi_lfsr/Makefile rename to src/lfsr/tb/taxi_lfsr/Makefile index e621060..436453e 100644 --- a/tb/lfsr/taxi_lfsr/Makefile +++ b/src/lfsr/tb/taxi_lfsr/Makefile @@ -13,12 +13,14 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_lfsr COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lfsr/taxi_lfsr/test_taxi_lfsr.py b/src/lfsr/tb/taxi_lfsr/test_taxi_lfsr.py similarity index 97% rename from tb/lfsr/taxi_lfsr/test_taxi_lfsr.py rename to src/lfsr/tb/taxi_lfsr/test_taxi_lfsr.py index d8052ce..34a39df 100644 --- a/tb/lfsr/taxi_lfsr/test_taxi_lfsr.py +++ b/src/lfsr/tb/taxi_lfsr/test_taxi_lfsr.py @@ -175,7 +175,7 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) def process_f_files(files): @@ -207,7 +207,7 @@ def test_taxi_lfsr(request, lfsr_w, lfsr_poly, lfsr_galois, reverse, data_w): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "lfsr", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/lfsr/taxi_lfsr_crc/Makefile b/src/lfsr/tb/taxi_lfsr_crc/Makefile similarity index 93% rename from tb/lfsr/taxi_lfsr_crc/Makefile rename to src/lfsr/tb/taxi_lfsr_crc/Makefile index d63013e..5076410 100644 --- a/tb/lfsr/taxi_lfsr_crc/Makefile +++ b/src/lfsr/tb/taxi_lfsr_crc/Makefile @@ -13,13 +13,15 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_lfsr_crc COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lfsr/taxi_lfsr_crc/test_taxi_lfsr_crc.py b/src/lfsr/tb/taxi_lfsr_crc/test_taxi_lfsr_crc.py similarity index 96% rename from tb/lfsr/taxi_lfsr_crc/test_taxi_lfsr_crc.py rename to src/lfsr/tb/taxi_lfsr_crc/test_taxi_lfsr_crc.py index bfc5141..6fb82d1 100644 --- a/tb/lfsr/taxi_lfsr_crc/test_taxi_lfsr_crc.py +++ b/src/lfsr/tb/taxi_lfsr_crc/test_taxi_lfsr_crc.py @@ -128,7 +128,7 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) def process_f_files(files): @@ -156,8 +156,8 @@ def test_taxi_lfsr_crc(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, rever toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "lfsr", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_lfsr.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/lfsr/taxi_lfsr_descramble/Makefile b/src/lfsr/tb/taxi_lfsr_descramble/Makefile similarity index 93% rename from tb/lfsr/taxi_lfsr_descramble/Makefile rename to src/lfsr/tb/taxi_lfsr_descramble/Makefile index 9eb95a7..8cdcebd 100644 --- a/tb/lfsr/taxi_lfsr_descramble/Makefile +++ b/src/lfsr/tb/taxi_lfsr_descramble/Makefile @@ -13,13 +13,15 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_lfsr_descramble COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lfsr/taxi_lfsr_descramble/test_taxi_lfsr_descramble.py b/src/lfsr/tb/taxi_lfsr_descramble/test_taxi_lfsr_descramble.py similarity index 96% rename from tb/lfsr/taxi_lfsr_descramble/test_taxi_lfsr_descramble.py rename to src/lfsr/tb/taxi_lfsr_descramble/test_taxi_lfsr_descramble.py index fc0b434..434a7c7 100644 --- a/tb/lfsr/taxi_lfsr_descramble/test_taxi_lfsr_descramble.py +++ b/src/lfsr/tb/taxi_lfsr_descramble/test_taxi_lfsr_descramble.py @@ -129,7 +129,7 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) def process_f_files(files): @@ -155,8 +155,8 @@ def test_taxi_lfsr_descramble(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "lfsr", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_lfsr.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/lfsr/taxi_lfsr_prbs_check/Makefile b/src/lfsr/tb/taxi_lfsr_prbs_check/Makefile similarity index 93% rename from tb/lfsr/taxi_lfsr_prbs_check/Makefile rename to src/lfsr/tb/taxi_lfsr_prbs_check/Makefile index b63d855..a52af9f 100644 --- a/tb/lfsr/taxi_lfsr_prbs_check/Makefile +++ b/src/lfsr/tb/taxi_lfsr_prbs_check/Makefile @@ -13,13 +13,15 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_lfsr_prbs_check COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lfsr/taxi_lfsr_prbs_check/test_taxi_lfsr_prbs_check.py b/src/lfsr/tb/taxi_lfsr_prbs_check/test_taxi_lfsr_prbs_check.py similarity index 96% rename from tb/lfsr/taxi_lfsr_prbs_check/test_taxi_lfsr_prbs_check.py rename to src/lfsr/tb/taxi_lfsr_prbs_check/test_taxi_lfsr_prbs_check.py index 2b7b8c6..77eb0d4 100644 --- a/tb/lfsr/taxi_lfsr_prbs_check/test_taxi_lfsr_prbs_check.py +++ b/src/lfsr/tb/taxi_lfsr_prbs_check/test_taxi_lfsr_prbs_check.py @@ -162,7 +162,7 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) def process_f_files(files): @@ -190,8 +190,8 @@ def test_taxi_lfsr_prbs_check(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "lfsr", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_lfsr.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/lfsr/taxi_lfsr_prbs_gen/Makefile b/src/lfsr/tb/taxi_lfsr_prbs_gen/Makefile similarity index 93% rename from tb/lfsr/taxi_lfsr_prbs_gen/Makefile rename to src/lfsr/tb/taxi_lfsr_prbs_gen/Makefile index 9ea951f..aa935c3 100644 --- a/tb/lfsr/taxi_lfsr_prbs_gen/Makefile +++ b/src/lfsr/tb/taxi_lfsr_prbs_gen/Makefile @@ -13,13 +13,15 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_lfsr_prbs_gen COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lfsr/taxi_lfsr_prbs_gen/test_taxi_lfsr_prbs_gen.py b/src/lfsr/tb/taxi_lfsr_prbs_gen/test_taxi_lfsr_prbs_gen.py similarity index 95% rename from tb/lfsr/taxi_lfsr_prbs_gen/test_taxi_lfsr_prbs_gen.py rename to src/lfsr/tb/taxi_lfsr_prbs_gen/test_taxi_lfsr_prbs_gen.py index 8a51938..73dc8e7 100644 --- a/tb/lfsr/taxi_lfsr_prbs_gen/test_taxi_lfsr_prbs_gen.py +++ b/src/lfsr/tb/taxi_lfsr_prbs_gen/test_taxi_lfsr_prbs_gen.py @@ -110,7 +110,7 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) def process_f_files(files): @@ -138,8 +138,8 @@ def test_taxi_lfsr_prbs_gen(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "lfsr", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_lfsr.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/lfsr/taxi_lfsr_scramble/Makefile b/src/lfsr/tb/taxi_lfsr_scramble/Makefile similarity index 93% rename from tb/lfsr/taxi_lfsr_scramble/Makefile rename to src/lfsr/tb/taxi_lfsr_scramble/Makefile index cd01dfe..9e645f1 100644 --- a/tb/lfsr/taxi_lfsr_scramble/Makefile +++ b/src/lfsr/tb/taxi_lfsr_scramble/Makefile @@ -13,13 +13,15 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_lfsr_scramble COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lfsr/taxi_lfsr_scramble/test_taxi_lfsr_scramble.py b/src/lfsr/tb/taxi_lfsr_scramble/test_taxi_lfsr_scramble.py similarity index 95% rename from tb/lfsr/taxi_lfsr_scramble/test_taxi_lfsr_scramble.py rename to src/lfsr/tb/taxi_lfsr_scramble/test_taxi_lfsr_scramble.py index e72652b..0f3363e 100644 --- a/tb/lfsr/taxi_lfsr_scramble/test_taxi_lfsr_scramble.py +++ b/src/lfsr/tb/taxi_lfsr_scramble/test_taxi_lfsr_scramble.py @@ -112,7 +112,7 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) def process_f_files(files): @@ -138,8 +138,8 @@ def test_taxi_lfsr_scramble(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "lfsr", f"{dut}.sv"), - os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_lfsr.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/src/lss/lib/taxi b/src/lss/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/lss/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/rtl/lss/taxi_i2c_master.sv b/src/lss/rtl/taxi_i2c_master.sv similarity index 100% rename from rtl/lss/taxi_i2c_master.sv rename to src/lss/rtl/taxi_i2c_master.sv diff --git a/rtl/lss/taxi_i2c_single_reg.sv b/src/lss/rtl/taxi_i2c_single_reg.sv similarity index 100% rename from rtl/lss/taxi_i2c_single_reg.sv rename to src/lss/rtl/taxi_i2c_single_reg.sv diff --git a/rtl/lss/taxi_mdio_master.sv b/src/lss/rtl/taxi_mdio_master.sv similarity index 100% rename from rtl/lss/taxi_mdio_master.sv rename to src/lss/rtl/taxi_mdio_master.sv diff --git a/rtl/lss/taxi_uart.f b/src/lss/rtl/taxi_uart.f similarity index 60% rename from rtl/lss/taxi_uart.f rename to src/lss/rtl/taxi_uart.f index 012469e..9a37d39 100644 --- a/rtl/lss/taxi_uart.f +++ b/src/lss/rtl/taxi_uart.f @@ -2,4 +2,4 @@ taxi_uart.sv taxi_uart_rx.sv taxi_uart_tx.sv taxi_uart_brg.sv -../axis/taxi_axis_if.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/lss/taxi_uart.sv b/src/lss/rtl/taxi_uart.sv similarity index 100% rename from rtl/lss/taxi_uart.sv rename to src/lss/rtl/taxi_uart.sv diff --git a/rtl/lss/taxi_uart_brg.sv b/src/lss/rtl/taxi_uart_brg.sv similarity index 100% rename from rtl/lss/taxi_uart_brg.sv rename to src/lss/rtl/taxi_uart_brg.sv diff --git a/rtl/lss/taxi_uart_rx.sv b/src/lss/rtl/taxi_uart_rx.sv similarity index 100% rename from rtl/lss/taxi_uart_rx.sv rename to src/lss/rtl/taxi_uart_rx.sv diff --git a/rtl/lss/taxi_uart_tx.sv b/src/lss/rtl/taxi_uart_tx.sv similarity index 100% rename from rtl/lss/taxi_uart_tx.sv rename to src/lss/rtl/taxi_uart_tx.sv diff --git a/tb/lss/taxi_i2c_master/Makefile b/src/lss/tb/taxi_i2c_master/Makefile similarity index 88% rename from tb/lss/taxi_i2c_master/Makefile rename to src/lss/tb/taxi_i2c_master/Makefile index 22f9985..463ccaa 100644 --- a/tb/lss/taxi_i2c_master/Makefile +++ b/src/lss/tb/taxi_i2c_master/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_i2c_master COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/lss/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lss/taxi_i2c_master/test_taxi_i2c_master.py b/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py similarity index 94% rename from tb/lss/taxi_i2c_master/test_taxi_i2c_master.py rename to src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py index b190dcf..a750bed 100644 --- a/tb/lss/taxi_i2c_master/test_taxi_i2c_master.py +++ b/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py @@ -175,7 +175,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -198,8 +200,8 @@ def test_taxi_i2c_master(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "lss", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] parameters = {} diff --git a/tb/lss/taxi_i2c_master/test_taxi_i2c_master.sv b/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.sv similarity index 100% rename from tb/lss/taxi_i2c_master/test_taxi_i2c_master.sv rename to src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.sv diff --git a/tb/lss/taxi_i2c_single_reg/Makefile b/src/lss/tb/taxi_i2c_single_reg/Makefile similarity index 92% rename from tb/lss/taxi_i2c_single_reg/Makefile rename to src/lss/tb/taxi_i2c_single_reg/Makefile index f3cf824..8a60443 100644 --- a/tb/lss/taxi_i2c_single_reg/Makefile +++ b/src/lss/tb/taxi_i2c_single_reg/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_i2c_single_reg COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/lss/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py b/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py similarity index 94% rename from tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py rename to src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py index 571aa10..e46b35b 100644 --- a/tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py +++ b/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py @@ -147,7 +147,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -170,7 +172,7 @@ def test_taxi_i2c_single_reg(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "lss", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] parameters = {} diff --git a/tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv b/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv similarity index 100% rename from tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv rename to src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv diff --git a/tb/lss/taxi_uart/Makefile b/src/lss/tb/taxi_uart/Makefile similarity index 92% rename from tb/lss/taxi_uart/Makefile rename to src/lss/tb/taxi_uart/Makefile index a3cb966..d67f795 100644 --- a/tb/lss/taxi_uart/Makefile +++ b/src/lss/tb/taxi_uart/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ns +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_uart COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/lss/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/lss/taxi_uart/test_taxi_uart.py b/src/lss/tb/taxi_uart/test_taxi_uart.py similarity index 94% rename from tb/lss/taxi_uart/test_taxi_uart.py rename to src/lss/tb/taxi_uart/test_taxi_uart.py index b255e46..195ddde 100644 --- a/tb/lss/taxi_uart/test_taxi_uart.py +++ b/src/lss/tb/taxi_uart/test_taxi_uart.py @@ -138,7 +138,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -161,7 +163,7 @@ def test_taxi_uart(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "lss", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/lss/taxi_uart/test_taxi_uart.sv b/src/lss/tb/taxi_uart/test_taxi_uart.sv similarity index 100% rename from tb/lss/taxi_uart/test_taxi_uart.sv rename to src/lss/tb/taxi_uart/test_taxi_uart.sv diff --git a/src/pcie/lib/taxi b/src/pcie/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/pcie/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/rtl/pcie/taxi_pcie_axil_master.sv b/src/pcie/rtl/taxi_pcie_axil_master.sv similarity index 100% rename from rtl/pcie/taxi_pcie_axil_master.sv rename to src/pcie/rtl/taxi_pcie_axil_master.sv diff --git a/rtl/pcie/taxi_pcie_axil_master_minimal.sv b/src/pcie/rtl/taxi_pcie_axil_master_minimal.sv similarity index 100% rename from rtl/pcie/taxi_pcie_axil_master_minimal.sv rename to src/pcie/rtl/taxi_pcie_axil_master_minimal.sv diff --git a/rtl/pcie/taxi_pcie_tlp_if.sv b/src/pcie/rtl/taxi_pcie_tlp_if.sv similarity index 100% rename from rtl/pcie/taxi_pcie_tlp_if.sv rename to src/pcie/rtl/taxi_pcie_tlp_if.sv diff --git a/tb/pcie/pcie_if.py b/src/pcie/tb/pcie_if.py similarity index 100% rename from tb/pcie/pcie_if.py rename to src/pcie/tb/pcie_if.py diff --git a/tb/pcie/taxi_pcie_axil_master/Makefile b/src/pcie/tb/taxi_pcie_axil_master/Makefile similarity index 86% rename from tb/pcie/taxi_pcie_axil_master/Makefile rename to src/pcie/tb/taxi_pcie_axil_master/Makefile index a07e56e..960df73 100644 --- a/tb/pcie/taxi_pcie_axil_master/Makefile +++ b/src/pcie/tb/taxi_pcie_axil_master/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_pcie_axil_master COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/pcie/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/pcie/taxi_pcie_tlp_if.sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_pcie_tlp_if.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/pcie/taxi_pcie_axil_master/pcie_if.py b/src/pcie/tb/taxi_pcie_axil_master/pcie_if.py similarity index 100% rename from tb/pcie/taxi_pcie_axil_master/pcie_if.py rename to src/pcie/tb/taxi_pcie_axil_master/pcie_if.py diff --git a/tb/pcie/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py b/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py similarity index 96% rename from tb/pcie/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py rename to src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py index 9aad5e6..c0012da 100644 --- a/tb/pcie/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py +++ b/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py @@ -302,7 +302,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -327,9 +329,9 @@ def test_taxi_pcie_axil_master(request, pcie_data_w, axil_data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "pcie", f"{dut}.sv"), - os.path.join(rtl_dir, "pcie", "taxi_pcie_tlp_if.sv"), - os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_pcie_tlp_if.sv"), + os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/pcie/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv b/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv similarity index 100% rename from tb/pcie/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv rename to src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv diff --git a/tb/pcie/taxi_pcie_axil_master_minimal/Makefile b/src/pcie/tb/taxi_pcie_axil_master_minimal/Makefile similarity index 86% rename from tb/pcie/taxi_pcie_axil_master_minimal/Makefile rename to src/pcie/tb/taxi_pcie_axil_master_minimal/Makefile index aec1ceb..32dc4e6 100644 --- a/tb/pcie/taxi_pcie_axil_master_minimal/Makefile +++ b/src/pcie/tb/taxi_pcie_axil_master_minimal/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_pcie_axil_master_minimal COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/pcie/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/pcie/taxi_pcie_tlp_if.sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_pcie_tlp_if.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/pcie/taxi_pcie_axil_master_minimal/pcie_if.py b/src/pcie/tb/taxi_pcie_axil_master_minimal/pcie_if.py similarity index 100% rename from tb/pcie/taxi_pcie_axil_master_minimal/pcie_if.py rename to src/pcie/tb/taxi_pcie_axil_master_minimal/pcie_if.py diff --git a/tb/pcie/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py b/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py similarity index 96% rename from tb/pcie/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py rename to src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py index cd018ad..9dbad0d 100644 --- a/tb/pcie/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py +++ b/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py @@ -337,7 +337,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -362,9 +364,9 @@ def test_taxi_pcie_axil_master_minimal(request, pcie_data_w, axil_data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "pcie", f"{dut}.sv"), - os.path.join(rtl_dir, "pcie", "taxi_pcie_tlp_if.sv"), - os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_pcie_tlp_if.sv"), + os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/pcie/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv b/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv similarity index 100% rename from tb/pcie/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv rename to src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv diff --git a/rtl/prim/taxi_arbiter.sv b/src/prim/rtl/taxi_arbiter.sv similarity index 100% rename from rtl/prim/taxi_arbiter.sv rename to src/prim/rtl/taxi_arbiter.sv diff --git a/rtl/prim/taxi_penc.sv b/src/prim/rtl/taxi_penc.sv similarity index 100% rename from rtl/prim/taxi_penc.sv rename to src/prim/rtl/taxi_penc.sv diff --git a/tb/prim/taxi_arbiter/Makefile b/src/prim/tb/taxi_arbiter/Makefile similarity index 93% rename from tb/prim/taxi_arbiter/Makefile rename to src/prim/tb/taxi_arbiter/Makefile index 3d5b670..b613738 100644 --- a/tb/prim/taxi_arbiter/Makefile +++ b/src/prim/tb/taxi_arbiter/Makefile @@ -13,13 +13,15 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_arbiter COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/prim/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/prim/taxi_penc.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_penc.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/prim/taxi_arbiter/test_taxi_arbiter.py b/src/prim/tb/taxi_arbiter/test_taxi_arbiter.py similarity index 97% rename from tb/prim/taxi_arbiter/test_taxi_arbiter.py rename to src/prim/tb/taxi_arbiter/test_taxi_arbiter.py index bafe4fb..e0d38cb 100644 --- a/tb/prim/taxi_arbiter/test_taxi_arbiter.py +++ b/src/prim/tb/taxi_arbiter/test_taxi_arbiter.py @@ -280,7 +280,8 @@ async def run_five_bits(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +src_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..')) def process_f_files(files): @@ -304,8 +305,8 @@ def test_taxi_arbiter(request, round_robin, lsb_high_prio): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "prim", f"{dut}.sv"), - os.path.join(rtl_dir, "prim", "taxi_penc.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_penc.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/prim/taxi_penc/Makefile b/src/prim/tb/taxi_penc/Makefile similarity index 95% rename from tb/prim/taxi_penc/Makefile rename to src/prim/tb/taxi_penc/Makefile index a5235f9..52bd8a3 100644 --- a/tb/prim/taxi_penc/Makefile +++ b/src/prim/tb/taxi_penc/Makefile @@ -13,12 +13,14 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl + DUT = taxi_penc COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/prim/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/prim/taxi_penc/test_taxi_penc.py b/src/prim/tb/taxi_penc/test_taxi_penc.py similarity index 94% rename from tb/prim/taxi_penc/test_taxi_penc.py rename to src/prim/tb/taxi_penc/test_taxi_penc.py index babec7b..b9b0e66 100644 --- a/tb/prim/taxi_penc/test_taxi_penc.py +++ b/src/prim/tb/taxi_penc/test_taxi_penc.py @@ -73,7 +73,8 @@ async def run_two_bits(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +src_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..')) def process_f_files(files): @@ -96,7 +97,7 @@ def test_taxi_penc(request, lsb_high_prio): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "prim", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/src/ptp/lib/taxi b/src/ptp/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/ptp/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/rtl/ptp/taxi_ptp_clock.sv b/src/ptp/rtl/taxi_ptp_clock.sv similarity index 100% rename from rtl/ptp/taxi_ptp_clock.sv rename to src/ptp/rtl/taxi_ptp_clock.sv diff --git a/rtl/ptp/taxi_ptp_clock_cdc.sv b/src/ptp/rtl/taxi_ptp_clock_cdc.sv similarity index 100% rename from rtl/ptp/taxi_ptp_clock_cdc.sv rename to src/ptp/rtl/taxi_ptp_clock_cdc.sv diff --git a/rtl/ptp/taxi_ptp_perout.sv b/src/ptp/rtl/taxi_ptp_perout.sv similarity index 100% rename from rtl/ptp/taxi_ptp_perout.sv rename to src/ptp/rtl/taxi_ptp_perout.sv diff --git a/rtl/ptp/taxi_ptp_td_leaf.sv b/src/ptp/rtl/taxi_ptp_td_leaf.sv similarity index 100% rename from rtl/ptp/taxi_ptp_td_leaf.sv rename to src/ptp/rtl/taxi_ptp_td_leaf.sv diff --git a/rtl/ptp/taxi_ptp_td_phc.sv b/src/ptp/rtl/taxi_ptp_td_phc.sv similarity index 100% rename from rtl/ptp/taxi_ptp_td_phc.sv rename to src/ptp/rtl/taxi_ptp_td_phc.sv diff --git a/rtl/ptp/taxi_ptp_td_rel2tod.sv b/src/ptp/rtl/taxi_ptp_td_rel2tod.sv similarity index 100% rename from rtl/ptp/taxi_ptp_td_rel2tod.sv rename to src/ptp/rtl/taxi_ptp_td_rel2tod.sv diff --git a/syn/vivado/taxi_ptp_clock_cdc.tcl b/src/ptp/syn/vivado/taxi_ptp_clock_cdc.tcl similarity index 100% rename from syn/vivado/taxi_ptp_clock_cdc.tcl rename to src/ptp/syn/vivado/taxi_ptp_clock_cdc.tcl diff --git a/syn/vivado/taxi_ptp_td_leaf.tcl b/src/ptp/syn/vivado/taxi_ptp_td_leaf.tcl similarity index 100% rename from syn/vivado/taxi_ptp_td_leaf.tcl rename to src/ptp/syn/vivado/taxi_ptp_td_leaf.tcl diff --git a/syn/vivado/taxi_ptp_td_rel2tod.tcl b/src/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl similarity index 100% rename from syn/vivado/taxi_ptp_td_rel2tod.tcl rename to src/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl diff --git a/tb/ptp/ptp_td.py b/src/ptp/tb/ptp_td.py similarity index 100% rename from tb/ptp/ptp_td.py rename to src/ptp/tb/ptp_td.py diff --git a/tb/ptp/taxi_ptp_clock/Makefile b/src/ptp/tb/taxi_ptp_clock/Makefile similarity index 92% rename from tb/ptp/taxi_ptp_clock/Makefile rename to src/ptp/tb/taxi_ptp_clock/Makefile index 2fdc8a9..285033d 100644 --- a/tb/ptp/taxi_ptp_clock/Makefile +++ b/src/ptp/tb/taxi_ptp_clock/Makefile @@ -13,12 +13,16 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_ptp_clock COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py b/src/ptp/tb/taxi_ptp_clock/test_taxi_ptp_clock.py similarity index 97% rename from tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py rename to src/ptp/tb/taxi_ptp_clock/test_taxi_ptp_clock.py index 3fface0..9f0dbef 100644 --- a/tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py +++ b/src/ptp/tb/taxi_ptp_clock/test_taxi_ptp_clock.py @@ -348,7 +348,9 @@ async def run_drift_adjustment(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -370,7 +372,7 @@ def test_taxi_ptp_clock(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "ptp", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/ptp/taxi_ptp_clock_cdc/Makefile b/src/ptp/tb/taxi_ptp_clock_cdc/Makefile similarity index 92% rename from tb/ptp/taxi_ptp_clock_cdc/Makefile rename to src/ptp/tb/taxi_ptp_clock_cdc/Makefile index 3c48adf..1a39a58 100644 --- a/tb/ptp/taxi_ptp_clock_cdc/Makefile +++ b/src/ptp/tb/taxi_ptp_clock_cdc/Makefile @@ -13,12 +13,16 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_ptp_clock_cdc COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/ptp/taxi_ptp_clock_cdc/test_taxi_ptp_clock_cdc.py b/src/ptp/tb/taxi_ptp_clock_cdc/test_taxi_ptp_clock_cdc.py similarity index 98% rename from tb/ptp/taxi_ptp_clock_cdc/test_taxi_ptp_clock_cdc.py rename to src/ptp/tb/taxi_ptp_clock_cdc/test_taxi_ptp_clock_cdc.py index d4c458b..69df823 100644 --- a/tb/ptp/taxi_ptp_clock_cdc/test_taxi_ptp_clock_cdc.py +++ b/src/ptp/tb/taxi_ptp_clock_cdc/test_taxi_ptp_clock_cdc.py @@ -439,7 +439,9 @@ async def run_test(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -462,7 +464,7 @@ def test_taxi_ptp_clock_cdc(request, ts_w): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "ptp", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/ptp/taxi_ptp_perout/Makefile b/src/ptp/tb/taxi_ptp_perout/Makefile similarity index 93% rename from tb/ptp/taxi_ptp_perout/Makefile rename to src/ptp/tb/taxi_ptp_perout/Makefile index 62f8ca1..f72111c 100644 --- a/tb/ptp/taxi_ptp_perout/Makefile +++ b/src/ptp/tb/taxi_ptp_perout/Makefile @@ -13,12 +13,16 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_ptp_perout COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/ptp/taxi_ptp_perout/test_taxi_ptp_perout.py b/src/ptp/tb/taxi_ptp_perout/test_taxi_ptp_perout.py similarity index 94% rename from tb/ptp/taxi_ptp_perout/test_taxi_ptp_perout.py rename to src/ptp/tb/taxi_ptp_perout/test_taxi_ptp_perout.py index ca878c3..e397c6e 100644 --- a/tb/ptp/taxi_ptp_perout/test_taxi_ptp_perout.py +++ b/src/ptp/tb/taxi_ptp_perout/test_taxi_ptp_perout.py @@ -108,7 +108,9 @@ async def run_test(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -130,7 +132,7 @@ def test_taxi_ptp_perout(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "ptp", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/ptp/taxi_ptp_td_leaf/Makefile b/src/ptp/tb/taxi_ptp_td_leaf/Makefile similarity index 93% rename from tb/ptp/taxi_ptp_td_leaf/Makefile rename to src/ptp/tb/taxi_ptp_td_leaf/Makefile index 82e32b8..f6cf580 100644 --- a/tb/ptp/taxi_ptp_td_leaf/Makefile +++ b/src/ptp/tb/taxi_ptp_td_leaf/Makefile @@ -13,12 +13,16 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_ptp_td_leaf COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/ptp/taxi_ptp_td_leaf/ptp_td.py b/src/ptp/tb/taxi_ptp_td_leaf/ptp_td.py similarity index 100% rename from tb/ptp/taxi_ptp_td_leaf/ptp_td.py rename to src/ptp/tb/taxi_ptp_td_leaf/ptp_td.py diff --git a/tb/ptp/taxi_ptp_td_leaf/test_taxi_ptp_td_leaf.py b/src/ptp/tb/taxi_ptp_td_leaf/test_taxi_ptp_td_leaf.py similarity index 98% rename from tb/ptp/taxi_ptp_td_leaf/test_taxi_ptp_td_leaf.py rename to src/ptp/tb/taxi_ptp_td_leaf/test_taxi_ptp_td_leaf.py index 472a991..e253cd6 100644 --- a/tb/ptp/taxi_ptp_td_leaf/test_taxi_ptp_td_leaf.py +++ b/src/ptp/tb/taxi_ptp_td_leaf/test_taxi_ptp_td_leaf.py @@ -486,7 +486,9 @@ async def run_test(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -508,7 +510,7 @@ def test_taxi_ptp_td_leaf(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "ptp", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/ptp/taxi_ptp_td_phc/Makefile b/src/ptp/tb/taxi_ptp_td_phc/Makefile similarity index 91% rename from tb/ptp/taxi_ptp_td_phc/Makefile rename to src/ptp/tb/taxi_ptp_td_phc/Makefile index bcdbcaa..ea63453 100644 --- a/tb/ptp/taxi_ptp_td_phc/Makefile +++ b/src/ptp/tb/taxi_ptp_td_phc/Makefile @@ -13,12 +13,16 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_ptp_td_phc COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) -VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/ptp/taxi_ptp_td_phc/ptp_td.py b/src/ptp/tb/taxi_ptp_td_phc/ptp_td.py similarity index 100% rename from tb/ptp/taxi_ptp_td_phc/ptp_td.py rename to src/ptp/tb/taxi_ptp_td_phc/ptp_td.py diff --git a/tb/ptp/taxi_ptp_td_phc/test_taxi_ptp_td_phc.py b/src/ptp/tb/taxi_ptp_td_phc/test_taxi_ptp_td_phc.py similarity index 98% rename from tb/ptp/taxi_ptp_td_phc/test_taxi_ptp_td_phc.py rename to src/ptp/tb/taxi_ptp_td_phc/test_taxi_ptp_td_phc.py index aa2de40..656fe97 100644 --- a/tb/ptp/taxi_ptp_td_phc/test_taxi_ptp_td_phc.py +++ b/src/ptp/tb/taxi_ptp_td_phc/test_taxi_ptp_td_phc.py @@ -501,7 +501,9 @@ async def run_drift_adjustment(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -523,7 +525,7 @@ def test_taxi_ptp_td_phc(request): toplevel = dut verilog_sources = [ - os.path.join(rtl_dir, "ptp", f"{dut}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/ptp/taxi_ptp_td_rel2tod/Makefile b/src/ptp/tb/taxi_ptp_td_rel2tod/Makefile similarity index 88% rename from tb/ptp/taxi_ptp_td_rel2tod/Makefile rename to src/ptp/tb/taxi_ptp_td_rel2tod/Makefile index e64d0fb..0f20389 100644 --- a/tb/ptp/taxi_ptp_td_rel2tod/Makefile +++ b/src/ptp/tb/taxi_ptp_td_rel2tod/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_ptp_td_rel2tod COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/ptp/taxi_ptp_td_rel2tod/ptp_td.py b/src/ptp/tb/taxi_ptp_td_rel2tod/ptp_td.py similarity index 100% rename from tb/ptp/taxi_ptp_td_rel2tod/ptp_td.py rename to src/ptp/tb/taxi_ptp_td_rel2tod/ptp_td.py diff --git a/tb/ptp/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.py b/src/ptp/tb/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.py similarity index 94% rename from tb/ptp/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.py rename to src/ptp/tb/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.py index 5d199cb..abebe88 100644 --- a/tb/ptp/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.py +++ b/src/ptp/tb/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.py @@ -137,7 +137,9 @@ async def run_test(dut): # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -160,8 +162,8 @@ def test_taxi_ptp_td_rel2tod(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "ptp", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/ptp/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.sv b/src/ptp/tb/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.sv similarity index 100% rename from tb/ptp/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.sv rename to src/ptp/tb/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.sv diff --git a/src/stats/lib/taxi b/src/stats/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/stats/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/rtl/stats/taxi_stats_collect.sv b/src/stats/rtl/taxi_stats_collect.sv similarity index 100% rename from rtl/stats/taxi_stats_collect.sv rename to src/stats/rtl/taxi_stats_collect.sv diff --git a/rtl/stats/taxi_stats_counter.sv b/src/stats/rtl/taxi_stats_counter.sv similarity index 100% rename from rtl/stats/taxi_stats_counter.sv rename to src/stats/rtl/taxi_stats_counter.sv diff --git a/rtl/stats/taxi_stats_strings_full.sv b/src/stats/rtl/taxi_stats_strings_full.sv similarity index 100% rename from rtl/stats/taxi_stats_strings_full.sv rename to src/stats/rtl/taxi_stats_strings_full.sv diff --git a/tb/stats/taxi_stats_collect/Makefile b/src/stats/tb/taxi_stats_collect/Makefile similarity index 89% rename from tb/stats/taxi_stats_collect/Makefile rename to src/stats/tb/taxi_stats_collect/Makefile index 85d2052..4f3a598 100644 --- a/tb/stats/taxi_stats_collect/Makefile +++ b/src/stats/tb/taxi_stats_collect/Makefile @@ -13,14 +13,18 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_stats_collect COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/stats/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/stats/taxi_stats_collect/test_taxi_stats_collect.py b/src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.py similarity index 96% rename from tb/stats/taxi_stats_collect/test_taxi_stats_collect.py rename to src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.py index 035b227..077b1e6 100644 --- a/tb/stats/taxi_stats_collect/test_taxi_stats_collect.py +++ b/src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.py @@ -292,7 +292,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -315,8 +317,8 @@ def test_taxi_stats_collect(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "stats", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv b/src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.sv similarity index 100% rename from tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv rename to src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.sv diff --git a/tb/stats/taxi_stats_counter/Makefile b/src/stats/tb/taxi_stats_counter/Makefile similarity index 86% rename from tb/stats/taxi_stats_counter/Makefile rename to src/stats/tb/taxi_stats_counter/Makefile index 1a821f4..f0844eb 100644 --- a/tb/stats/taxi_stats_counter/Makefile +++ b/src/stats/tb/taxi_stats_counter/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_stats_counter COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/stats/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/stats/taxi_stats_counter/test_taxi_stats_counter.py b/src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.py similarity index 93% rename from tb/stats/taxi_stats_counter/test_taxi_stats_counter.py rename to src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.py index 402e6d4..183c5f4 100644 --- a/tb/stats/taxi_stats_counter/test_taxi_stats_counter.py +++ b/src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.py @@ -171,7 +171,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -195,9 +197,9 @@ def test_taxi_stats_counter(request, stat_count_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "stats", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), - os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), + os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/stats/taxi_stats_counter/test_taxi_stats_counter.sv b/src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.sv similarity index 100% rename from tb/stats/taxi_stats_counter/test_taxi_stats_counter.sv rename to src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.sv diff --git a/tb/stats/taxi_stats_strings_full/Makefile b/src/stats/tb/taxi_stats_strings_full/Makefile similarity index 86% rename from tb/stats/taxi_stats_strings_full/Makefile rename to src/stats/tb/taxi_stats_strings_full/Makefile index a6343a1..fdecb83 100644 --- a/tb/stats/taxi_stats_strings_full/Makefile +++ b/src/stats/tb/taxi_stats_strings_full/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_stats_strings_full COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/stats/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/stats/taxi_stats_strings_full/test_taxi_stats_strings_full.py b/src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.py similarity index 92% rename from tb/stats/taxi_stats_strings_full/test_taxi_stats_strings_full.py rename to src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.py index 8059760..06814ed 100644 --- a/tb/stats/taxi_stats_strings_full/test_taxi_stats_strings_full.py +++ b/src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.py @@ -126,7 +126,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -149,9 +151,9 @@ def test_taxi_stats_strings_full(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "stats", f"{dut}.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), - os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), + os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/stats/taxi_stats_strings_full/test_taxi_stats_strings_full.sv b/src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.sv similarity index 100% rename from tb/stats/taxi_stats_strings_full/test_taxi_stats_strings_full.sv rename to src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.sv diff --git a/rtl/sync/taxi_sync_reset.sv b/src/sync/rtl/taxi_sync_reset.sv similarity index 100% rename from rtl/sync/taxi_sync_reset.sv rename to src/sync/rtl/taxi_sync_reset.sv diff --git a/rtl/sync/taxi_sync_signal.sv b/src/sync/rtl/taxi_sync_signal.sv similarity index 100% rename from rtl/sync/taxi_sync_signal.sv rename to src/sync/rtl/taxi_sync_signal.sv diff --git a/syn/vivado/taxi_sync_reset.tcl b/src/sync/syn/vivado/taxi_sync_reset.tcl similarity index 100% rename from syn/vivado/taxi_sync_reset.tcl rename to src/sync/syn/vivado/taxi_sync_reset.tcl diff --git a/syn/vivado/taxi_sync_signal.tcl b/src/sync/syn/vivado/taxi_sync_signal.tcl similarity index 100% rename from syn/vivado/taxi_sync_signal.tcl rename to src/sync/syn/vivado/taxi_sync_signal.tcl diff --git a/src/xfcp/lib/taxi b/src/xfcp/lib/taxi new file mode 120000 index 0000000..1b20c9f --- /dev/null +++ b/src/xfcp/lib/taxi @@ -0,0 +1 @@ +../../../ \ No newline at end of file diff --git a/src/xfcp/rtl/taxi_xfcp_if_uart.f b/src/xfcp/rtl/taxi_xfcp_if_uart.f new file mode 100644 index 0000000..cb30e7c --- /dev/null +++ b/src/xfcp/rtl/taxi_xfcp_if_uart.f @@ -0,0 +1,5 @@ +taxi_xfcp_if_uart.sv +../lib/taxi/src/lss/rtl/taxi_uart.f +../lib/taxi/src/axis/rtl/taxi_axis_fifo.sv +../lib/taxi/src/axis/rtl/taxi_axis_cobs_encode.f +../lib/taxi/src/axis/rtl/taxi_axis_cobs_decode.sv \ No newline at end of file diff --git a/rtl/xfcp/taxi_xfcp_if_uart.sv b/src/xfcp/rtl/taxi_xfcp_if_uart.sv similarity index 100% rename from rtl/xfcp/taxi_xfcp_if_uart.sv rename to src/xfcp/rtl/taxi_xfcp_if_uart.sv diff --git a/src/xfcp/rtl/taxi_xfcp_mod_axi.f b/src/xfcp/rtl/taxi_xfcp_mod_axi.f new file mode 100644 index 0000000..04b8c4c --- /dev/null +++ b/src/xfcp/rtl/taxi_xfcp_mod_axi.f @@ -0,0 +1,5 @@ +taxi_xfcp_mod_axi.sv +taxi_xfcp_mod_axil.sv +../lib/taxi/src/axi/rtl/taxi_axi_if.sv +../lib/taxi/src/axi/rtl/taxi_axil_if.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/xfcp/taxi_xfcp_mod_axi.sv b/src/xfcp/rtl/taxi_xfcp_mod_axi.sv similarity index 100% rename from rtl/xfcp/taxi_xfcp_mod_axi.sv rename to src/xfcp/rtl/taxi_xfcp_mod_axi.sv diff --git a/rtl/xfcp/taxi_xfcp_mod_axil.sv b/src/xfcp/rtl/taxi_xfcp_mod_axil.sv similarity index 100% rename from rtl/xfcp/taxi_xfcp_mod_axil.sv rename to src/xfcp/rtl/taxi_xfcp_mod_axil.sv diff --git a/src/xfcp/rtl/taxi_xfcp_mod_i2c_master.f b/src/xfcp/rtl/taxi_xfcp_mod_i2c_master.f new file mode 100644 index 0000000..e295bcf --- /dev/null +++ b/src/xfcp/rtl/taxi_xfcp_mod_i2c_master.f @@ -0,0 +1,3 @@ +taxi_xfcp_mod_i2c_master.sv +../lib/taxi/src/lss/rtl/taxi_i2c_master.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/xfcp/taxi_xfcp_mod_i2c_master.sv b/src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv similarity index 100% rename from rtl/xfcp/taxi_xfcp_mod_i2c_master.sv rename to src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv diff --git a/src/xfcp/rtl/taxi_xfcp_mod_stats.f b/src/xfcp/rtl/taxi_xfcp_mod_stats.f new file mode 100644 index 0000000..29bdc59 --- /dev/null +++ b/src/xfcp/rtl/taxi_xfcp_mod_stats.f @@ -0,0 +1,7 @@ +taxi_xfcp_mod_stats.sv +taxi_xfcp_mod_axil.sv +taxi_xfcp_switch.f +../lib/taxi/src/stats/rtl/taxi_stats_counter.sv +../lib/taxi/src/stats/rtl/taxi_stats_strings_full.sv +../lib/taxi/src/axi/rtl/taxi_axil_if.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/xfcp/taxi_xfcp_mod_stats.sv b/src/xfcp/rtl/taxi_xfcp_mod_stats.sv similarity index 100% rename from rtl/xfcp/taxi_xfcp_mod_stats.sv rename to src/xfcp/rtl/taxi_xfcp_mod_stats.sv diff --git a/src/xfcp/rtl/taxi_xfcp_switch.f b/src/xfcp/rtl/taxi_xfcp_switch.f new file mode 100644 index 0000000..6d37081 --- /dev/null +++ b/src/xfcp/rtl/taxi_xfcp_switch.f @@ -0,0 +1,4 @@ +taxi_xfcp_switch.sv +../lib/taxi/src/prim/rtl/taxi_arbiter.sv +../lib/taxi/src/prim/rtl/taxi_penc.sv +../lib/taxi/src/axis/rtl/taxi_axis_if.sv diff --git a/rtl/xfcp/taxi_xfcp_switch.sv b/src/xfcp/rtl/taxi_xfcp_switch.sv similarity index 100% rename from rtl/xfcp/taxi_xfcp_switch.sv rename to src/xfcp/rtl/taxi_xfcp_switch.sv diff --git a/tb/xfcp/taxi_xfcp_if_uart/Makefile b/src/xfcp/tb/taxi_xfcp_if_uart/Makefile similarity index 92% rename from tb/xfcp/taxi_xfcp_if_uart/Makefile rename to src/xfcp/tb/taxi_xfcp_if_uart/Makefile index 1978004..b919619 100644 --- a/tb/xfcp/taxi_xfcp_if_uart/Makefile +++ b/src/xfcp/tb/taxi_xfcp_if_uart/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_xfcp_if_uart COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/xfcp/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/xfcp/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py b/src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py similarity index 95% rename from tb/xfcp/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py rename to src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py index a29ecc4..8c60bf0 100644 --- a/tb/xfcp/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py +++ b/src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py @@ -150,7 +150,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -174,7 +176,7 @@ def test_taxi_xfcp_if_uart(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "xfcp", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/xfcp/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv b/src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv similarity index 100% rename from tb/xfcp/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv rename to src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv diff --git a/tb/xfcp/taxi_xfcp_if_uart/xfcp.py b/src/xfcp/tb/taxi_xfcp_if_uart/xfcp.py similarity index 100% rename from tb/xfcp/taxi_xfcp_if_uart/xfcp.py rename to src/xfcp/tb/taxi_xfcp_if_uart/xfcp.py diff --git a/tb/xfcp/taxi_xfcp_mod_axi/Makefile b/src/xfcp/tb/taxi_xfcp_mod_axi/Makefile similarity index 92% rename from tb/xfcp/taxi_xfcp_mod_axi/Makefile rename to src/xfcp/tb/taxi_xfcp_mod_axi/Makefile index 82b726a..c6e29b3 100644 --- a/tb/xfcp/taxi_xfcp_mod_axi/Makefile +++ b/src/xfcp/tb/taxi_xfcp_mod_axi/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_xfcp_mod_axi COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/xfcp/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/xfcp/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.py b/src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.py similarity index 96% rename from tb/xfcp/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.py rename to src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.py index 85b3dfd..0ae523b 100644 --- a/tb/xfcp/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.py +++ b/src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.py @@ -204,7 +204,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -229,7 +231,7 @@ def test_taxi_xfcp_mod_axi(request, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "xfcp", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/xfcp/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv b/src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv similarity index 100% rename from tb/xfcp/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv rename to src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv diff --git a/tb/xfcp/taxi_xfcp_mod_axi/xfcp.py b/src/xfcp/tb/taxi_xfcp_mod_axi/xfcp.py similarity index 100% rename from tb/xfcp/taxi_xfcp_mod_axi/xfcp.py rename to src/xfcp/tb/taxi_xfcp_mod_axi/xfcp.py diff --git a/tb/xfcp/taxi_xfcp_mod_axil/Makefile b/src/xfcp/tb/taxi_xfcp_mod_axil/Makefile similarity index 85% rename from tb/xfcp/taxi_xfcp_mod_axil/Makefile rename to src/xfcp/tb/taxi_xfcp_mod_axil/Makefile index e017313..e0cfb03 100644 --- a/tb/xfcp/taxi_xfcp_mod_axil/Makefile +++ b/src/xfcp/tb/taxi_xfcp_mod_axil/Makefile @@ -13,15 +13,19 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_xfcp_mod_axil COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/xfcp/$(DUT).sv -VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv -VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/xfcp/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py b/src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py similarity index 94% rename from tb/xfcp/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py rename to src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py index 4fc8f4b..3960a51 100644 --- a/tb/xfcp/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py +++ b/src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py @@ -204,7 +204,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -229,9 +231,9 @@ def test_taxi_xfcp_mod_axil(request, data_w): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "xfcp", f"{dut}.sv"), - os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"), - os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/xfcp/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv b/src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv similarity index 100% rename from tb/xfcp/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv rename to src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv diff --git a/tb/xfcp/taxi_xfcp_mod_axil/xfcp.py b/src/xfcp/tb/taxi_xfcp_mod_axil/xfcp.py similarity index 100% rename from tb/xfcp/taxi_xfcp_mod_axil/xfcp.py rename to src/xfcp/tb/taxi_xfcp_mod_axil/xfcp.py diff --git a/tb/xfcp/taxi_xfcp_mod_i2c_master/Makefile b/src/xfcp/tb/taxi_xfcp_mod_i2c_master/Makefile similarity index 92% rename from tb/xfcp/taxi_xfcp_mod_i2c_master/Makefile rename to src/xfcp/tb/taxi_xfcp_mod_i2c_master/Makefile index c5cfe31..9e875a0 100644 --- a/tb/xfcp/taxi_xfcp_mod_i2c_master/Makefile +++ b/src/xfcp/tb/taxi_xfcp_mod_i2c_master/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_xfcp_mod_i2c_master COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/xfcp/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/xfcp/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.py b/src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.py similarity index 97% rename from tb/xfcp/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.py rename to src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.py index 8780f16..3693f36 100644 --- a/tb/xfcp/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.py +++ b/src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.py @@ -315,7 +315,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -339,7 +341,7 @@ def test_taxi_xfcp_mod_i2c_master(request): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "xfcp", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/xfcp/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv b/src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv similarity index 100% rename from tb/xfcp/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv rename to src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv diff --git a/tb/xfcp/taxi_xfcp_mod_i2c_master/xfcp.py b/src/xfcp/tb/taxi_xfcp_mod_i2c_master/xfcp.py similarity index 100% rename from tb/xfcp/taxi_xfcp_mod_i2c_master/xfcp.py rename to src/xfcp/tb/taxi_xfcp_mod_i2c_master/xfcp.py diff --git a/tb/xfcp/taxi_xfcp_switch/Makefile b/src/xfcp/tb/taxi_xfcp_switch/Makefile similarity index 91% rename from tb/xfcp/taxi_xfcp_switch/Makefile rename to src/xfcp/tb/taxi_xfcp_switch/Makefile index 5078a37..31189ad 100644 --- a/tb/xfcp/taxi_xfcp_switch/Makefile +++ b/src/xfcp/tb/taxi_xfcp_switch/Makefile @@ -13,13 +13,17 @@ WAVES ?= 0 COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 1ps +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + DUT = taxi_xfcp_switch COCOTB_TEST_MODULES = test_$(DUT) COCOTB_TOPLEVEL = test_$(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv -VERILOG_SOURCES += ../../../rtl/xfcp/$(DUT).f +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f # handle file list files process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) diff --git a/tb/xfcp/taxi_xfcp_switch/test_taxi_xfcp_switch.py b/src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.py similarity index 96% rename from tb/xfcp/taxi_xfcp_switch/test_taxi_xfcp_switch.py rename to src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.py index be57c1b..da8099e 100644 --- a/tb/xfcp/taxi_xfcp_switch/test_taxi_xfcp_switch.py +++ b/src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.py @@ -191,7 +191,9 @@ if cocotb.SIM_NAME: # cocotb-test tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) def process_f_files(files): @@ -216,7 +218,7 @@ def test_taxi_xfcp_switch(request, ports): verilog_sources = [ os.path.join(tests_dir, f"{toplevel}.sv"), - os.path.join(rtl_dir, "xfcp", f"{dut}.f"), + os.path.join(rtl_dir, f"{dut}.f"), ] verilog_sources = process_f_files(verilog_sources) diff --git a/tb/xfcp/taxi_xfcp_switch/test_taxi_xfcp_switch.sv b/src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.sv similarity index 100% rename from tb/xfcp/taxi_xfcp_switch/test_taxi_xfcp_switch.sv rename to src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.sv diff --git a/tb/xfcp/taxi_xfcp_switch/xfcp.py b/src/xfcp/tb/taxi_xfcp_switch/xfcp.py similarity index 100% rename from tb/xfcp/taxi_xfcp_switch/xfcp.py rename to src/xfcp/tb/taxi_xfcp_switch/xfcp.py diff --git a/tb/xfcp/xfcp.py b/src/xfcp/tb/xfcp.py similarity index 100% rename from tb/xfcp/xfcp.py rename to src/xfcp/tb/xfcp.py diff --git a/tox.ini b/tox.ini index a1b2a4c..f9c3742 100644 --- a/tox.ini +++ b/tox.ini @@ -26,8 +26,7 @@ commands = # pytest configuration [pytest] testpaths = - tb - example + src norecursedirs = lib addopts =