bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-12 18:18:39 -08:00
Code Issues Packages Projects Releases Wiki Activity

Reorganize repository

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-05-18 12:25:59 -07:00
parent 8cdae180a1
commit 66b53d98a2
690 changed files with 2314 additions and 1581 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/sync/syn/vivado/taxi_sync_reset.tcl Normal file
View File

@@ -0,0 +1,18 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# reset synchronizer timing constraints
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_reset || REF_NAME == taxi_sync_reset)}] {
puts "Inserting timing constraints for taxi_sync_reset instance $inst"
# reset synchronization
set reset_ffs [get_cells -quiet -hier "sync_reg_reg[*]" -filter "PARENT == $inst"]
set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
}

15
src/sync/syn/vivado/taxi_sync_signal.tcl Normal file
View File

@@ -0,0 +1,15 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# signal synchronizer timing constraints
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_signal || REF_NAME == taxi_sync_signal)}] {
puts "Inserting timing constraints for taxi_sync_signal instance $inst"
set_false_path -to [get_cells -hier "sync_reg_reg[0][*]" -filter "PARENT == $inst"]
}