diff --git a/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
index 1762a70..c9b3f0d 100644
--- a/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
@@ -346,7 +346,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
         // PHY parameters
         .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-        .DATA_W(MAC_DATA_W),
+        .DATA_W(axis_qsfp_tx[0].DATA_W),
+        .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
         .DIC_EN(1'b1),
         .PTP_TS_EN(PTP_TS_EN),
         .PTP_TD_EN(PTP_TS_EN),
@@ -416,6 +417,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
          */
         .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
 
+        /*
+         * USXGMII autonegotiation
+         */
+        .an_en('{CNT{1'b1}}),
+        .an_restart('{CNT{1'b0}}),
+        .an_speedup('{CNT{1'b0}}),
+        .an_timeout_en('{CNT{1'b1}}),
+        .an_usxgmii_en('{CNT{1'b0}}),
+        .an_usxgmii_auto('{CNT{1'b1}}),
+        .an_intr(),
+        .an_running(),
+        .an_complete(),
+        .an_timeout(),
+        .an_usxgmii_mode(),
+        .an_adv_ability_usxgmii('{CNT{16'h1601}}),
+        .an_lp_adv_ability(),
+        .an_lp_usxgmii_link(),
+        .an_lp_usxgmii_speed(),
+        .an_res_full_duplex(),
+
         /*
          * PTP clock
          */
diff --git a/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv b/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv
index 2ade6aa..8723854 100644
--- a/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv
@@ -468,7 +468,8 @@ taxi_eth_mac_25g_us #(
 
     // MAC/PHY config
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-    .DATA_W(MAC_DATA_W),
+    .DATA_W(axis_sfp_tx[0].DATA_W),
+    .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
     .DIC_EN(1'b1),
     .PTP_TS_EN(PTP_TS_EN),
     .PTP_TD_EN(PTP_TS_EN),
@@ -538,6 +539,26 @@ sfp_mac_inst (
      */
     .m_axis_rx(axis_sfp_rx),
 
+    /*
+     * USXGMII autonegotiation
+     */
+    .an_en('{2{1'b1}}),
+    .an_restart('{2{1'b0}}),
+    .an_speedup('{2{1'b0}}),
+    .an_timeout_en('{2{1'b1}}),
+    .an_usxgmii_en('{2{1'b0}}),
+    .an_usxgmii_auto('{2{1'b1}}),
+    .an_intr(),
+    .an_running(),
+    .an_complete(),
+    .an_timeout(),
+    .an_usxgmii_mode(),
+    .an_adv_ability_usxgmii('{2{16'h1601}}),
+    .an_lp_adv_ability(),
+    .an_lp_usxgmii_link(),
+    .an_lp_usxgmii_speed(),
+    .an_res_full_duplex(),
+
     /*
      * PTP clock
      */
diff --git a/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv b/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv
index f3a1f70..7f1f7ef 100644
--- a/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv
@@ -514,7 +514,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
         // MAC/PHY config
         .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-        .DATA_W(MAC_DATA_W),
+        .DATA_W(eth_gty_axis_tx[0].DATA_W),
+        .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32),
         .DIC_EN(1'b1),
         .PTP_TS_EN(PTP_TS_EN),
         .PTP_TD_EN(PTP_TS_EN),
@@ -590,6 +591,26 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
          */
         .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
 
+        /*
+         * USXGMII autonegotiation
+         */
+        .an_en('{CNT{1'b1}}),
+        .an_restart('{CNT{1'b0}}),
+        .an_speedup('{CNT{1'b0}}),
+        .an_timeout_en('{CNT{1'b1}}),
+        .an_usxgmii_en('{CNT{1'b0}}),
+        .an_usxgmii_auto('{CNT{1'b1}}),
+        .an_intr(),
+        .an_running(),
+        .an_complete(),
+        .an_timeout(),
+        .an_usxgmii_mode(),
+        .an_adv_ability_usxgmii('{CNT{16'h1601}}),
+        .an_lp_adv_ability(),
+        .an_lp_usxgmii_link(),
+        .an_lp_usxgmii_speed(),
+        .an_res_full_duplex(),
+
         /*
          * PTP clock
          */
diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv
index db8d7f2..1288076 100644
--- a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv
@@ -501,7 +501,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
         // MAC/PHY config
         .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-        .DATA_W(MAC_DATA_W),
+        .DATA_W(axis_qsfp_tx[0].DATA_W),
+        .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
         .DIC_EN(1'b1),
         .PTP_TS_EN(PTP_TS_EN),
         .PTP_TD_EN(PTP_TS_EN),
@@ -577,6 +578,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
          */
         .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
 
+        /*
+         * USXGMII autonegotiation
+         */
+        .an_en('{CNT{1'b1}}),
+        .an_restart('{CNT{1'b0}}),
+        .an_speedup('{CNT{1'b0}}),
+        .an_timeout_en('{CNT{1'b1}}),
+        .an_usxgmii_en('{CNT{1'b0}}),
+        .an_usxgmii_auto('{CNT{1'b1}}),
+        .an_intr(),
+        .an_running(),
+        .an_complete(),
+        .an_timeout(),
+        .an_usxgmii_mode(),
+        .an_adv_ability_usxgmii('{CNT{16'h1601}}),
+        .an_lp_adv_ability(),
+        .an_lp_usxgmii_link(),
+        .an_lp_usxgmii_speed(),
+        .an_res_full_duplex(),
+
         /*
          * PTP clock
          */
diff --git a/src/cndm/board/KCU105/fpga/rtl/fpga_core.sv b/src/cndm/board/KCU105/fpga/rtl/fpga_core.sv
index 55f17f1..0a09001 100644
--- a/src/cndm/board/KCU105/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/KCU105/fpga/rtl/fpga_core.sv
@@ -690,7 +690,8 @@ taxi_eth_mac_25g_us #(
 
     // MAC/PHY config
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-    .DATA_W(MAC_DATA_W),
+    .DATA_W(axis_sfp_tx[0].DATA_W),
+    .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
     .DIC_EN(1'b1),
     .PTP_TS_EN(PTP_TS_EN),
     .PTP_TD_EN(PTP_TS_EN),
@@ -767,6 +768,26 @@ sfp_mac_inst (
      */
     .m_axis_rx(axis_sfp_rx),
 
+    /*
+     * USXGMII autonegotiation
+     */
+    .an_en('{2{1'b1}}),
+    .an_restart('{2{1'b0}}),
+    .an_speedup('{2{1'b0}}),
+    .an_timeout_en('{2{1'b1}}),
+    .an_usxgmii_en('{2{1'b0}}),
+    .an_usxgmii_auto('{2{1'b1}}),
+    .an_intr(),
+    .an_running(),
+    .an_complete(),
+    .an_timeout(),
+    .an_usxgmii_mode(),
+    .an_adv_ability_usxgmii('{2{16'h1601}}),
+    .an_lp_adv_ability(),
+    .an_lp_usxgmii_link(),
+    .an_lp_usxgmii_speed(),
+    .an_res_full_duplex(),
+
     /*
      * PTP clock
      */
diff --git a/src/cndm/board/NT200A02/fpga/rtl/fpga_core.sv b/src/cndm/board/NT200A02/fpga/rtl/fpga_core.sv
index e9b3a19..2a3d81f 100644
--- a/src/cndm/board/NT200A02/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/NT200A02/fpga/rtl/fpga_core.sv
@@ -376,7 +376,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
         // MAC/PHY config
         .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-        .DATA_W(MAC_DATA_W),
+        .DATA_W(eth_gty_axis_tx[0].DATA_W),
+        .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32),
         .DIC_EN(1'b1),
         .PTP_TS_EN(PTP_TS_EN),
         .PTP_TD_EN(PTP_TS_EN),
@@ -452,6 +453,26 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
          */
         .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
 
+        /*
+         * USXGMII autonegotiation
+         */
+        .an_en('{CNT{1'b1}}),
+        .an_restart('{CNT{1'b0}}),
+        .an_speedup('{CNT{1'b0}}),
+        .an_timeout_en('{CNT{1'b1}}),
+        .an_usxgmii_en('{CNT{1'b0}}),
+        .an_usxgmii_auto('{CNT{1'b1}}),
+        .an_intr(),
+        .an_running(),
+        .an_complete(),
+        .an_timeout(),
+        .an_usxgmii_mode(),
+        .an_adv_ability_usxgmii('{CNT{16'h1601}}),
+        .an_lp_adv_ability(),
+        .an_lp_usxgmii_link(),
+        .an_lp_usxgmii_speed(),
+        .an_res_full_duplex(),
+
         /*
          * PTP clock
          */
diff --git a/src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv b/src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv
index 9f457fb..501c825 100644
--- a/src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv
@@ -556,7 +556,8 @@ taxi_eth_mac_25g_us #(
 
     // MAC/PHY config
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-    .DATA_W(MAC_DATA_W),
+    .DATA_W(axis_qsfp_tx[0].DATA_W),
+    .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
     .DIC_EN(1'b1),
     .PTP_TS_EN(PTP_TS_EN),
     .PTP_TD_EN(PTP_TS_EN),
@@ -632,6 +633,26 @@ qsfp_mac_inst (
      */
     .m_axis_rx(axis_qsfp_rx),
 
+    /*
+     * USXGMII autonegotiation
+     */
+    .an_en('{4{1'b1}}),
+    .an_restart('{4{1'b0}}),
+    .an_speedup('{4{1'b0}}),
+    .an_timeout_en('{4{1'b1}}),
+    .an_usxgmii_en('{4{1'b0}}),
+    .an_usxgmii_auto('{4{1'b1}}),
+    .an_intr(),
+    .an_running(),
+    .an_complete(),
+    .an_timeout(),
+    .an_usxgmii_mode(),
+    .an_adv_ability_usxgmii('{4{16'h1601}}),
+    .an_lp_adv_ability(),
+    .an_lp_usxgmii_link(),
+    .an_lp_usxgmii_speed(),
+    .an_res_full_duplex(),
+
     /*
      * PTP clock
      */
diff --git a/src/cndm/board/VCU108/fpga/rtl/fpga_core.sv b/src/cndm/board/VCU108/fpga/rtl/fpga_core.sv
index 6dbd874..1416a9e 100644
--- a/src/cndm/board/VCU108/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/VCU108/fpga/rtl/fpga_core.sv
@@ -571,7 +571,8 @@ taxi_eth_mac_25g_us #(
 
     // MAC/PHY config
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-    .DATA_W(MAC_DATA_W),
+    .DATA_W(axis_qsfp_tx[0].DATA_W),
+    .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
     .DIC_EN(1'b1),
     .PTP_TS_EN(PTP_TS_EN),
     .PTP_TD_EN(PTP_TS_EN),
@@ -647,6 +648,26 @@ qsfp_mac_inst (
      */
     .m_axis_rx(axis_qsfp_rx),
 
+    /*
+     * USXGMII autonegotiation
+     */
+    .an_en('{4{1'b1}}),
+    .an_restart('{4{1'b0}}),
+    .an_speedup('{4{1'b0}}),
+    .an_timeout_en('{4{1'b1}}),
+    .an_usxgmii_en('{4{1'b0}}),
+    .an_usxgmii_auto('{4{1'b1}}),
+    .an_intr(),
+    .an_running(),
+    .an_complete(),
+    .an_timeout(),
+    .an_usxgmii_mode(),
+    .an_adv_ability_usxgmii('{4{16'h1601}}),
+    .an_lp_adv_ability(),
+    .an_lp_usxgmii_link(),
+    .an_lp_usxgmii_speed(),
+    .an_res_full_duplex(),
+
     /*
      * PTP clock
      */
diff --git a/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv b/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv
index b4a2a5f..707f370 100644
--- a/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv
@@ -764,7 +764,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
         // MAC/PHY config
         .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-        .DATA_W(MAC_DATA_W),
+        .DATA_W(axis_qsfp_tx[0].DATA_W),
+        .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
         .DIC_EN(1'b1),
         .PTP_TS_EN(PTP_TS_EN),
         .PTP_TD_EN(PTP_TS_EN),
@@ -840,6 +841,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
          */
         .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
 
+        /*
+         * USXGMII autonegotiation
+         */
+        .an_en('{CNT{1'b1}}),
+        .an_restart('{CNT{1'b0}}),
+        .an_speedup('{CNT{1'b0}}),
+        .an_timeout_en('{CNT{1'b1}}),
+        .an_usxgmii_en('{CNT{1'b0}}),
+        .an_usxgmii_auto('{CNT{1'b1}}),
+        .an_intr(),
+        .an_running(),
+        .an_complete(),
+        .an_timeout(),
+        .an_usxgmii_mode(),
+        .an_adv_ability_usxgmii('{CNT{16'h1601}}),
+        .an_lp_adv_ability(),
+        .an_lp_usxgmii_link(),
+        .an_lp_usxgmii_speed(),
+        .an_res_full_duplex(),
+
         /*
          * PTP clock
          */
diff --git a/src/cndm/board/ZCU106/fpga/rtl/fpga_core.sv b/src/cndm/board/ZCU106/fpga/rtl/fpga_core.sv
index 2061847..ce96c13 100644
--- a/src/cndm/board/ZCU106/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/ZCU106/fpga/rtl/fpga_core.sv
@@ -377,7 +377,8 @@ taxi_eth_mac_25g_us #(
 
     // PHY parameters
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-    .DATA_W(MAC_DATA_W),
+    .DATA_W(axis_sfp_tx[0].DATA_W),
+    .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
     .DIC_EN(1'b1),
     .PTP_TS_EN(PTP_TS_EN),
     .PTP_TD_EN(PTP_TS_EN),
@@ -454,6 +455,26 @@ sfp_mac_inst (
      */
     .m_axis_rx(axis_sfp_rx),
 
+    /*
+     * USXGMII autonegotiation
+     */
+    .an_en('{2{1'b1}}),
+    .an_restart('{2{1'b0}}),
+    .an_speedup('{2{1'b0}}),
+    .an_timeout_en('{2{1'b1}}),
+    .an_usxgmii_en('{2{1'b0}}),
+    .an_usxgmii_auto('{2{1'b1}}),
+    .an_intr(),
+    .an_running(),
+    .an_complete(),
+    .an_timeout(),
+    .an_usxgmii_mode(),
+    .an_adv_ability_usxgmii('{2{16'h1601}}),
+    .an_lp_adv_ability(),
+    .an_lp_usxgmii_link(),
+    .an_lp_usxgmii_speed(),
+    .an_res_full_duplex(),
+
     /*
      * PTP clock
      */
diff --git a/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv b/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv
index 8c14daa..1662afb 100644
--- a/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv
+++ b/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv
@@ -389,7 +389,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
         // MAC/PHY config
         .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
-        .DATA_W(MAC_DATA_W),
+        .DATA_W(axis_qsfp_tx[0].DATA_W),
+        .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
         .DIC_EN(1'b1),
         .PTP_TS_EN(PTP_TS_EN),
         .PTP_TD_EN(PTP_TS_EN),
@@ -459,6 +460,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
          */
         .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
 
+        /*
+         * USXGMII autonegotiation
+         */
+        .an_en('{CNT{1'b1}}),
+        .an_restart('{CNT{1'b0}}),
+        .an_speedup('{CNT{1'b0}}),
+        .an_timeout_en('{CNT{1'b1}}),
+        .an_usxgmii_en('{CNT{1'b0}}),
+        .an_usxgmii_auto('{CNT{1'b1}}),
+        .an_intr(),
+        .an_running(),
+        .an_complete(),
+        .an_timeout(),
+        .an_usxgmii_mode(),
+        .an_adv_ability_usxgmii('{CNT{16'h1601}}),
+        .an_lp_adv_ability(),
+        .an_lp_usxgmii_link(),
+        .an_lp_usxgmii_speed(),
+        .an_res_full_duplex(),
+
         /*
          * PTP clock
          */