diff --git a/rtl/axis/taxi_axis_async_fifo.sv b/rtl/axis/taxi_axis_async_fifo.sv new file mode 100644 index 0000000..9ff9c3f --- /dev/null +++ b/rtl/axis/taxi_axis_async_fifo.sv @@ -0,0 +1,903 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream asynchronous FIFO + */ +module taxi_axis_async_fifo # +( + // FIFO depth in words + // KEEP_W words per cycle if KEEP_EN set + // Rounded up to nearest power of 2 cycles + parameter DEPTH = 4096, + // FIFO ramstyle attribute + parameter FIFO_RAMSTYLE = "auto", + // number of RAM pipeline registers + parameter RAM_PIPELINE = 1, + // use output FIFO + // When set, the RAM read enable and pipeline clock enables are removed + parameter logic OUTPUT_FIFO_EN = 1'b0, + // output FIFO ramstyle attribute + parameter OUTPUT_FIFO_RAMSTYLE = "distributed", + // Frame FIFO mode - operate on frames instead of cycles + // When set, m_axis_tvalid will not be deasserted within a frame + // Requires LAST_EN set + parameter logic FRAME_FIFO = 1'b0, + // tuser value for bad frame marker + parameter USER_BAD_FRAME_VALUE = 1'b1, + // tuser mask for bad frame marker + parameter USER_BAD_FRAME_MASK = 1'b1, + // Drop frames larger than FIFO + // Requires FRAME_FIFO set + parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO, + // Drop frames marked bad + // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set + parameter logic DROP_BAD_FRAME = 1'b0, + // Drop incoming frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set + parameter logic DROP_WHEN_FULL = 1'b0, + // Mark incoming frames as bad frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO to be clear + parameter logic MARK_WHEN_FULL = 1'b0, + // Enable pause request input + parameter logic PAUSE_EN = 1'b0, + // Pause between frames + parameter logic FRAME_PAUSE = FRAME_FIFO +) +( + /* + * AXI4-Stream input (sink) + */ + input wire logic s_clk, + input wire logic s_rst, + taxi_axis_if.snk s_axis, + + /* + * AXI4-Stream output (source) + */ + input wire logic m_clk, + input wire logic m_rst, + taxi_axis_if.src m_axis, + + /* + * Pause + */ + input wire logic s_pause_req = 1'b0, + output wire logic s_pause_ack, + input wire logic m_pause_req = 1'b0, + output wire logic m_pause_ack, + + /* + * Status + */ + output wire logic [$clog2(DEPTH):0] s_status_depth, + output wire logic [$clog2(DEPTH):0] s_status_depth_commit, + output wire logic s_status_overflow, + output wire logic s_status_bad_frame, + output wire logic s_status_good_frame, + output wire logic [$clog2(DEPTH):0] m_status_depth, + output wire logic [$clog2(DEPTH):0] m_status_depth_commit, + output wire logic m_status_overflow, + output wire logic m_status_bad_frame, + output wire logic m_status_good_frame +); + +// extract parameters +localparam DATA_W = s_axis.DATA_W; +localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN; +localparam KEEP_W = s_axis.KEEP_W; +localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN; +localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN; +localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN; +localparam ID_W = s_axis.ID_W; +localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN; +localparam DEST_W = s_axis.DEST_W; +localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN; +localparam USER_W = s_axis.USER_W; + +localparam CL_DEPTH = $clog2(DEPTH); +localparam CL_KEEP_W = $clog2(KEEP_W); +localparam FIFO_AW = (KEEP_EN && KEEP_W > 1) ? $clog2(DEPTH/KEEP_W) : CL_DEPTH; + +localparam OUTPUT_FIFO_AW = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7); + +// check configuration +if (FRAME_FIFO && !LAST_EN) + $fatal(0, "Error: FRAME_FIFO set requires LAST_EN set (instance %m)"); + +if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) + $fatal(0, "Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)"); + +if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) + $fatal(0, "Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); + +if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) + $fatal(0, "Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); + +if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_W{1'b1}}) == 0) + $fatal(0, "Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); + +if (MARK_WHEN_FULL && FRAME_FIFO) + $fatal(0, "Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)"); + +if (MARK_WHEN_FULL && !LAST_EN) + $fatal(0, "Error: MARK_WHEN_FULL set requires LAST_EN set (instance %m)"); + +if (m_axis.DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (KEEP_EN && m_axis.KEEP_W != KEEP_W) + $fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)"); + +localparam KEEP_OFFSET = DATA_W; +localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0); +localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0); +localparam ID_OFFSET = LAST_OFFSET + (LAST_EN ? 1 : 0); +localparam DEST_OFFSET = ID_OFFSET + (ID_EN ? ID_W : 0); +localparam USER_OFFSET = DEST_OFFSET + (DEST_EN ? DEST_W : 0); +localparam WIDTH = USER_OFFSET + (USER_EN ? USER_W : 0); + +function [FIFO_AW:0] bin2gray(input [FIFO_AW:0] b); + bin2gray = b ^ (b >> 1); +endfunction + +function [FIFO_AW:0] gray2bin(input [FIFO_AW:0] g); + for (integer i = 0; i <= FIFO_AW; i = i + 1) begin + gray2bin[i] = ^(g >> i); + end +endfunction + +logic [FIFO_AW:0] wr_ptr_reg = '0; +logic [FIFO_AW:0] wr_ptr_commit_reg = '0; +logic [FIFO_AW:0] wr_ptr_gray_reg = '0; +logic [FIFO_AW:0] wr_ptr_sync_commit_reg = '0; +logic [FIFO_AW:0] rd_ptr_reg = '0; +logic [FIFO_AW:0] rd_ptr_gray_reg = '0; +logic [FIFO_AW:0] wr_ptr_conv_reg = '0; +logic [FIFO_AW:0] rd_ptr_conv_reg = '0; + +logic [FIFO_AW:0] wr_ptr_temp; +logic [FIFO_AW:0] rd_ptr_temp; + +(* SHREG_EXTRACT = "NO" *) +logic [FIFO_AW:0] wr_ptr_gray_sync1_reg = '0; +(* SHREG_EXTRACT = "NO" *) +logic [FIFO_AW:0] wr_ptr_gray_sync2_reg = '0; +(* SHREG_EXTRACT = "NO" *) +logic [FIFO_AW:0] wr_ptr_commit_sync_reg = '0; +(* SHREG_EXTRACT = "NO" *) +logic [FIFO_AW:0] rd_ptr_gray_sync1_reg = '0; +(* SHREG_EXTRACT = "NO" *) +logic [FIFO_AW:0] rd_ptr_gray_sync2_reg = '0; + +logic wr_ptr_update_valid_reg = 1'b0; +logic wr_ptr_update_reg = 1'b0; +(* SHREG_EXTRACT = "NO" *) +logic wr_ptr_update_sync1_reg = 1'b0; +(* SHREG_EXTRACT = "NO" *) +logic wr_ptr_update_sync2_reg = 1'b0; +(* SHREG_EXTRACT = "NO" *) +logic wr_ptr_update_sync3_reg = 1'b0; +(* SHREG_EXTRACT = "NO" *) +logic wr_ptr_update_ack_sync1_reg = 1'b0; +(* SHREG_EXTRACT = "NO" *) +logic wr_ptr_update_ack_sync2_reg = 1'b0; + +(* SHREG_EXTRACT = "NO" *) +logic s_rst_sync1_reg = 1'b1; +(* SHREG_EXTRACT = "NO" *) +logic s_rst_sync2_reg = 1'b1; +(* SHREG_EXTRACT = "NO" *) +logic s_rst_sync3_reg = 1'b1; +(* SHREG_EXTRACT = "NO" *) +logic m_rst_sync1_reg = 1'b1; +(* SHREG_EXTRACT = "NO" *) +logic m_rst_sync2_reg = 1'b1; +(* SHREG_EXTRACT = "NO" *) +logic m_rst_sync3_reg = 1'b1; + +(* ramstyle = "no_rw_check" *) +logic [WIDTH-1:0] mem[(2**FIFO_AW)-1:0]; +logic mem_read_data_valid_reg = 1'b0; + +(* shreg_extract = "no" *) +logic [WIDTH-1:0] mem_rd_data_pipe_reg[RAM_PIPELINE+1-1:0]; +logic [RAM_PIPELINE+1-1:0] mem_rd_valid_pipe_reg = 0; + +// full when first TWO MSBs do NOT match, but rest matches +// (gray code equivalent of first MSB different but rest same) +wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {FIFO_AW-1{1'b0}}}); +// empty when pointers match exactly +wire empty = FRAME_FIFO ? (rd_ptr_reg == wr_ptr_commit_sync_reg) : (rd_ptr_gray_reg == wr_ptr_gray_sync2_reg); +// overflow within packet +wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {FIFO_AW{1'b0}}}); + +// control signals +logic write; +logic read; +logic store_output; + +logic s_frame_reg = 1'b0; +logic m_frame_reg = 1'b0; + +logic drop_frame_reg = 1'b0; +logic mark_frame_reg = 1'b0; +logic send_frame_reg = 1'b0; +logic overflow_reg = 1'b0; +logic bad_frame_reg = 1'b0; +logic good_frame_reg = 1'b0; + +logic m_empty_pipe_reg = 1'b0; +logic m_terminate_frame_reg = 1'b0; + +logic [FIFO_AW:0] s_depth_reg = '0; +logic [FIFO_AW:0] s_depth_commit_reg = '0; +logic [FIFO_AW:0] m_depth_reg = '0; +logic [FIFO_AW:0] m_depth_commit_reg = '0; + +logic overflow_sync1_reg = 1'b0; +logic overflow_sync2_reg = 1'b0; +logic overflow_sync3_reg = 1'b0; +logic overflow_sync4_reg = 1'b0; +logic bad_frame_sync1_reg = 1'b0; +logic bad_frame_sync2_reg = 1'b0; +logic bad_frame_sync3_reg = 1'b0; +logic bad_frame_sync4_reg = 1'b0; +logic good_frame_sync1_reg = 1'b0; +logic good_frame_sync2_reg = 1'b0; +logic good_frame_sync3_reg = 1'b0; +logic good_frame_sync4_reg = 1'b0; + +assign s_axis.tready = (FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL)) && !s_rst_sync3_reg; + +wire [WIDTH-1:0] mem_wr_data; + +generate + assign mem_wr_data[DATA_W-1:0] = s_axis.tdata; + if (KEEP_EN) assign mem_wr_data[KEEP_OFFSET +: KEEP_W] = s_axis.tkeep; + if (STRB_EN) assign mem_wr_data[STRB_OFFSET +: KEEP_W] = s_axis.tstrb; + if (LAST_EN) assign mem_wr_data[LAST_OFFSET] = s_axis.tlast | mark_frame_reg; + if (ID_EN) assign mem_wr_data[ID_OFFSET +: ID_W] = s_axis.tid; + if (DEST_EN) assign mem_wr_data[DEST_OFFSET +: DEST_W] = s_axis.tdest; + if (USER_EN) assign mem_wr_data[USER_OFFSET +: USER_W] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis.tuser; +endgenerate + +wire [WIDTH-1:0] mem_rd_data = mem_rd_data_pipe_reg[RAM_PIPELINE+1-1]; + +wire m_axis_tready_pipe; +wire m_axis_tvalid_pipe = mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1]; + +wire [DATA_W-1:0] m_axis_tdata_pipe = mem_rd_data[DATA_W-1:0]; +wire [KEEP_W-1:0] m_axis_tkeep_pipe; +wire [KEEP_W-1:0] m_axis_tstrb_pipe; +wire m_axis_tlast_pipe; +wire [ID_W-1:0] m_axis_tid_pipe; +wire [DEST_W-1:0] m_axis_tdest_pipe; +wire [USER_W-1:0] m_axis_tuser_pipe; + +if (KEEP_EN) begin + assign m_axis_tkeep_pipe = mem_rd_data[KEEP_OFFSET +: KEEP_W]; +end else begin + assign m_axis_tkeep_pipe = '1; +end + +if (STRB_EN) begin + assign m_axis_tstrb_pipe = mem_rd_data[STRB_OFFSET +: KEEP_W]; +end else begin + assign m_axis_tstrb_pipe = m_axis_tkeep_pipe; +end + +if (LAST_EN) begin + assign m_axis_tlast_pipe = mem_rd_data[LAST_OFFSET] | m_terminate_frame_reg; +end else begin + assign m_axis_tlast_pipe = 1'b1; +end + +if (ID_EN) begin + assign m_axis_tid_pipe = mem_rd_data[ID_OFFSET +: ID_W]; +end else begin + assign m_axis_tid_pipe = '0; +end + +if (DEST_EN) begin + assign m_axis_tdest_pipe = mem_rd_data[DEST_OFFSET +: DEST_W]; +end else begin + assign m_axis_tdest_pipe = '0; +end + +if (USER_EN) begin + assign m_axis_tuser_pipe = m_terminate_frame_reg ? USER_BAD_FRAME_VALUE : mem_rd_data[USER_OFFSET +: USER_W]; +end else begin + assign m_axis_tuser_pipe = '0; +end + +wire m_axis_tready_out; +wire m_axis_tvalid_out; + +wire [DATA_W-1:0] m_axis_tdata_out; +wire [KEEP_W-1:0] m_axis_tkeep_out; +wire [KEEP_W-1:0] m_axis_tstrb_out; +wire m_axis_tlast_out; +wire [ID_W-1:0] m_axis_tid_out; +wire [DEST_W-1:0] m_axis_tdest_out; +wire [USER_W-1:0] m_axis_tuser_out; + +wire pipe_ready; + +assign s_status_depth = (KEEP_EN && KEEP_W > 1) ? {s_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_reg); +assign s_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {s_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_commit_reg); +assign s_status_overflow = overflow_reg; +assign s_status_bad_frame = bad_frame_reg; +assign s_status_good_frame = good_frame_reg; + +assign m_status_depth = (KEEP_EN && KEEP_W > 1) ? {m_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_reg); +assign m_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {m_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_commit_reg); +assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg; +assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg; +assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg; + +// reset synchronization +always_ff @(posedge m_clk or posedge m_rst) begin + if (m_rst) begin + s_rst_sync1_reg <= 1'b1; + end else begin + s_rst_sync1_reg <= 1'b0; + end +end + +always_ff @(posedge s_clk) begin + s_rst_sync2_reg <= s_rst_sync1_reg; + s_rst_sync3_reg <= s_rst_sync2_reg; +end + +always_ff @(posedge s_clk or posedge s_rst) begin + if (s_rst) begin + m_rst_sync1_reg <= 1'b1; + end else begin + m_rst_sync1_reg <= 1'b0; + end +end + +always_ff @(posedge m_clk) begin + m_rst_sync2_reg <= m_rst_sync1_reg; + m_rst_sync3_reg <= m_rst_sync2_reg; +end + +// Write logic +always_ff @(posedge s_clk) begin + overflow_reg <= 1'b0; + bad_frame_reg <= 1'b0; + good_frame_reg <= 1'b0; + + if (FRAME_FIFO && wr_ptr_update_valid_reg) begin + // have updated pointer to sync + if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_sync_commit_reg <= wr_ptr_commit_reg; + wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; + end + end + + if (s_axis.tready && s_axis.tvalid && LAST_EN) begin + // track input frame status + s_frame_reg <= !s_axis.tlast; + end + + if (s_rst_sync3_reg && LAST_EN) begin + // if sink side is reset during transfer, drop partial frame + if (s_frame_reg && !(s_axis.tready && s_axis.tvalid && s_axis.tlast)) begin + drop_frame_reg <= 1'b1; + end + if (s_axis.tready && s_axis.tvalid && !s_axis.tlast) begin + drop_frame_reg <= 1'b1; + end + end + + if (FRAME_FIFO) begin + // frame FIFO mode + if (s_axis.tready && s_axis.tvalid) begin + // transfer in + if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin + // full, packet overflow, or currently dropping frame + // drop frame + drop_frame_reg <= 1'b1; + if (s_axis.tlast) begin + // end of frame, reset write pointer + wr_ptr_temp = wr_ptr_commit_reg; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else begin + mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data; + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + if (s_axis.tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin + // end of frame or send frame + send_frame_reg <= !s_axis.tlast; + if (s_axis.tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis.tuser ^ USER_BAD_FRAME_VALUE)) begin + // bad packet, reset write pointer + wr_ptr_temp = wr_ptr_commit_reg; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + bad_frame_reg <= 1'b1; + end else begin + // good packet or packet overflow, update write pointer + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + + if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_sync_commit_reg <= wr_ptr_temp; + wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; + end else begin + // sync in progress; flag it for later + wr_ptr_update_valid_reg <= 1'b1; + end + + good_frame_reg <= s_axis.tlast; + end + end + end + end else if (s_axis.tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin + // data valid with packet overflow + // update write pointer + send_frame_reg <= 1'b1; + wr_ptr_temp = wr_ptr_reg; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + + if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_sync_commit_reg <= wr_ptr_temp; + wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; + end else begin + // sync in progress; flag it for later + wr_ptr_update_valid_reg <= 1'b1; + end + end + end else begin + // normal FIFO mode + if (s_axis.tready && s_axis.tvalid) begin + if (drop_frame_reg && LAST_EN) begin + // currently dropping frame + if (s_axis.tlast) begin + // end of frame + if (!full && mark_frame_reg && MARK_WHEN_FULL) begin + // terminate marked frame + mark_frame_reg <= 1'b0; + mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data; + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + end + // end of frame, clear drop flag + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin + // full or marking frame + // drop frame; mark if this isn't the first cycle + drop_frame_reg <= 1'b1; + mark_frame_reg <= mark_frame_reg || s_frame_reg; + if (s_axis.tlast) begin + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else begin + // transfer in + mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data; + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + end + end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin + // terminate marked frame + mark_frame_reg <= 1'b0; + mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data; + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + end + end + + if (s_rst_sync3_reg) begin + wr_ptr_reg <= '0; + wr_ptr_commit_reg <= '0; + wr_ptr_gray_reg <= '0; + wr_ptr_sync_commit_reg <= '0; + + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_update_reg <= 1'b0; + end + + if (s_rst) begin + wr_ptr_reg <= '0; + wr_ptr_commit_reg <= '0; + wr_ptr_gray_reg <= '0; + wr_ptr_sync_commit_reg <= '0; + + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_update_reg <= 1'b0; + + s_frame_reg <= 1'b0; + + drop_frame_reg <= 1'b0; + mark_frame_reg <= 1'b0; + send_frame_reg <= 1'b0; + overflow_reg <= 1'b0; + bad_frame_reg <= 1'b0; + good_frame_reg <= 1'b0; + end +end + +// Write-side status +always_ff @(posedge s_clk) begin + rd_ptr_conv_reg <= gray2bin(rd_ptr_gray_sync2_reg); + s_depth_reg <= wr_ptr_reg - rd_ptr_conv_reg; + s_depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_conv_reg; +end + +// pointer synchronization +always_ff @(posedge s_clk) begin + rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg; + rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg; + wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg; + wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg; + + if (s_rst) begin + rd_ptr_gray_sync1_reg <= '0; + rd_ptr_gray_sync2_reg <= '0; + wr_ptr_update_ack_sync1_reg <= 1'b0; + wr_ptr_update_ack_sync2_reg <= 1'b0; + end +end + +always_ff @(posedge m_clk) begin + wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg; + wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg; + if (FRAME_FIFO && wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin + wr_ptr_commit_sync_reg <= wr_ptr_sync_commit_reg; + end + wr_ptr_update_sync1_reg <= wr_ptr_update_reg; + wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg; + wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg; + + if (FRAME_FIFO && m_rst_sync3_reg) begin + wr_ptr_gray_sync1_reg <= '0; + end + + if (m_rst) begin + wr_ptr_gray_sync1_reg <= '0; + wr_ptr_gray_sync2_reg <= '0; + wr_ptr_commit_sync_reg <= '0; + wr_ptr_update_sync1_reg <= 1'b0; + wr_ptr_update_sync2_reg <= 1'b0; + wr_ptr_update_sync3_reg <= 1'b0; + end +end + +// status synchronization +always_ff @(posedge s_clk) begin + overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg; + bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg; + good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg; + + if (s_rst) begin + overflow_sync1_reg <= 1'b0; + bad_frame_sync1_reg <= 1'b0; + good_frame_sync1_reg <= 1'b0; + end +end + +always_ff @(posedge m_clk) begin + overflow_sync2_reg <= overflow_sync1_reg; + overflow_sync3_reg <= overflow_sync2_reg; + overflow_sync4_reg <= overflow_sync3_reg; + bad_frame_sync2_reg <= bad_frame_sync1_reg; + bad_frame_sync3_reg <= bad_frame_sync2_reg; + bad_frame_sync4_reg <= bad_frame_sync3_reg; + good_frame_sync2_reg <= good_frame_sync1_reg; + good_frame_sync3_reg <= good_frame_sync2_reg; + good_frame_sync4_reg <= good_frame_sync3_reg; + + if (m_rst) begin + overflow_sync2_reg <= 1'b0; + overflow_sync3_reg <= 1'b0; + overflow_sync4_reg <= 1'b0; + bad_frame_sync2_reg <= 1'b0; + bad_frame_sync3_reg <= 1'b0; + bad_frame_sync4_reg <= 1'b0; + good_frame_sync2_reg <= 1'b0; + good_frame_sync3_reg <= 1'b0; + good_frame_sync4_reg <= 1'b0; + end +end + +// Read logic +always_ff @(posedge m_clk) begin + if (m_axis_tready_pipe) begin + // output ready; invalidate stage + mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; + m_terminate_frame_reg <= 1'b0; + end + + for (integer j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin + // if (m_axis_tready_pipe || ((~mem_rd_valid_pipe_reg) >> j)) begin + if (m_axis_tready_pipe || ((RAM_PIPELINE+1)'(~mem_rd_valid_pipe_reg) >> j) != 0) begin + // output ready or bubble in pipeline; transfer down pipeline + mem_rd_valid_pipe_reg[j] <= mem_rd_valid_pipe_reg[j-1]; + mem_rd_data_pipe_reg[j] <= mem_rd_data_pipe_reg[j-1]; + mem_rd_valid_pipe_reg[j-1] <= 1'b0; + end + end + + if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg == 0) begin + // output ready or bubble in pipeline; read new data from FIFO + mem_rd_valid_pipe_reg[0] <= 1'b0; + mem_rd_data_pipe_reg[0] <= mem[rd_ptr_reg[FIFO_AW-1:0]]; + if (!empty && !m_rst_sync3_reg && !m_empty_pipe_reg && pipe_ready) begin + // not empty, increment pointer + mem_rd_valid_pipe_reg[0] <= 1'b1; + rd_ptr_temp = rd_ptr_reg + 1; + rd_ptr_reg <= rd_ptr_temp; + rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1); + end + end + + if (m_axis_tvalid_pipe && LAST_EN) begin + // track output frame status + if (m_axis_tlast_pipe && m_axis_tready_pipe) begin + m_frame_reg <= 1'b0; + end else begin + m_frame_reg <= 1'b1; + end + end + + if (m_empty_pipe_reg && mem_rd_valid_pipe_reg == 0 && LAST_EN) begin + // terminate frame + // (only for frame transfers interrupted by source reset) + if (m_frame_reg) begin + mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b1; + m_terminate_frame_reg <= 1'b1; + end + m_empty_pipe_reg <= 1'b0; + end + + if (m_rst_sync3_reg && LAST_EN) begin + // if source side is reset during transfer, drop partial frame + m_empty_pipe_reg <= 1'b1; + end + + if (m_rst_sync3_reg) begin + rd_ptr_reg <= '0; + rd_ptr_gray_reg <= '0; + end + + if (m_rst) begin + rd_ptr_reg <= '0; + rd_ptr_gray_reg <= '0; + mem_rd_valid_pipe_reg <= '0; + m_frame_reg <= 1'b0; + m_empty_pipe_reg <= 1'b0; + m_terminate_frame_reg <= 1'b0; + end +end + +// Read-side status +always_ff @(posedge m_clk) begin + wr_ptr_conv_reg <= gray2bin(wr_ptr_gray_sync2_reg); + m_depth_reg <= wr_ptr_conv_reg - rd_ptr_reg; + m_depth_commit_reg <= FRAME_FIFO ? wr_ptr_commit_sync_reg - rd_ptr_reg : wr_ptr_conv_reg - rd_ptr_reg; +end + +if (!OUTPUT_FIFO_EN) begin + + assign pipe_ready = 1'b1; + + assign m_axis_tready_pipe = m_axis_tready_out; + assign m_axis_tvalid_out = m_axis_tvalid_pipe; + + assign m_axis_tdata_out = m_axis_tdata_pipe; + assign m_axis_tkeep_out = m_axis_tkeep_pipe; + assign m_axis_tstrb_out = m_axis_tstrb_pipe; + assign m_axis_tlast_out = m_axis_tlast_pipe; + assign m_axis_tid_out = m_axis_tid_pipe; + assign m_axis_tdest_out = m_axis_tdest_pipe; + assign m_axis_tuser_out = m_axis_tuser_pipe; + +end else begin : output_fifo + + // output datapath logic + logic [DATA_W-1:0] m_axis_tdata_reg = '0; + logic [KEEP_W-1:0] m_axis_tkeep_reg = '0; + logic [KEEP_W-1:0] m_axis_tstrb_reg = '0; + logic m_axis_tvalid_reg = 1'b0; + logic m_axis_tlast_reg = 1'b0; + logic [ID_W-1:0] m_axis_tid_reg = '0; + logic [DEST_W-1:0] m_axis_tdest_reg = '0; + logic [USER_W-1:0] m_axis_tuser_reg = '0; + + logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = 0; + logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = 0; + logic out_fifo_half_full_reg = 1'b0; + + wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}}); + wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; + + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic out_fifo_tlast[2**OUTPUT_FIFO_AW-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [ID_W-1:0] out_fifo_tid[2**OUTPUT_FIFO_AW-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW-1:0]; + + assign pipe_ready = !out_fifo_half_full_reg; + + assign m_axis_tready_pipe = 1'b1; + + assign m_axis_tdata_out = m_axis_tdata_reg; + assign m_axis_tkeep_out = KEEP_EN ? m_axis_tkeep_reg : '1; + assign m_axis_tstrb_out = STRB_EN ? m_axis_tkeep_reg : m_axis_tkeep_out; + assign m_axis_tvalid_out = m_axis_tvalid_reg; + assign m_axis_tlast_out = LAST_EN ? m_axis_tlast_reg : 1'b1; + assign m_axis_tid_out = ID_EN ? m_axis_tid_reg : '0; + assign m_axis_tdest_out = DEST_EN ? m_axis_tdest_reg : '0; + assign m_axis_tuser_out = USER_EN ? m_axis_tuser_reg : '0; + + always_ff @(posedge m_clk) begin + m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out; + + out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1); + + if (!out_fifo_full && m_axis_tvalid_pipe) begin + out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdata_pipe; + out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tkeep_pipe; + out_fifo_tstrb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tstrb_pipe; + out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tlast_pipe; + out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tid_pipe; + out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdest_pipe; + out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tuser_pipe; + out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1; + end + + if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin + m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]]; + m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]]; + m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]]; + m_axis_tvalid_reg <= 1'b1; + m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]]; + m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]]; + m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]]; + m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]]; + out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1; + end + + if (m_rst) begin + out_fifo_wr_ptr_reg <= 0; + out_fifo_rd_ptr_reg <= 0; + m_axis_tvalid_reg <= 1'b0; + end + end + +end + +if (PAUSE_EN) begin : pause + + // Pause logic + logic pause_reg = 1'b0; + logic pause_frame_reg = 1'b0; + + logic s_pause_req_sync1_reg; + logic s_pause_req_sync2_reg; + logic s_pause_req_sync3_reg; + logic s_pause_ack_sync1_reg; + logic s_pause_ack_sync2_reg; + logic s_pause_ack_sync3_reg; + + always_ff @(posedge s_clk) begin + s_pause_req_sync1_reg <= s_pause_req; + s_pause_ack_sync2_reg <= s_pause_ack_sync1_reg; + s_pause_ack_sync3_reg <= s_pause_ack_sync2_reg; + end + + always_ff @(posedge m_clk) begin + s_pause_req_sync2_reg <= s_pause_req_sync1_reg; + s_pause_req_sync3_reg <= s_pause_req_sync2_reg; + s_pause_ack_sync1_reg <= pause_reg; + end + + assign m_axis_tready_out = m_axis.tready && !pause_reg; + assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg; + + assign m_axis.tdata = m_axis_tdata_out; + assign m_axis.tkeep = m_axis_tkeep_out; + assign m_axis.tstrb = m_axis_tstrb_out; + assign m_axis.tlast = m_axis_tlast_out; + assign m_axis.tid = m_axis_tid_out; + assign m_axis.tdest = m_axis_tdest_out; + assign m_axis.tuser = m_axis_tuser_out; + + assign s_pause_ack = s_pause_ack_sync3_reg; + assign m_pause_ack = pause_reg; + + always_ff @(posedge m_clk) begin + if (FRAME_PAUSE) begin + if (pause_reg) begin + // paused; update pause status + pause_reg <= m_pause_req || s_pause_req_sync3_reg; + end else if (m_axis_tvalid_out) begin + // frame transfer; set frame bit + pause_frame_reg <= 1'b1; + if (m_axis.tready && m_axis.tlast) begin + // end of frame; clear frame bit and update pause status + pause_frame_reg <= 1'b0; + pause_reg <= m_pause_req || s_pause_req_sync3_reg; + end + end else if (!pause_frame_reg) begin + // idle; update pause status + pause_reg <= m_pause_req || s_pause_req_sync3_reg; + end + end else begin + pause_reg <= m_pause_req || s_pause_req_sync3_reg; + end + + if (m_rst) begin + pause_frame_reg <= 1'b0; + pause_reg <= 1'b0; + end + end + +end else begin + + assign m_axis_tready_out = m_axis.tready; + assign m_axis.tvalid = m_axis_tvalid_out; + + assign m_axis.tdata = m_axis_tdata_out; + assign m_axis.tkeep = m_axis_tkeep_out; + assign m_axis.tstrb = m_axis_tstrb_out; + assign m_axis.tlast = m_axis_tlast_out; + assign m_axis.tid = m_axis_tid_out; + assign m_axis.tdest = m_axis_tdest_out; + assign m_axis.tuser = m_axis_tuser_out; + + assign s_pause_ack = 1'b0; + assign m_pause_ack = 1'b0; + +end + +endmodule + +`resetall diff --git a/syn/vivado/taxi_axis_async_fifo.tcl b/syn/vivado/taxi_axis_async_fifo.tcl new file mode 100644 index 0000000..ebdffce --- /dev/null +++ b/syn/vivado/taxi_axis_async_fifo.tcl @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2019-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# AXI stream asynchronous FIFO timing constraints + +foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_axis_async_fifo || REF_NAME == taxi_axis_async_fifo)}] { + puts "Inserting timing constraints for taxi_axis_async_fifo instance $fifo_inst" + + # get clock periods + set write_clk [get_clocks -of_objects [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"]] + set read_clk [get_clocks -of_objects [get_cells -quiet "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"]] + + set write_clk_period [if {[llength $write_clk]} {get_property -min PERIOD $write_clk} {expr 1.0}] + set read_clk_period [if {[llength $read_clk]} {get_property -min PERIOD $read_clk} {expr 1.0}] + + set min_clk_period [expr min($write_clk_period, $read_clk_period)] + + # reset synchronization + set reset_ffs [get_cells -quiet -hier -regexp ".*/s_rst_sync\[23\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $reset_ffs]} { + set_property ASYNC_REG TRUE $reset_ffs + + # hunt down source + set dest [get_cells $fifo_inst/s_rst_sync2_reg_reg] + set dest_pins [get_pins -of_objects $dest -filter {REF_PIN_NAME == D}] + set net [get_nets -segments -of_objects $dest_pins] + set source_pins [get_pins -of_objects $net -filter {IS_LEAF && DIRECTION == OUT}] + set source [get_cells -of_objects $source_pins] + + set_max_delay -from $source -to $dest -datapath_only $read_clk_period + } + + set reset_ffs [get_cells -quiet -hier -regexp ".*/m_rst_sync\[23\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $reset_ffs]} { + set_property ASYNC_REG TRUE $reset_ffs + + # hunt down source + set dest [get_cells $fifo_inst/m_rst_sync2_reg_reg] + set dest_pins [get_pins -of_objects $dest -filter {REF_PIN_NAME == D}] + set net [get_nets -segments -of_objects $dest_pins] + set source_pins [get_pins -of_objects $net -filter {IS_LEAF && DIRECTION == OUT}] + set source [get_cells -of_objects $source_pins] + + set_max_delay -from $source -to $dest -datapath_only $write_clk_period + } + + # pointer synchronization + set sync_ffs [get_cells -quiet -hier -regexp ".*/rd_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"] -datapath_only $read_clk_period + set_bus_skew -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"] $write_clk_period + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] -datapath_only $write_clk_period + set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] $read_clk_period + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_commit_sync_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] -datapath_only $write_clk_period + set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] $read_clk_period + } + + # output register (needed for distributed RAM sync write/async read) + set output_reg_ffs [get_cells -quiet "$fifo_inst/m_axis_pipe_reg_reg[0][*]"] + + if {[llength $output_reg_ffs]} { + if {[llength $write_clk]} { + set_false_path -from $write_clk -to $output_reg_ffs + } + } + + # frame FIFO pointer update synchronization + set update_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_update(_ack)?_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $update_ffs]} { + set_property ASYNC_REG TRUE $update_ffs + + set_max_delay -from [get_cells "$fifo_inst/wr_ptr_update_reg_reg"] -to [get_cells "$fifo_inst/wr_ptr_update_sync1_reg_reg"] -datapath_only $write_clk_period + set_max_delay -from [get_cells "$fifo_inst/wr_ptr_update_sync3_reg_reg"] -to [get_cells "$fifo_inst/wr_ptr_update_ack_sync1_reg_reg"] -datapath_only $read_clk_period + } + + # status synchronization + foreach i {overflow bad_frame good_frame} { + set status_sync_regs [get_cells -quiet -hier -regexp ".*/${i}_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $status_sync_regs]} { + set_property ASYNC_REG TRUE $status_sync_regs + + set_max_delay -from [get_cells "$fifo_inst/${i}_sync1_reg_reg"] -to [get_cells "$fifo_inst/${i}_sync2_reg_reg"] -datapath_only $read_clk_period + } + } + + # pause sync + set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_req_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_req_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_req_sync2_reg_reg"] -datapath_only $read_clk_period + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_ack_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_ack_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_ack_sync2_reg_reg"] -datapath_only $write_clk_period + } +} diff --git a/tb/axis/taxi_axis_async_fifo/Makefile b/tb/axis/taxi_axis_async_fifo/Makefile new file mode 100644 index 0000000..d95dbaf --- /dev/null +++ b/tb/axis/taxi_axis_async_fifo/Makefile @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2021-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = taxi_axis_async_fifo +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv +VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 8 +export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 ))) +export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 ))) +export PARAM_STRB_EN := 0 +export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_W) ))) +export PARAM_LAST_EN := 1 +export PARAM_ID_EN := 1 +export PARAM_ID_W := 8 +export PARAM_DEST_EN := 1 +export PARAM_DEST_W := 8 +export PARAM_USER_EN := 1 +export PARAM_USER_W := 1 +export PARAM_RAM_PIPELINE := 1 +export PARAM_OUTPUT_FIFO_EN := 0 +export PARAM_FRAME_FIFO := 1 +export PARAM_USER_BAD_FRAME_VALUE := 1 +export PARAM_USER_BAD_FRAME_MASK := 1 +export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) +export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) +export PARAM_DROP_WHEN_FULL := 0 +export PARAM_MARK_WHEN_FULL := 0 +export PARAM_PAUSE_EN := 1 +export PARAM_FRAME_PAUSE := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py b/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py new file mode 100644 index 0000000..235b7dc --- /dev/null +++ b/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py @@ -0,0 +1,734 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + s_clk = int(os.getenv("S_CLK_PERIOD", "10")) + m_clk = int(os.getenv("M_CLK_PERIOD", "11")) + + cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start()) + cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start()) + + self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst) + self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst) + + dut.s_pause_req.setimmediatevalue(0) + dut.m_pause_req.setimmediatevalue(0) + + def set_idle_generator(self, generator=None): + if generator: + self.source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.sink.set_pause_generator(generator()) + + async def reset(self): + self.dut.m_rst.setimmediatevalue(0) + self.dut.s_rst.setimmediatevalue(0) + for k in range(10): + await RisingEdge(self.dut.s_clk) + self.dut.m_rst.value = 1 + self.dut.s_rst.value = 1 + for k in range(10): + await RisingEdge(self.dut.s_clk) + self.dut.m_rst.value = 0 + self.dut.s_rst.value = 0 + for k in range(10): + await RisingEdge(self.dut.s_clk) + + async def reset_source(self): + self.dut.s_rst.setimmediatevalue(0) + for k in range(10): + await RisingEdge(self.dut.s_clk) + self.dut.s_rst.value = 1 + for k in range(10): + await RisingEdge(self.dut.s_clk) + self.dut.s_rst.value = 0 + for k in range(10): + await RisingEdge(self.dut.s_clk) + + async def reset_sink(self): + self.dut.m_rst.setimmediatevalue(0) + for k in range(10): + await RisingEdge(self.dut.m_clk) + self.dut.m_rst.value = 1 + for k in range(10): + await RisingEdge(self.dut.m_clk) + self.dut.m_rst.value = 0 + for k in range(10): + await RisingEdge(self.dut.m_clk) + + +async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + id_count = 2**len(tb.source.bus.tid) + + cur_id = 1 + + await tb.reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for test_data in [payload_data(x) for x in payload_lengths()]: + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id + test_frame.tdest = cur_id + + test_frames.append(test_frame) + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % id_count + + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_tuser_assert(dut): + + tb = TB(dut) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32)) + test_frame = AxiStreamFrame(test_data, tuser=1) + await tb.source.send(test_frame) + + if int(dut.DROP_BAD_FRAME.value): + for k in range(64): + await RisingEdge(dut.s_clk) + + else: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_init_sink_pause(dut): + + tb = TB(dut) + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + for k in range(64): + await RisingEdge(dut.s_clk) + + tb.sink.pause = False + + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_init_sink_pause_reset(dut): + + tb = TB(dut) + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + for k in range(64): + await RisingEdge(dut.s_clk) + + await tb.reset() + + tb.sink.pause = False + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_init_sink_pause_source_reset(dut): + + tb = TB(dut) + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 512)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + for k in range(1024): + await RisingEdge(dut.s_clk) + + await tb.reset_source() + + tb.sink.pause = False + + for k in range(64): + await RisingEdge(dut.s_clk) + + rx_frame = await tb.sink.recv() + + assert rx_frame.tuser + + assert tb.sink.idle() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_init_sink_pause_sink_reset(dut): + + tb = TB(dut) + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + for k in range(64): + await RisingEdge(dut.s_clk) + + await tb.reset_sink() + + tb.sink.pause = False + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_shift_in_source_reset(dut): + + tb = TB(dut) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + for k in range(8): + await RisingEdge(dut.s_clk) + + await tb.reset_source() + + for k in range(64): + await RisingEdge(dut.s_clk) + + if int(dut.FRAME_FIFO.value): + assert tb.sink.empty() + else: + rx_frame = await tb.sink.recv() + + assert rx_frame.tuser + + assert tb.sink.empty() + assert tb.sink.idle() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_shift_in_sink_reset(dut): + + tb = TB(dut) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + for k in range(8): + await RisingEdge(dut.s_clk) + + await tb.reset_sink() + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_shift_out_source_reset(dut): + + tb = TB(dut) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + await RisingEdge(dut.m_axis.tvalid) + + for k in range(8): + await RisingEdge(dut.s_clk) + + await tb.reset_source() + + for k in range(64): + await RisingEdge(dut.s_clk) + + rx_frame = await tb.sink.recv() + + assert rx_frame.tuser + + assert tb.sink.idle() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_shift_out_sink_reset(dut): + + tb = TB(dut) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + await RisingEdge(dut.m_axis.tvalid) + + for k in range(8): + await RisingEdge(dut.s_clk) + + await tb.reset_sink() + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_pause(dut): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes)) + test_frame = AxiStreamFrame(test_data) + + for k in range(16): + await tb.source.send(test_frame) + + for k in range(60): + await RisingEdge(dut.s_clk) + + dut.m_pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + dut.m_pause_req.value = 0 + + for k in range(60): + await RisingEdge(dut.s_clk) + + dut.s_pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + dut.s_pause_req.value = 0 + + for k in range(16): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_overflow(dut): + + tb = TB(dut) + + depth = int(dut.DEPTH.value) + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + tb.sink.pause = True + + size = (16*byte_lanes) + count = depth*2 // size + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size)) + test_frame = AxiStreamFrame(test_data) + for k in range(count): + await tb.source.send(test_frame) + + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.s_clk) + + if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value): + assert tb.source.idle() + else: + assert not tb.source.idle() + + tb.sink.pause = False + + if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value): + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.s_clk) + + rx_count = 0 + + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser: + continue + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + rx_count += 1 + + assert rx_count < count + + else: + for k in range(count): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_oversize(dut): + + tb = TB(dut) + + depth = int(dut.DEPTH.value) + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2)) + test_frame = AxiStreamFrame(test_data) + await tb.source.send(test_frame) + + for k in range((depth//byte_lanes)*2): + await RisingEdge(dut.s_clk) + + tb.sink.pause = False + + if int(dut.DROP_OVERSIZE_FRAME.value): + for k in range((depth//byte_lanes)*2): + await RisingEdge(dut.s_clk) + + else: + rx_frame = await tb.sink.recv() + + if int(dut.MARK_WHEN_FULL.value): + assert rx_frame.tuser + else: + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + id_count = 2**len(tb.source.bus.tid) + + cur_id = 1 + + await tb.reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for k in range(512): + length = random.randint(1, byte_lanes*16) + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id + test_frame.tdest = cur_id + + test_frames.append(test_frame) + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % id_count + + if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value): + cycles = 0 + while cycles < 100: + cycles += 1 + if not tb.source.idle() or int(dut.s_axis.tvalid.value) or int(dut.m_axis.tvalid.value) or int(dut.m_status_depth.value): + cycles = 0 + await RisingEdge(dut.m_clk) + + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser: + continue + + assert not rx_frame.tuser + + while True: + test_frame = test_frames.pop(0) + if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata: + break + + assert len(test_frames) < 512 + + else: + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +def size_list(): + data_width = len(cocotb.top.m_axis.tdata) + byte_width = data_width // 8 + return list(range(1, byte_width*4+1))+[512]+[1]*64 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + for test in [ + run_test_tuser_assert, + run_test_init_sink_pause, + run_test_init_sink_pause_reset, + run_test_init_sink_pause_source_reset, + run_test_init_sink_pause_sink_reset, + run_test_shift_in_source_reset, + run_test_shift_in_sink_reset, + run_test_shift_out_source_reset, + run_test_shift_out_sink_reset, + run_test_pause, + run_test_overflow, + run_test_oversize + ]: + + factory = TestFactory(test) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.dirname(__file__) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize(("s_clk", "m_clk"), [(10, 10), (10, 11), (11, 10)]) +@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", + "drop_when_full", "mark_when_full"), + [(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0), + (1, 1, 1, 1, 0), (0, 0, 0, 0, 1)]) +@pytest.mark.parametrize(("ram_pipeline", "output_fifo"), + [(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)]) +@pytest.mark.parametrize("data_w", [8, 16, 32, 64]) +def test_taxi_axis_async_fifo(request, data_w, ram_pipeline, output_fifo, + frame_fifo, drop_oversize_frame, drop_bad_frame, + drop_when_full, mark_when_full, s_clk, m_clk): + + dut = "taxi_axis_async_fifo" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "axis", f"{dut}.sv"), + os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = data_w + parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8) + parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8 + parameters['STRB_EN'] = 0 + parameters['DEPTH'] = 1024 * parameters['KEEP_W'] + parameters['LAST_EN'] = 1 + parameters['ID_EN'] = 1 + parameters['ID_W'] = 8 + parameters['DEST_EN'] = 1 + parameters['DEST_W'] = 8 + parameters['USER_EN'] = 1 + parameters['USER_W'] = 1 + parameters['RAM_PIPELINE'] = ram_pipeline + parameters['OUTPUT_FIFO_EN'] = output_fifo + parameters['FRAME_FIFO'] = frame_fifo + parameters['USER_BAD_FRAME_VALUE'] = 1 + parameters['USER_BAD_FRAME_MASK'] = 1 + parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame + parameters['DROP_BAD_FRAME'] = drop_bad_frame + parameters['DROP_WHEN_FULL'] = drop_when_full + parameters['MARK_WHEN_FULL'] = mark_when_full + parameters['PAUSE_EN'] = 1 + parameters['FRAME_PAUSE'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + extra_env['S_CLK_PERIOD'] = str(s_clk) + extra_env['M_CLK_PERIOD'] = str(m_clk) + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv b/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv new file mode 100644 index 0000000..18b8697 --- /dev/null +++ b/tb/axis/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream asynchronous FIFO testbench + */ +module test_taxi_axis_async_fifo # +( + /* verilator lint_off WIDTHTRUNC */ + parameter DEPTH = 4096, + parameter DATA_W = 8, + parameter logic KEEP_EN = (DATA_W>8), + parameter KEEP_W = ((DATA_W+7)/8), + parameter logic STRB_EN = 1'b0, + parameter logic LAST_EN = 1'b1, + parameter logic ID_EN = 1'b0, + parameter ID_W = 8, + parameter logic DEST_EN = 1'b0, + parameter DEST_W = 8, + parameter logic USER_EN = 1'b1, + parameter USER_W = 1, + parameter RAM_PIPELINE = 1, + parameter logic OUTPUT_FIFO_EN = 1'b0, + parameter logic FRAME_FIFO = 1'b0, + parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1, + parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1, + parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO, + parameter logic DROP_BAD_FRAME = 1'b0, + parameter logic DROP_WHEN_FULL = 1'b0, + parameter logic MARK_WHEN_FULL = 1'b0, + parameter logic PAUSE_EN = 1'b0, + parameter logic FRAME_PAUSE = FRAME_FIFO + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic s_clk; +logic s_rst; + +logic m_clk; +logic m_rst; + +taxi_axis_if #( + .DATA_W(DATA_W), + .KEEP_EN(KEEP_EN), + .KEEP_W(KEEP_W), + .STRB_EN(STRB_EN), + .LAST_EN(LAST_EN), + .ID_EN(ID_EN), + .ID_W(ID_W), + .DEST_EN(DEST_EN), + .DEST_W(DEST_W), + .USER_EN(USER_EN), + .USER_W(USER_W) +) s_axis(), m_axis(); + +logic s_pause_req; +logic s_pause_ack; +logic m_pause_req; +logic m_pause_ack; + +logic [$clog2(DEPTH):0] s_status_depth; +logic [$clog2(DEPTH):0] s_status_depth_commit; +logic s_status_overflow; +logic s_status_bad_frame; +logic s_status_good_frame; +logic [$clog2(DEPTH):0] m_status_depth; +logic [$clog2(DEPTH):0] m_status_depth_commit; +logic m_status_overflow; +logic m_status_bad_frame; +logic m_status_good_frame; + +taxi_axis_async_fifo #( + .DEPTH(DEPTH), + .RAM_PIPELINE(RAM_PIPELINE), + .OUTPUT_FIFO_EN(OUTPUT_FIFO_EN), + .FRAME_FIFO(FRAME_FIFO), + .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), + .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK), + .DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME), + .DROP_BAD_FRAME(DROP_BAD_FRAME), + .DROP_WHEN_FULL(DROP_WHEN_FULL), + .MARK_WHEN_FULL(MARK_WHEN_FULL), + .PAUSE_EN(PAUSE_EN), + .FRAME_PAUSE(FRAME_PAUSE) +) +uut ( + /* + * AXI4-Stream input (sink) + */ + .s_clk(s_clk), + .s_rst(s_rst), + .s_axis(s_axis), + + /* + * AXI4-Stream output (source) + */ + .m_clk(m_clk), + .m_rst(m_rst), + .m_axis(m_axis), + + /* + * Pause + */ + .s_pause_req(s_pause_req), + .s_pause_ack(s_pause_ack), + .m_pause_req(m_pause_req), + .m_pause_ack(m_pause_ack), + + /* + * Status + */ + .s_status_depth(s_status_depth), + .s_status_depth_commit(s_status_depth_commit), + .s_status_overflow(s_status_overflow), + .s_status_bad_frame(s_status_bad_frame), + .s_status_good_frame(s_status_good_frame), + .m_status_depth(m_status_depth), + .m_status_depth_commit(m_status_depth_commit), + .m_status_overflow(m_status_overflow), + .m_status_bad_frame(m_status_bad_frame), + .m_status_good_frame(m_status_good_frame) +); + +endmodule + +`resetall