diff --git a/example/Arty/fpga/rtl/fpga.sv b/example/Arty/fpga/rtl/fpga.sv
index 4105aaa..6c25f6a 100644
--- a/example/Arty/fpga/rtl/fpga.sv
+++ b/example/Arty/fpga/rtl/fpga.sv
@@ -20,9 +20,9 @@ module fpga #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "artix7"
+    parameter string FAMILY = "artix7"
 )
 (
     /*
diff --git a/example/Arty/fpga/rtl/fpga_core.sv b/example/Arty/fpga/rtl/fpga_core.sv
index 68ee525..fe27baf 100644
--- a/example/Arty/fpga/rtl/fpga_core.sv
+++ b/example/Arty/fpga/rtl/fpga_core.sv
@@ -20,9 +20,9 @@ module fpga_core #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "artix7"
+    parameter string FAMILY = "artix7"
 )
 (
     /*
diff --git a/example/HTG940/fpga/rtl/fpga.sv b/example/HTG940/fpga/rtl/fpga.sv
index b99d4cc..adb077d 100644
--- a/example/HTG940/fpga/rtl/fpga.sv
+++ b/example/HTG940/fpga/rtl/fpga.sv
@@ -20,9 +20,9 @@ module fpga #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "zynquplus",
+    parameter string FAMILY = "zynquplus",
     // Use 90 degree clock for RGMII transmit
     parameter logic USE_CLK90 = 1'b0
 )
diff --git a/example/HTG940/fpga/rtl/fpga_core.sv b/example/HTG940/fpga/rtl/fpga_core.sv
index 3541443..7cff99f 100644
--- a/example/HTG940/fpga/rtl/fpga_core.sv
+++ b/example/HTG940/fpga/rtl/fpga_core.sv
@@ -20,9 +20,9 @@ module fpga_core #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "zynquplus",
+    parameter string FAMILY = "zynquplus",
     // Use 90 degree clock for RGMII transmit
     parameter logic USE_CLK90 = 1'b1
 )
diff --git a/example/KC705/fpga/rtl/fpga.sv b/example/KC705/fpga/rtl/fpga.sv
index f81d36e..843d47f 100644
--- a/example/KC705/fpga/rtl/fpga.sv
+++ b/example/KC705/fpga/rtl/fpga.sv
@@ -20,9 +20,9 @@ module fpga #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "kintex7",
+    parameter string FAMILY = "kintex7",
     // Use 90 degree clock for RGMII transmit
     parameter logic USE_CLK90 = 1'b1,
     // BASE-T PHY type (GMII, RGMII, SGMII)
diff --git a/example/KC705/fpga/rtl/fpga_core.sv b/example/KC705/fpga/rtl/fpga_core.sv
index a7f44a6..5a0080d 100644
--- a/example/KC705/fpga/rtl/fpga_core.sv
+++ b/example/KC705/fpga/rtl/fpga_core.sv
@@ -20,9 +20,9 @@ module fpga_core #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "kintex7",
+    parameter string FAMILY = "kintex7",
     // Use 90 degree clock for RGMII transmit
     parameter logic USE_CLK90 = 1'b1,
     // BASE-T PHY type (GMII, RGMII, SGMII)
diff --git a/example/KR260/fpga/rtl/fpga.sv b/example/KR260/fpga/rtl/fpga.sv
index d7ed8a9..a70ebaa 100644
--- a/example/KR260/fpga/rtl/fpga.sv
+++ b/example/KR260/fpga/rtl/fpga.sv
@@ -20,9 +20,9 @@ module fpga #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "zynquplus",
+    parameter string FAMILY = "zynquplus",
     // Use 90 degree clock for RGMII transmit
     parameter logic USE_CLK90 = 1'b1
 )
diff --git a/example/KR260/fpga/rtl/fpga_core.sv b/example/KR260/fpga/rtl/fpga_core.sv
index 6b87e6f..6ecc47a 100644
--- a/example/KR260/fpga/rtl/fpga_core.sv
+++ b/example/KR260/fpga/rtl/fpga_core.sv
@@ -20,9 +20,9 @@ module fpga_core #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "zynquplus",
+    parameter string FAMILY = "zynquplus",
     // Use 90 degree clock for RGMII transmit
     parameter logic USE_CLK90 = 1'b1
 )
diff --git a/rtl/eth/taxi_eth_mac_1g_gmii.sv b/rtl/eth/taxi_eth_mac_1g_gmii.sv
index 7cbcffd..f9538a7 100644
--- a/rtl/eth/taxi_eth_mac_1g_gmii.sv
+++ b/rtl/eth/taxi_eth_mac_1g_gmii.sv
@@ -18,8 +18,8 @@ Authors:
 module taxi_eth_mac_1g_gmii #
 (
     parameter logic SIM = 1'b0,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
     parameter logic PTP_TS_EN = 1'b0,
diff --git a/rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv b/rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv
index 3a21556..1998524 100644
--- a/rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv
+++ b/rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv
@@ -18,8 +18,8 @@ Authors:
 module taxi_eth_mac_1g_gmii_fifo #
 (
     parameter logic SIM = 1'b0,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
     parameter TX_FIFO_DEPTH = 4096,
diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii.sv b/rtl/eth/taxi_eth_mac_1g_rgmii.sv
index 879d5c2..e46066e 100644
--- a/rtl/eth/taxi_eth_mac_1g_rgmii.sv
+++ b/rtl/eth/taxi_eth_mac_1g_rgmii.sv
@@ -18,8 +18,8 @@ Authors:
 module taxi_eth_mac_1g_rgmii #
 (
     parameter logic SIM = 1'b0,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic USE_CLK90 = 1'b1,
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv b/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv
index 39decca..76c7ab7 100644
--- a/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv
+++ b/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv
@@ -18,8 +18,8 @@ Authors:
 module taxi_eth_mac_1g_rgmii_fifo #
 (
     parameter logic SIM = 1'b0,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic USE_CLK90 = 1'b1,
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
diff --git a/rtl/eth/taxi_eth_mac_mii.sv b/rtl/eth/taxi_eth_mac_mii.sv
index d41ba8e..252139d 100644
--- a/rtl/eth/taxi_eth_mac_mii.sv
+++ b/rtl/eth/taxi_eth_mac_mii.sv
@@ -18,8 +18,8 @@ Authors:
 module taxi_eth_mac_mii #
 (
     parameter logic SIM = 1'b0,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
     parameter logic PTP_TS_EN = 1'b0,
diff --git a/rtl/eth/taxi_eth_mac_mii_fifo.sv b/rtl/eth/taxi_eth_mac_mii_fifo.sv
index cbeb1f8..e7cfd7d 100644
--- a/rtl/eth/taxi_eth_mac_mii_fifo.sv
+++ b/rtl/eth/taxi_eth_mac_mii_fifo.sv
@@ -18,8 +18,8 @@ Authors:
 module taxi_eth_mac_mii_fifo #
 (
     parameter logic SIM = 1'b0,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
     parameter TX_FIFO_DEPTH = 4096,
diff --git a/rtl/io/taxi_iddr.sv b/rtl/io/taxi_iddr.sv
index 8e20984..a7cbb7d 100644
--- a/rtl/io/taxi_iddr.sv
+++ b/rtl/io/taxi_iddr.sv
@@ -20,9 +20,9 @@ module taxi_iddr #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/rtl/io/taxi_oddr.sv b/rtl/io/taxi_oddr.sv
index 369a8d1..d036cef 100644
--- a/rtl/io/taxi_oddr.sv
+++ b/rtl/io/taxi_oddr.sv
@@ -20,9 +20,9 @@ module taxi_oddr #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/rtl/io/taxi_ssio_ddr_in.sv b/rtl/io/taxi_ssio_ddr_in.sv
index b8a8b60..d322408 100644
--- a/rtl/io/taxi_ssio_ddr_in.sv
+++ b/rtl/io/taxi_ssio_ddr_in.sv
@@ -20,9 +20,9 @@ module taxi_ssio_ddr_in #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/rtl/io/taxi_ssio_ddr_in_diff.sv b/rtl/io/taxi_ssio_ddr_in_diff.sv
index dcd47d5..2bdb117 100644
--- a/rtl/io/taxi_ssio_ddr_in_diff.sv
+++ b/rtl/io/taxi_ssio_ddr_in_diff.sv
@@ -20,9 +20,9 @@ module taxi_ssio_ddr_in_diff #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/rtl/io/taxi_ssio_ddr_out.sv b/rtl/io/taxi_ssio_ddr_out.sv
index 7927c78..af6154d 100644
--- a/rtl/io/taxi_ssio_ddr_out.sv
+++ b/rtl/io/taxi_ssio_ddr_out.sv
@@ -20,9 +20,9 @@ module taxi_ssio_ddr_out #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Use 90 degree clock for transmit
     parameter logic USE_CLK90 = 1'b1,
     // Width of register in bits
diff --git a/rtl/io/taxi_ssio_ddr_out_diff.sv b/rtl/io/taxi_ssio_ddr_out_diff.sv
index 90a1eda..033e0e2 100644
--- a/rtl/io/taxi_ssio_ddr_out_diff.sv
+++ b/rtl/io/taxi_ssio_ddr_out_diff.sv
@@ -20,9 +20,9 @@ module taxi_ssio_ddr_out_diff #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Use 90 degree clock for transmit
     parameter logic USE_CLK90 = 1'b1,
     // Width of register in bits
diff --git a/rtl/io/taxi_ssio_sdr_in.sv b/rtl/io/taxi_ssio_sdr_in.sv
index f4942b4..dcf41e1 100644
--- a/rtl/io/taxi_ssio_sdr_in.sv
+++ b/rtl/io/taxi_ssio_sdr_in.sv
@@ -20,9 +20,9 @@ module taxi_ssio_sdr_in #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/rtl/io/taxi_ssio_sdr_in_diff.sv b/rtl/io/taxi_ssio_sdr_in_diff.sv
index 4c21418..6bb214c 100644
--- a/rtl/io/taxi_ssio_sdr_in_diff.sv
+++ b/rtl/io/taxi_ssio_sdr_in_diff.sv
@@ -20,9 +20,9 @@ module ssio_sdr_in_diff #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/rtl/io/taxi_ssio_sdr_out.sv b/rtl/io/taxi_ssio_sdr_out.sv
index d19dc28..e4acb0f 100644
--- a/rtl/io/taxi_ssio_sdr_out.sv
+++ b/rtl/io/taxi_ssio_sdr_out.sv
@@ -20,9 +20,9 @@ module taxi_ssio_sdr_out #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/rtl/io/taxi_ssio_sdr_out_diff.sv b/rtl/io/taxi_ssio_sdr_out_diff.sv
index 84fba78..885d5e8 100644
--- a/rtl/io/taxi_ssio_sdr_out_diff.sv
+++ b/rtl/io/taxi_ssio_sdr_out_diff.sv
@@ -20,9 +20,9 @@ module taxi_ssio_sdr_out_diff #
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
     // vendor ("GENERIC", "XILINX", "ALTERA")
-    parameter VENDOR = "XILINX",
+    parameter string VENDOR = "XILINX",
     // device family
-    parameter FAMILY = "virtex7",
+    parameter string FAMILY = "virtex7",
     // Width of register in bits
     parameter WIDTH = 1
 )
diff --git a/tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv b/tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
index fa31805..99c8dbf 100644
--- a/tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
+++ b/tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_gmii #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter logic SIM = 1'b1,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
     parameter logic PTP_TS_EN = 1'b0,
diff --git a/tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv b/tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv
index 63d6441..679edc7 100644
--- a/tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv
+++ b/tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv
@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_gmii_fifo #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter logic SIM = 1'b1,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter AXIS_DATA_W = 8,
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
diff --git a/tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv b/tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
index b3884b8..186156d 100644
--- a/tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
+++ b/tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_rgmii #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter logic SIM = 1'b1,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic USE_CLK90 = 1'b1,
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
diff --git a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
index 7f105f3..e17c0b2 100644
--- a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
+++ b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_rgmii_fifo #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter logic SIM = 1'b1,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic USE_CLK90 = 1'b1,
     parameter AXIS_DATA_W = 8,
     parameter logic PADDING_EN = 1'b1,
diff --git a/tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv b/tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
index 976d11a..109fdc0 100644
--- a/tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
+++ b/tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
@@ -19,8 +19,8 @@ module test_taxi_eth_mac_mii #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter logic SIM = 1'b1,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,
     parameter logic PTP_TS_EN = 1'b0,
diff --git a/tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv b/tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv
index b78795f..4e988ea 100644
--- a/tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv
+++ b/tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv
@@ -19,8 +19,8 @@ module test_taxi_eth_mac_mii_fifo #
 (
     /* verilator lint_off WIDTHTRUNC */
     parameter logic SIM = 1'b1,
-    parameter VENDOR = "XILINX",
-    parameter FAMILY = "virtex7",
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
     parameter AXIS_DATA_W = 8,
     parameter logic PADDING_EN = 1'b1,
     parameter MIN_FRAME_LEN = 64,