From 6c9026bccf0b2694a1d628ca9c51d83079f164b5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 5 Sep 2025 07:15:26 -0700 Subject: [PATCH] eth/example/HTG9200: Fix refclock frequency in testbench Signed-off-by: Alex Forencich --- src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py index f388680..c2379c9 100644 --- a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py @@ -111,7 +111,7 @@ class TB: await RisingEdge(self.dut.clk_125mhz) async def _run_refclk(self): - t = Timer(3.2, 'ns') + t = Timer(3.102, 'ns') val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1 while True: self.dut.eth_gty_mgt_refclk_p.value = val