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eth/example/HTG9200: Fix refclock frequency in testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-09-05 07:15:26 -07:00
parent 2ae5b5fae3
commit 6c9026bccf
1 changed files with 1 additions and 1 deletions
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2
src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
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@@ -111,7 +111,7 @@ class TB:
await RisingEdge(self.dut.clk_125mhz) await RisingEdge(self.dut.clk_125mhz)
async def _run_refclk(self): async def _run_refclk(self):
t = Timer(3.2, 'ns') t = Timer(3.102, 'ns')
val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1 val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
while True: while True:
self.dut.eth_gty_mgt_refclk_p.value = val self.dut.eth_gty_mgt_refclk_p.value = val