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pcie: Use SV enums in PCIe logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-02-27 15:55:34 -08:00
parent 1740e09a8a
commit 6cf03d6435
5 changed files with 77 additions and 62 deletions
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40
src/pcie/rtl/taxi_pcie_axil_master.sv
View File

@@ -89,36 +89,40 @@ if (AXIL_DATA_W != 32)
if (AXIL_STRB_W * 8 != AXIL_DATA_W)
$fatal(0, "Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
localparam [2:0]
typedef enum logic [2:0] {
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
TLP_FMT_PREFIX = 3'b100
} tlp_fmt_t;
localparam [2:0]
typedef enum logic [2:0] {
CPL_STATUS_SC = 3'b000, // successful completion
CPL_STATUS_UR = 3'b001, // unsupported request
CPL_STATUS_CRS = 3'b010, // configuration request retry status
CPL_STATUS_CA = 3'b100; // completer abort
CPL_STATUS_CA = 3'b100 // completer abort
} cpl_status_t;
localparam [2:0]
REQ_STATE_IDLE = 3'd0,
REQ_STATE_READ_1 = 3'd1,
REQ_STATE_READ_2 = 3'd2,
REQ_STATE_WRITE_1 = 3'd3,
REQ_STATE_WRITE_2 = 3'd4,
REQ_STATE_WAIT_END = 3'd5;
typedef enum logic [2:0] {
REQ_STATE_IDLE,
REQ_STATE_READ_1,
REQ_STATE_READ_2,
REQ_STATE_WRITE_1,
REQ_STATE_WRITE_2,
REQ_STATE_WAIT_END
} req_state_t;
logic [2:0] req_state_reg = REQ_STATE_IDLE, req_state_next;
req_state_t req_state_reg = REQ_STATE_IDLE, req_state_next;
localparam [1:0]
RESP_STATE_IDLE = 2'd0,
RESP_STATE_READ = 2'd1,
RESP_STATE_WRITE = 2'd2,
RESP_STATE_CPL = 2'd3;
typedef enum logic [1:0] {
RESP_STATE_IDLE,
RESP_STATE_READ,
RESP_STATE_WRITE,
RESP_STATE_CPL
} resp_state_t;
logic [1:0] resp_state_reg = RESP_STATE_IDLE, resp_state_next;
resp_state_t resp_state_reg = RESP_STATE_IDLE, resp_state_next;
logic [AXIL_ADDR_W-1:0] req_addr_reg = '0, req_addr_next;
logic [TLP_DATA_W-1:0] req_data_reg = '0, req_data_next;

32
src/pcie/rtl/taxi_pcie_axil_master_minimal.sv
View File

@@ -87,32 +87,36 @@ if (AXIL_DATA_W != 32)
if (AXIL_STRB_W * 8 != AXIL_DATA_W)
$fatal(0, "Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
localparam [2:0]
typedef enum logic [2:0] {
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
TLP_FMT_PREFIX = 3'b100
} tlp_fmt_t;
localparam [2:0]
typedef enum logic [2:0] {
CPL_STATUS_SC = 3'b000, // successful completion
CPL_STATUS_UR = 3'b001, // unsupported request
CPL_STATUS_CRS = 3'b010, // configuration request retry status
CPL_STATUS_CA = 3'b100; // completer abort
CPL_STATUS_CA = 3'b100 // completer abort
} cpl_status_t;
localparam [0:0]
REQ_STATE_IDLE = 1'd0,
REQ_STATE_WAIT_END = 1'd1;
typedef enum logic [0:0] {
REQ_STATE_IDLE,
REQ_STATE_WAIT_END
} req_state_t;
logic [0:0] req_state_reg = REQ_STATE_IDLE, req_state_next;
req_state_t req_state_reg = REQ_STATE_IDLE, req_state_next;
localparam [1:0]
RESP_STATE_IDLE = 2'd0,
RESP_STATE_READ = 2'd1,
RESP_STATE_WRITE = 2'd2,
RESP_STATE_CPL = 2'd3;
typedef enum logic [1:0] {
RESP_STATE_IDLE,
RESP_STATE_READ,
RESP_STATE_WRITE,
RESP_STATE_CPL
} resp_state_t;
logic [1:0] resp_state_reg = RESP_STATE_IDLE, resp_state_next;
resp_state_t resp_state_reg = RESP_STATE_IDLE, resp_state_next;
logic [2:0] rx_req_tlp_hdr_fmt;
logic [4:0] rx_req_tlp_hdr_type;

18
src/pcie/rtl/taxi_pcie_msix_apb.sv
View File

@@ -87,20 +87,22 @@ if (APB_ADDR_W < IRQ_INDEX_W+5)
if (IRQ_INDEX_W > 11)
$fatal(0, "Error: IRQ index width must be 11 or less (instance %m)");
localparam [2:0]
typedef enum logic [2:0] {
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
TLP_FMT_PREFIX = 3'b100
} tlp_fmt_t;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_READ_TBL_1 = 2'd1,
STATE_READ_TBL_2 = 2'd2,
STATE_SEND_TLP = 2'd3;
typedef enum logic [1:0] {
STATE_IDLE,
STATE_READ_TBL_1,
STATE_READ_TBL_2,
STATE_SEND_TLP
} state_t;
logic [1:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
logic [IRQ_INDEX_W-1:0] irq_index_reg = '0, irq_index_next;

18
src/pcie/rtl/taxi_pcie_msix_axil.sv
View File

@@ -88,20 +88,22 @@ if (AXIL_ADDR_W < IRQ_INDEX_W+5)
if (IRQ_INDEX_W > 11)
$fatal(0, "Error: IRQ index width must be 11 or less (instance %m)");
localparam [2:0]
typedef enum logic [2:0] {
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
TLP_FMT_PREFIX = 3'b100
} tlp_fmt_t;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_READ_TBL_1 = 2'd1,
STATE_READ_TBL_2 = 2'd2,
STATE_SEND_TLP = 2'd3;
typedef enum logic [1:0] {
STATE_IDLE,
STATE_READ_TBL_1,
STATE_READ_TBL_2,
STATE_SEND_TLP
} state_t;
logic [1:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
logic [IRQ_INDEX_W-1:0] irq_index_reg = '0, irq_index_next;

31
src/pcie/rtl/taxi_pcie_us_axil_master.sv
View File

@@ -81,7 +81,7 @@ if (AXIL_DATA_W != 32)
if (AXIL_STRB_W * 8 != AXIL_DATA_W)
$fatal(0, "Error: AXI interface requires byte (8-bit) granularity (instance %m)");
localparam [3:0]
typedef enum logic [3:0] {
REQ_MEM_READ = 4'b0000,
REQ_MEM_WRITE = 4'b0001,
REQ_IO_READ = 4'b0010,
@@ -96,23 +96,26 @@ localparam [3:0]
REQ_CFG_WRITE_1 = 4'b1011,
REQ_MSG = 4'b1100,
REQ_MSG_VENDOR = 4'b1101,
REQ_MSG_ATS = 4'b1110;
REQ_MSG_ATS = 4'b1110
} req_type_t;
localparam [2:0]
typedef enum logic [2:0] {
CPL_STATUS_SC = 3'b000, // successful completion
CPL_STATUS_UR = 3'b001, // unsupported request
CPL_STATUS_CRS = 3'b010, // configuration request retry status
CPL_STATUS_CA = 3'b100; // completer abort
CPL_STATUS_CA = 3'b100 // completer abort
} cpl_status_t;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_HEADER = 3'd1,
STATE_READ = 3'd2,
STATE_WRITE_1 = 3'd3,
STATE_WRITE_2 = 3'd4,
STATE_WAIT_END = 3'd5,
STATE_CPL_1 = 3'd6,
STATE_CPL_2 = 3'd7;
typedef enum logic [2:0] {
STATE_IDLE,
STATE_HEADER,
STATE_READ,
STATE_WRITE_1,
STATE_WRITE_2,
STATE_WAIT_END,
STATE_CPL_1,
STATE_CPL_2
} state_t;
wire [63:0] req_tlp_hdr_addr;
wire [10:0] req_tlp_hdr_length;
@@ -161,7 +164,7 @@ logic [95:0] cpl_tlp_hdr;
logic [32:0] cpl_tuser_1;
logic [80:0] cpl_tuser_2;
logic [2:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
logic [10:0] dword_count_reg = '0, dword_count_next;
logic [3:0] type_reg = '0, type_next;