From 6e90f4f0a0b71462e76cd9988af29c628b8fe969 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 25 Feb 2025 15:39:00 -0800 Subject: [PATCH] syn: Add timing constraints for signal synchronizer Signed-off-by: Alex Forencich --- syn/vivado/taxi_sync_signal.tcl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 syn/vivado/taxi_sync_signal.tcl diff --git a/syn/vivado/taxi_sync_signal.tcl b/syn/vivado/taxi_sync_signal.tcl new file mode 100644 index 0000000..176852a --- /dev/null +++ b/syn/vivado/taxi_sync_signal.tcl @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# signal synchronizer timing constraints + +foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_signal || REF_NAME == taxi_sync_signal)}] { + puts "Inserting timing constraints for taxi_sync_signal instance $inst" + + set_property ASYNC_REG TRUE [get_cells -hier "sync_reg_reg[*][*]" -filter "PARENT == $inst"] + set_false_path -to [get_cells -hier "sync_reg_reg[0][*]" -filter "PARENT == $inst"] +}