diff --git a/src/eth/example/KCU105/fpga/fpga_10g/config.tcl b/src/eth/example/KCU105/fpga/fpga_10g/config.tcl
index 51c34b1..4359e24 100644
--- a/src/eth/example/KCU105/fpga/fpga_10g/config.tcl
+++ b/src/eth/example/KCU105/fpga/fpga_10g/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "32"
diff --git a/src/eth/example/KCU105/fpga/fpga_1g/config.tcl b/src/eth/example/KCU105/fpga/fpga_1g/config.tcl
index a95092e..ab45ff6 100644
--- a/src/eth/example/KCU105/fpga/fpga_1g/config.tcl
+++ b/src/eth/example/KCU105/fpga/fpga_1g/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "0"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "16"
diff --git a/src/eth/example/KCU105/fpga/rtl/fpga.sv b/src/eth/example/KCU105/fpga/rtl/fpga.sv
index d54d97a..09fd8c0 100644
--- a/src/eth/example/KCU105/fpga/rtl/fpga.sv
+++ b/src/eth/example/KCU105/fpga/rtl/fpga.sv
@@ -23,12 +23,10 @@ module fpga #
     parameter string VENDOR = "XILINX",
     // device family
     parameter string FAMILY = "kintexu",
-    // SFP rate selection (0 for 1G, 1 for 10G)
-    parameter logic SFP_RATE = 1'b1,
-    // 10G MAC configuration
+    // MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
     parameter logic COMBINED_MAC_PCS = 1'b1,
-    parameter MAC_DATA_W = SFP_RATE ? 32 : 16
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -383,7 +381,6 @@ fpga_core #(
     .SIM(SIM),
     .VENDOR(VENDOR),
     .FAMILY(FAMILY),
-    .SFP_RATE(SFP_RATE),
     .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
     .MAC_DATA_W(MAC_DATA_W)
diff --git a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv
index 95f318d..b60142b 100644
--- a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv
+++ b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv
@@ -23,12 +23,10 @@ module fpga_core #
     parameter string VENDOR = "XILINX",
     // device family
     parameter string FAMILY = "kintexu",
-    // SFP rate selection (0 for 1G, 1 for 10G)
-    parameter logic SFP_RATE = 1'b1,
-    // 10G MAC configuration
+    // MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
     parameter logic COMBINED_MAC_PCS = 1'b1,
-    parameter MAC_DATA_W = SFP_RATE ? 32 : 16
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -398,7 +396,7 @@ xfcp_mod_apb_inst (
     .m_apb(gt_apb_ctrl)
 );
 
-if (SFP_RATE == 0) begin : sfp_mac
+if (MAC_DATA_W == 16) begin : sfp_mac
 
     taxi_eth_mac_1g_basex_us #(
         .SIM(SIM),
diff --git a/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile b/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile
index 4ec8223..9f110d5 100644
--- a/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile
+++ b/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile
@@ -45,7 +45,6 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 export PARAM_SIM := "1'b1"
 export PARAM_VENDOR := "\"XILINX\""
 export PARAM_FAMILY := "\"kintexu\""
-export PARAM_SFP_RATE := "1'b1"
 export PARAM_CFG_LOW_LATENCY := "1'b1"
 export PARAM_COMBINED_MAC_PCS := "1'b1"
 export PARAM_MAC_DATA_W := "32"
diff --git a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
index ce18903..3593c6a 100644
--- a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
@@ -60,7 +60,7 @@ class TB:
         for ch in dut.sfp_mac.sfp_mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
-            if dut.SFP_RATE.value == 0:
+            if dut.MAC_DATA_W.value == 16:
                 if ch.ch_inst.CFG_LOW_LATENCY.value:
                     clk = 16
                     gbx_cfg = None
@@ -245,8 +245,8 @@ def process_f_files(files):
     return list(lst.values())
 
 
-@pytest.mark.parametrize(("sfp_rate", "mac_data_w"), [(0, 16), (1, 32), (1, 64)])
-def test_fpga_core(request, sfp_rate, mac_data_w):
+@pytest.mark.parametrize("mac_data_w", [16, 32, 64])
+def test_fpga_core(request, mac_data_w):
     dut = "fpga_core"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -273,7 +273,6 @@ def test_fpga_core(request, sfp_rate, mac_data_w):
     parameters['SIM'] = "1'b1"
     parameters['VENDOR'] = "\"XILINX\""
     parameters['FAMILY'] = "\"kintexu\""
-    parameters['SFP_RATE'] = f"1'b{sfp_rate}"
     parameters['CFG_LOW_LATENCY'] = "1'b1"
     parameters['COMBINED_MAC_PCS'] = "1'b1"
     parameters['MAC_DATA_W'] = mac_data_w
diff --git a/src/eth/example/ZCU102/fpga/fpga_10g/config.tcl b/src/eth/example/ZCU102/fpga/fpga_10g/config.tcl
index 51c34b1..4359e24 100644
--- a/src/eth/example/ZCU102/fpga/fpga_10g/config.tcl
+++ b/src/eth/example/ZCU102/fpga/fpga_10g/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "32"
diff --git a/src/eth/example/ZCU102/fpga/fpga_1g/config.tcl b/src/eth/example/ZCU102/fpga/fpga_1g/config.tcl
index a95092e..ab45ff6 100644
--- a/src/eth/example/ZCU102/fpga/fpga_1g/config.tcl
+++ b/src/eth/example/ZCU102/fpga/fpga_1g/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "0"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "16"
diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga.sv b/src/eth/example/ZCU102/fpga/rtl/fpga.sv
index 4289b5d..e9d85ba 100644
--- a/src/eth/example/ZCU102/fpga/rtl/fpga.sv
+++ b/src/eth/example/ZCU102/fpga/rtl/fpga.sv
@@ -23,12 +23,10 @@ module fpga #
     parameter string VENDOR = "XILINX",
     // device family
     parameter string FAMILY = "zynquplus",
-    // SFP rate selection (0 for 1G, 1 for 10G)
-    parameter logic SFP_RATE = 1'b1,
-    // 10G MAC configuration
+    // MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
     parameter logic COMBINED_MAC_PCS = 1'b1,
-    parameter MAC_DATA_W = SFP_RATE ? 32 : 16
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -248,7 +246,6 @@ fpga_core #(
     .SIM(SIM),
     .VENDOR(VENDOR),
     .FAMILY(FAMILY),
-    .SFP_RATE(SFP_RATE),
     .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
     .MAC_DATA_W(MAC_DATA_W)
diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv
index 2a9bc33..ae00807 100644
--- a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv
+++ b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv
@@ -25,10 +25,10 @@ module fpga_core #
     parameter string FAMILY = "zynquplus",
     // SFP rate selection (0 for 1G, 1 for 10G)
     parameter logic SFP_RATE = 1'b1,
-    // 10G MAC configuration
+    // MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
     parameter logic COMBINED_MAC_PCS = 1'b1,
-    parameter MAC_DATA_W = SFP_RATE ? 32 : 16
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -262,7 +262,7 @@ xfcp_mod_apb_inst (
     .m_apb(gt_apb_ctrl)
 );
 
-if (SFP_RATE == 0) begin : sfp_mac
+if (MAC_DATA_W == 16) begin : sfp_mac
 
     taxi_eth_mac_1g_basex_us #(
         .SIM(SIM),
@@ -808,30 +808,30 @@ for (genvar n = 0; n < $size(axis_sfp_tx); n = n + 1) begin : sfp_ch
     )
     ch_fifo (
         /*
-            * AXI4-Stream input (sink)
-            */
+         * AXI4-Stream input (sink)
+         */
         .s_clk(sfp_rx_clk[n]),
         .s_rst(sfp_rx_rst[n]),
         .s_axis(axis_sfp_rx[n]),
 
         /*
-            * AXI4-Stream output (source)
-            */
+         * AXI4-Stream output (source)
+         */
         .m_clk(sfp_tx_clk[n]),
         .m_rst(sfp_tx_rst[n]),
         .m_axis(axis_sfp_tx[n]),
 
         /*
-            * Pause
-            */
+         * Pause
+         */
         .s_pause_req(1'b0),
         .s_pause_ack(),
         .m_pause_req(1'b0),
         .m_pause_ack(),
 
         /*
-            * Status
-            */
+         * Status
+         */
         .s_status_depth(),
         .s_status_depth_commit(),
         .s_status_overflow(),
diff --git a/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile b/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile
index 34d9959..1fd5ac4 100644
--- a/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile
+++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile
@@ -44,7 +44,6 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 export PARAM_SIM := "1'b1"
 export PARAM_VENDOR := "\"XILINX\""
 export PARAM_FAMILY := "\"zynquplus\""
-export PARAM_SFP_RATE := "1'b1"
 export PARAM_CFG_LOW_LATENCY := "1'b1"
 export PARAM_COMBINED_MAC_PCS := "1'b1"
 export PARAM_MAC_DATA_W := "32"
diff --git a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
index 10c8361..40602d1 100644
--- a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
@@ -20,7 +20,6 @@ import cocotb
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
-from cocotbext.eth import GmiiSource, GmiiSink
 from cocotbext.eth import XgmiiFrame
 from cocotbext.uart import UartSource, UartSink
 
@@ -54,7 +53,7 @@ class TB:
         for ch in dut.sfp_mac.sfp_mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
-            if dut.SFP_RATE.value == 0:
+            if dut.MAC_DATA_W.value == 16:
                 if ch.ch_inst.CFG_LOW_LATENCY.value:
                     clk = 16
                     gbx_cfg = None
@@ -238,8 +237,8 @@ def process_f_files(files):
     return list(lst.values())
 
 
-@pytest.mark.parametrize(("sfp_rate", "mac_data_w"), [(0, 16), (1, 32), (1, 64)])
-def test_fpga_core(request, sfp_rate, mac_data_w):
+@pytest.mark.parametrize("mac_data_w", [16, 32, 64])
+def test_fpga_core(request, mac_data_w):
     dut = "fpga_core"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -265,7 +264,6 @@ def test_fpga_core(request, sfp_rate, mac_data_w):
     parameters['SIM'] = "1'b1"
     parameters['VENDOR'] = "\"XILINX\""
     parameters['FAMILY'] = "\"zynquplus\""
-    parameters['SFP_RATE'] = f"1'b{sfp_rate}"
     parameters['CFG_LOW_LATENCY'] = "1'b1"
     parameters['COMBINED_MAC_PCS'] = "1'b1"
     parameters['MAC_DATA_W'] = mac_data_w
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g/config.tcl
index 51c34b1..4359e24 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "32"
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g_64/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g_64/config.tcl
index b2423bd..cc1eeae 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g_64/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g_64/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "64"
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g_64_async/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g_64_async/config.tcl
index b5a57c8..b3147fe 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g_64_async/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g_64_async/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "0"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "64"
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g_64_split/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g_64_split/config.tcl
index ca073a8..230403b 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g_64_split/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g_64_split/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "0"
 dict set params MAC_DATA_W "64"
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g_64_split_async/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g_64_split_async/config.tcl
index bdce4b3..ffe6795 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g_64_split_async/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g_64_split_async/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "0"
 dict set params COMBINED_MAC_PCS "0"
 dict set params MAC_DATA_W "64"
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g_async/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g_async/config.tcl
index 6043470..c85fdf7 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g_async/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g_async/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "0"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "32"
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g_split/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g_split/config.tcl
index 6eb6613..cd91382 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g_split/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g_split/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "0"
 dict set params MAC_DATA_W "32"
diff --git a/src/eth/example/ZCU106/fpga/fpga_10g_split_async/config.tcl b/src/eth/example/ZCU106/fpga/fpga_10g_split_async/config.tcl
index 06c3d2a..adca85a 100644
--- a/src/eth/example/ZCU106/fpga/fpga_10g_split_async/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_10g_split_async/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "1"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "0"
 dict set params COMBINED_MAC_PCS "0"
 dict set params MAC_DATA_W "32"
diff --git a/src/eth/example/ZCU106/fpga/fpga_1g/config.tcl b/src/eth/example/ZCU106/fpga/fpga_1g/config.tcl
index a95092e..ab45ff6 100644
--- a/src/eth/example/ZCU106/fpga/fpga_1g/config.tcl
+++ b/src/eth/example/ZCU106/fpga/fpga_1g/config.tcl
@@ -8,11 +8,7 @@
 
 set params [dict create]
 
-# SFP+ rate
-# 0 for 1G, 1 for 10G
-dict set params SFP_RATE "0"
-
-# 10G MAC configuration
+# MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
 dict set params MAC_DATA_W "16"
diff --git a/src/eth/example/ZCU106/fpga/rtl/fpga.sv b/src/eth/example/ZCU106/fpga/rtl/fpga.sv
index 113b6db..2634761 100644
--- a/src/eth/example/ZCU106/fpga/rtl/fpga.sv
+++ b/src/eth/example/ZCU106/fpga/rtl/fpga.sv
@@ -23,12 +23,10 @@ module fpga #
     parameter string VENDOR = "XILINX",
     // device family
     parameter string FAMILY = "zynquplus",
-    // SFP rate selection (0 for 1G, 1 for 10G)
-    parameter logic SFP_RATE = 1'b1,
-    // 10G MAC configuration
+    // MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
     parameter logic COMBINED_MAC_PCS = 1'b1,
-    parameter MAC_DATA_W = SFP_RATE ? 32 : 16
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -241,7 +239,6 @@ fpga_core #(
     .SIM(SIM),
     .VENDOR(VENDOR),
     .FAMILY(FAMILY),
-    .SFP_RATE(SFP_RATE),
     .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
     .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
     .MAC_DATA_W(MAC_DATA_W)
diff --git a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv
index c511c0b..2f68c25 100644
--- a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv
+++ b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv
@@ -23,12 +23,10 @@ module fpga_core #
     parameter string VENDOR = "XILINX",
     // device family
     parameter string FAMILY = "zynquplus",
-    // SFP rate selection (0 for 1G, 1 for 10G)
-    parameter logic SFP_RATE = 1'b1,
-    // 10G MAC configuration
+    // MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
     parameter logic COMBINED_MAC_PCS = 1'b1,
-    parameter MAC_DATA_W = SFP_RATE ? 32 : 16
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -262,7 +260,7 @@ xfcp_mod_apb_inst (
     .m_apb(gt_apb_ctrl)
 );
 
-if (SFP_RATE == 0) begin : sfp_mac
+if (MAC_DATA_W == 16) begin : sfp_mac
 
     taxi_eth_mac_1g_basex_us #(
         .SIM(SIM),
@@ -810,30 +808,30 @@ for (genvar n = 0; n < $size(axis_sfp_tx); n = n + 1) begin : sfp_ch
     )
     ch_fifo (
         /*
-            * AXI4-Stream input (sink)
-            */
+         * AXI4-Stream input (sink)
+         */
         .s_clk(sfp_rx_clk[n]),
         .s_rst(sfp_rx_rst[n]),
         .s_axis(axis_sfp_rx[n]),
 
         /*
-            * AXI4-Stream output (source)
-            */
+         * AXI4-Stream output (source)
+         */
         .m_clk(sfp_tx_clk[n]),
         .m_rst(sfp_tx_rst[n]),
         .m_axis(axis_sfp_tx[n]),
 
         /*
-            * Pause
-            */
+         * Pause
+         */
         .s_pause_req(1'b0),
         .s_pause_ack(),
         .m_pause_req(1'b0),
         .m_pause_ack(),
 
         /*
-            * Status
-            */
+         * Status
+         */
         .s_status_depth(),
         .s_status_depth_commit(),
         .s_status_overflow(),
diff --git a/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile b/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile
index 34d9959..1fd5ac4 100644
--- a/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile
+++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile
@@ -44,7 +44,6 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 export PARAM_SIM := "1'b1"
 export PARAM_VENDOR := "\"XILINX\""
 export PARAM_FAMILY := "\"zynquplus\""
-export PARAM_SFP_RATE := "1'b1"
 export PARAM_CFG_LOW_LATENCY := "1'b1"
 export PARAM_COMBINED_MAC_PCS := "1'b1"
 export PARAM_MAC_DATA_W := "32"
diff --git a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
index 10c8361..40602d1 100644
--- a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
@@ -20,7 +20,6 @@ import cocotb
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
-from cocotbext.eth import GmiiSource, GmiiSink
 from cocotbext.eth import XgmiiFrame
 from cocotbext.uart import UartSource, UartSink
 
@@ -54,7 +53,7 @@ class TB:
         for ch in dut.sfp_mac.sfp_mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
-            if dut.SFP_RATE.value == 0:
+            if dut.MAC_DATA_W.value == 16:
                 if ch.ch_inst.CFG_LOW_LATENCY.value:
                     clk = 16
                     gbx_cfg = None
@@ -238,8 +237,8 @@ def process_f_files(files):
     return list(lst.values())
 
 
-@pytest.mark.parametrize(("sfp_rate", "mac_data_w"), [(0, 16), (1, 32), (1, 64)])
-def test_fpga_core(request, sfp_rate, mac_data_w):
+@pytest.mark.parametrize("mac_data_w", [16, 32, 64])
+def test_fpga_core(request, mac_data_w):
     dut = "fpga_core"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -265,7 +264,6 @@ def test_fpga_core(request, sfp_rate, mac_data_w):
     parameters['SIM'] = "1'b1"
     parameters['VENDOR'] = "\"XILINX\""
     parameters['FAMILY'] = "\"zynquplus\""
-    parameters['SFP_RATE'] = f"1'b{sfp_rate}"
     parameters['CFG_LOW_LATENCY'] = "1'b1"
     parameters['COMBINED_MAC_PCS'] = "1'b1"
     parameters['MAC_DATA_W'] = mac_data_w