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eth: Tie off transceiver control signals during simulation

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-24 16:28:59 -08:00
parent 34266fe25d
commit 7047cb5c4f
8 changed files with 6 additions and 14 deletions
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2
example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
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@@ -89,8 +89,6 @@ taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[7:0]();
if (SIM) begin
assign qsfp_gtpowergood = '1;
assign qsfp_0_mgt_refclk = qsfp_0_mgt_refclk_p;
assign qsfp_0_mgt_refclk_int = qsfp_0_mgt_refclk_p;
assign qsfp_0_mgt_refclk_bufg = qsfp_0_mgt_refclk_int;

2
example/KCU105/fpga/rtl/fpga_core.sv
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@@ -381,8 +381,6 @@ end else begin : sfp_mac
if (SIM) begin
assign sfp_gtpowergood = 1'b1;
assign sfp_mgt_refclk_0 = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_int = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_bufg = sfp_mgt_refclk_0_int;

2
example/KR260/fpga/rtl/fpga_core.sv
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@@ -326,8 +326,6 @@ end else begin : sfp_mac
if (SIM) begin
assign sfp_gtpowergood = 1'b1;
assign sfp_mgt_refclk = sfp_mgt_refclk_p;
assign sfp_mgt_refclk_int = sfp_mgt_refclk_p;
assign sfp_mgt_refclk_bufg = sfp_mgt_refclk_int;

2
example/VCU108/fpga/rtl/fpga_core.sv
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@@ -225,8 +225,6 @@ taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[3:0]();
if (SIM) begin
assign qsfp_gtpowergood = 1'b1;
assign qsfp_mgt_refclk_0 = qsfp_mgt_refclk_0_p;
assign qsfp_mgt_refclk_0_int = qsfp_mgt_refclk_0_p;
assign qsfp_mgt_refclk_0_bufg = qsfp_mgt_refclk_0_int;

2
example/ZCU102/fpga/rtl/fpga_core.sv
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@@ -452,8 +452,6 @@ end else begin : sfp_mac
if (SIM) begin
assign sfp_gtpowergood = 1'b1;
assign sfp_mgt_refclk_0 = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_int = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_bufg = sfp_mgt_refclk_0_int;

2
example/ZCU106/fpga/rtl/fpga_core.sv
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@@ -294,8 +294,6 @@ end else begin : sfp_mac
if (SIM) begin
assign sfp_gtpowergood = 1'b1;
assign sfp_mgt_refclk_0 = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_int = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_bufg = sfp_mgt_refclk_0_int;

2
example/ZCU111/fpga/rtl/fpga_core.sv
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@@ -130,8 +130,6 @@ taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[3:0]();
if (SIM) begin
assign sfp_gtpowergood = 1'b1;
assign sfp_mgt_refclk_0 = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_int = sfp_mgt_refclk_0_p;
assign sfp_mgt_refclk_0_bufg = sfp_mgt_refclk_0_int;

6
rtl/eth/us/taxi_eth_mac_25g_us_ch.sv
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@@ -227,6 +227,12 @@ wire [1:0] gt_rxdatavalid;
if (SIM) begin : xcvr
// simulation (no GT core)
assign xcvr_gtpowergood_out = 1'b1;
assign xcvr_qpll0lock_out = 1'b1;
assign xcvr_qpll0clk_out = 1'b0;
assign xcvr_qpll0refclk_out = 1'b0;
assign gt_reset_tx_done = !xcvr_ctrl_rst;
assign gt_reset_rx_done = !xcvr_ctrl_rst;