diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
index ac890b3..a263fa3 100644
--- a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -38,7 +37,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py
index d7c7582..dbdb401 100644
--- a/src/eth/example/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -38,7 +37,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
index c078a8c..35586c5 100644
--- a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
@@ -16,7 +16,6 @@ import sys
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Timer, Combine
 
@@ -38,7 +37,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
index 3095370..d775cb5 100644
--- a/src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
@@ -15,7 +15,6 @@ import os
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -27,7 +26,7 @@ class TB:
     def __init__(self, dut, speed=100e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
index 704d841..5b91c84 100644
--- a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -39,7 +38,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py
index dbf2183..ed5b84d 100644
--- a/src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py
@@ -15,7 +15,6 @@ import os
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Timer, Combine
 
@@ -27,7 +26,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         self.baset_phy = RgmiiPhy(dut.phy_rgmii_txd, dut.phy_rgmii_tx_ctl, dut.phy_rgmii_tx_clk,
diff --git a/src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.py
index ac6e67a..069dd2d 100644
--- a/src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -39,7 +38,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py
index 8225486..e28abd4 100644
--- a/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py
@@ -16,7 +16,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Timer, Combine
 
@@ -28,7 +27,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.phy_sgmii_clk, 8, units="ns").start())
diff --git a/src/eth/example/KC705/fpga_10g/tb/fpga_core/test_fpga_core.py b/src/eth/example/KC705/fpga_10g/tb/fpga_core/test_fpga_core.py
index e8addcf..a51b017 100644
--- a/src/eth/example/KC705/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/KC705/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Timer, Combine
 
@@ -40,7 +39,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         if hasattr(dut, "baset_mac_gmii"):
diff --git a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
index 0b9ef79..5593c51 100644
--- a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -40,7 +39,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
diff --git a/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
index 2343b1b..6c8b3c0 100644
--- a/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Timer, Combine
 
@@ -39,7 +38,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         self.baset_phy2 = RgmiiPhy(dut.phy2_rgmii_txd, dut.phy2_rgmii_tx_ctl, dut.phy2_rgmii_tx_clk,
diff --git a/src/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
index b9637ee..fcc3b8f 100644
--- a/src/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -39,7 +38,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
index 138e374..02e06a0 100644
--- a/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -38,7 +37,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py
index 11dd018..9a7dec8 100644
--- a/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -38,7 +37,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/VC709/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VC709/fpga/tb/fpga_core/test_fpga_core.py
index aa483d2..0f1afe1 100644
--- a/src/eth/example/VC709/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/VC709/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -39,7 +38,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
index 277ca89..7d3f48b 100644
--- a/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -40,7 +39,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
diff --git a/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
index bcb6f54..4a017a0 100644
--- a/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -40,7 +39,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
index 0648c30..8b06a6b 100644
--- a/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -39,7 +38,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
index f6011be..aea0b23 100644
--- a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -40,7 +39,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
index 3d45696..bc6006b 100644
--- a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -40,7 +39,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
index 2bbcc31..acabcc0 100644
--- a/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -39,7 +38,7 @@ class TB:
     def __init__(self, dut, speed=1000e6):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
diff --git a/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
index ecb77ef..664fe5b 100644
--- a/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
@@ -17,7 +17,6 @@ import pytest
 import cocotb_test.simulator
 
 import cocotb
-from cocotb.log import SimLog
 from cocotb.clock import Clock
 from cocotb.triggers import RisingEdge, Combine
 
@@ -38,7 +37,7 @@ class TB:
     def __init__(self, dut):
         self.dut = dut
 
-        self.log = SimLog("cocotb.tb")
+        self.log = logging.getLogger("cocotb.tb")
         self.log.setLevel(logging.DEBUG)
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())