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cndm_proto: Initial commit of corundum-proto
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
465
src/cndm_proto/rtl/cndm_proto_pcie_us.sv
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465
src/cndm_proto/rtl/cndm_proto_pcie_us.sv
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@@ -0,0 +1,465 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Corundum-proto core logic for UltraScale PCIe
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*/
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module cndm_proto_pcie_us #(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "kintexuplus",
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parameter PORTS = 2,
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parameter RQ_SEQ_NUM_W = 6,
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parameter BAR0_APERTURE = 24
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)
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(
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/*
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* PCIe
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*/
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input wire logic pcie_clk,
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input wire logic pcie_rst,
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taxi_axis_if.snk s_axis_pcie_cq,
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taxi_axis_if.src m_axis_pcie_cc,
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taxi_axis_if.src m_axis_pcie_rq,
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taxi_axis_if.snk s_axis_pcie_rc,
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input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0,
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input wire pcie_rq_seq_num_vld0,
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input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1,
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input wire pcie_rq_seq_num_vld1,
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input wire [2:0] cfg_max_payload,
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input wire [2:0] cfg_max_read_req,
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input wire [3:0] cfg_rcb_status,
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output wire [9:0] cfg_mgmt_addr,
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output wire [7:0] cfg_mgmt_function_number,
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output wire cfg_mgmt_write,
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output wire [31:0] cfg_mgmt_write_data,
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output wire [3:0] cfg_mgmt_byte_enable,
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output wire cfg_mgmt_read,
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input wire [31:0] cfg_mgmt_read_data,
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input wire cfg_mgmt_read_write_done,
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input wire [7:0] cfg_fc_ph,
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input wire [11:0] cfg_fc_pd,
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input wire [7:0] cfg_fc_nph,
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input wire [11:0] cfg_fc_npd,
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input wire [7:0] cfg_fc_cplh,
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input wire [11:0] cfg_fc_cpld,
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output wire [2:0] cfg_fc_sel,
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input wire [3:0] cfg_interrupt_msi_enable,
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input wire [11:0] cfg_interrupt_msi_mmenable,
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input wire cfg_interrupt_msi_mask_update,
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input wire [31:0] cfg_interrupt_msi_data,
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output wire [1:0] cfg_interrupt_msi_select,
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output wire [31:0] cfg_interrupt_msi_int,
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output wire [31:0] cfg_interrupt_msi_pending_status,
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output wire cfg_interrupt_msi_pending_status_data_enable,
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output wire [1:0] cfg_interrupt_msi_pending_status_function_num,
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input wire cfg_interrupt_msi_sent,
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input wire cfg_interrupt_msi_fail,
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output wire [2:0] cfg_interrupt_msi_attr,
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output wire cfg_interrupt_msi_tph_present,
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output wire [1:0] cfg_interrupt_msi_tph_type,
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output wire [7:0] cfg_interrupt_msi_tph_st_tag,
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output wire [7:0] cfg_interrupt_msi_function_number,
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/*
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* Ethernet
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*/
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input wire logic mac_tx_clk[PORTS],
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input wire logic mac_tx_rst[PORTS],
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taxi_axis_if.src mac_axis_tx[PORTS],
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taxi_axis_if.snk mac_axis_tx_cpl[PORTS],
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input wire logic mac_rx_clk[PORTS],
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input wire logic mac_rx_rst[PORTS],
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taxi_axis_if.snk mac_axis_rx[PORTS]
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);
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localparam CL_PORTS = $clog2(PORTS);
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localparam AXIL_DATA_W = 32;
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localparam AXIL_ADDR_W = BAR0_APERTURE;
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taxi_axil_if #(
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.DATA_W(AXIL_DATA_W),
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.ADDR_W(AXIL_ADDR_W),
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.AWUSER_EN(1'b0),
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.WUSER_EN(1'b0),
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.BUSER_EN(1'b0),
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.ARUSER_EN(1'b0),
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.RUSER_EN(1'b0)
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) axil_ctrl_bar();
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taxi_pcie_us_axil_master
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pcie_axil_master_inst (
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.clk(pcie_clk),
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.rst(pcie_rst),
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/*
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* UltraScale PCIe interface
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*/
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.s_axis_cq(s_axis_pcie_cq),
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.m_axis_cc(m_axis_pcie_cc),
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/*
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* AXI Lite Master output
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*/
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.m_axil_wr(axil_ctrl_bar),
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.m_axil_rd(axil_ctrl_bar),
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/*
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* Configuration
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*/
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.completer_id('0),
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.completer_id_en(1'b0),
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/*
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* Status
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*/
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.stat_err_cor(),
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.stat_err_uncor()
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);
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localparam AXIS_PCIE_DATA_W = m_axis_pcie_rq.DATA_W;
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localparam PCIE_ADDR_W = 64;
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// TODO
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localparam logic RQ_SEQ_NUM_EN = 1'b1;
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localparam RAM_SEL_W = 2+CL_PORTS;
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localparam RAM_ADDR_W = 16;
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localparam RAM_SEGS = 2;//AXIS_PCIE_DATA_W > 256 ? AXIS_PCIE_DATA_W / 128 : 2;
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localparam PCIE_TAG_CNT = 64;//AXIS_PCIE_RQ_USER_W == 60 ? 64 : 256,
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localparam logic IMM_EN = 1'b0;
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localparam IMM_W = 32;
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localparam LEN_W = 20;
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localparam TAG_W = 8;
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localparam RD_OP_TBL_SIZE = PCIE_TAG_CNT;
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localparam RD_TX_LIMIT = 2**(RQ_SEQ_NUM_W-1);
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localparam logic RD_TX_FC_EN = 1'b1;
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localparam RD_CPLH_FC_LIMIT = 512;
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localparam RD_CPLD_FC_LIMIT = RD_CPLH_FC_LIMIT*4;
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localparam WR_OP_TBL_SIZE = 2**(RQ_SEQ_NUM_W-1);
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localparam WR_TX_LIMIT = 2**(RQ_SEQ_NUM_W-1);
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localparam logic WR_TX_FC_EN = 1'b1;
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localparam RAM_DATA_W = AXIS_PCIE_DATA_W*2;
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localparam RAM_SEG_DATA_W = RAM_DATA_W / RAM_SEGS;
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localparam RAM_SEG_BE_W = RAM_SEG_DATA_W / 8;
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localparam RAM_SEG_ADDR_W = RAM_ADDR_W - $clog2(RAM_SEGS*RAM_SEG_BE_W);
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logic [RQ_SEQ_NUM_W-1:0] s_axis_rq_seq_num_0;
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logic s_axis_rq_seq_num_valid_0;
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logic [RQ_SEQ_NUM_W-1:0] s_axis_rq_seq_num_1;
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logic s_axis_rq_seq_num_valid_1;
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logic [7:0] pcie_tx_fc_nph_av;
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logic [7:0] pcie_tx_fc_ph_av;
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logic [11:0] pcie_tx_fc_pd_av;
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assign cfg_fc_sel = 3'b100;
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taxi_dma_desc_if #(
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.SRC_ADDR_W(PCIE_ADDR_W),
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.SRC_SEL_EN(1'b0),
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.SRC_ASID_EN(1'b0),
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.DST_ADDR_W(RAM_ADDR_W),
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.DST_SEL_EN(1'b1),
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.DST_SEL_W(RAM_SEL_W),
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.DST_ASID_EN(1'b0),
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.IMM_EN(1'b0),
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.LEN_W(LEN_W),
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.TAG_W(TAG_W),
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.ID_EN(1'b0),
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.DEST_EN(1'b0),
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.USER_EN(1'b0)
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) dma_rd_desc();
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taxi_dma_desc_if #(
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.SRC_ADDR_W(RAM_ADDR_W),
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.SRC_SEL_EN(1'b1),
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.SRC_SEL_W(RAM_SEL_W),
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.SRC_ASID_EN(1'b0),
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.DST_ADDR_W(PCIE_ADDR_W),
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.DST_SEL_EN(1'b0),
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.DST_ASID_EN(1'b0),
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.IMM_EN(IMM_EN),
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.IMM_W(IMM_W),
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.LEN_W(LEN_W),
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.TAG_W(TAG_W),
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.ID_EN(1'b0),
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.DEST_EN(1'b0),
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.USER_EN(1'b0)
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) dma_wr_desc();
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taxi_dma_ram_if #(
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.SEGS(RAM_SEGS),
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.SEG_ADDR_W(RAM_SEG_ADDR_W),
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.SEG_DATA_W(RAM_SEG_DATA_W),
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.SEG_BE_W(RAM_SEG_BE_W),
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.SEL_W(RAM_SEL_W)
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) dma_ram();
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logic stat_rd_busy;
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logic stat_wr_busy;
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logic stat_err_cor;
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logic stat_err_uncor;
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logic [$clog2(RD_OP_TBL_SIZE)-1:0] stat_rd_op_start_tag;
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logic stat_rd_op_start_valid;
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logic [$clog2(RD_OP_TBL_SIZE)-1:0] stat_rd_op_finish_tag;
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logic [3:0] stat_rd_op_finish_status;
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logic stat_rd_op_finish_valid;
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logic [$clog2(PCIE_TAG_CNT)-1:0] stat_rd_req_start_tag;
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logic [12:0] stat_rd_req_start_len;
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logic stat_rd_req_start_valid;
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logic [$clog2(PCIE_TAG_CNT)-1:0] stat_rd_req_finish_tag;
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logic [3:0] stat_rd_req_finish_status;
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logic stat_rd_req_finish_valid;
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logic stat_rd_req_timeout;
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logic stat_rd_op_tbl_full;
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logic stat_rd_no_tags;
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logic stat_rd_tx_limit;
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logic stat_rd_tx_stall;
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logic [$clog2(WR_OP_TBL_SIZE)-1:0] stat_wr_op_start_tag;
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logic stat_wr_op_start_valid;
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logic [$clog2(WR_OP_TBL_SIZE)-1:0] stat_wr_op_finish_tag;
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logic [3:0] stat_wr_op_finish_status;
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logic stat_wr_op_finish_valid;
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logic [$clog2(WR_OP_TBL_SIZE)-1:0] stat_wr_req_start_tag;
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logic [12:0] stat_wr_req_start_len;
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logic stat_wr_req_start_valid;
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logic [$clog2(WR_OP_TBL_SIZE)-1:0] stat_wr_req_finish_tag;
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logic [3:0] stat_wr_req_finish_status;
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logic stat_wr_req_finish_valid;
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logic stat_wr_op_tbl_full;
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logic stat_wr_tx_limit;
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logic stat_wr_tx_stall;
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// register to break timing path from PCIe HIP 500 MHz clock domain
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logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0_reg = '0;
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logic pcie_rq_seq_num_vld0_reg = 1'b0;
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logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1_reg = '0;
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logic pcie_rq_seq_num_vld1_reg = 1'b0;
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always_ff @(posedge pcie_clk) begin
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pcie_rq_seq_num0_reg <= pcie_rq_seq_num0;
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pcie_rq_seq_num_vld0_reg <= pcie_rq_seq_num_vld0;
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pcie_rq_seq_num1_reg <= pcie_rq_seq_num1;
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pcie_rq_seq_num_vld1_reg <= pcie_rq_seq_num_vld1;
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if (pcie_rst) begin
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pcie_rq_seq_num_vld0_reg <= 1'b0;
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pcie_rq_seq_num_vld1_reg <= 1'b0;
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end
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end
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taxi_dma_if_pcie_us #(
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.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
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.RQ_SEQ_NUM_EN(RQ_SEQ_NUM_EN),
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.PCIE_TAG_CNT(PCIE_TAG_CNT),
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.RD_OP_TBL_SIZE(RD_OP_TBL_SIZE),
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.RD_TX_LIMIT(RD_TX_LIMIT),
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.RD_TX_FC_EN(RD_TX_FC_EN),
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.RD_CPLH_FC_LIMIT(RD_CPLH_FC_LIMIT),
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.RD_CPLD_FC_LIMIT(RD_CPLD_FC_LIMIT),
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.WR_OP_TBL_SIZE(WR_OP_TBL_SIZE),
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.WR_TX_LIMIT(WR_TX_LIMIT),
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.WR_TX_FC_EN(WR_TX_FC_EN)
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)
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dma_if_inst (
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.clk(pcie_clk),
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.rst(pcie_rst),
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/*
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* UltraScale PCIe interface
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*/
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.m_axis_rq(m_axis_pcie_rq),
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.s_axis_rc(s_axis_pcie_rc),
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/*
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* Transmit sequence number input
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*/
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.s_axis_rq_seq_num_0(pcie_rq_seq_num0_reg),
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.s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0_reg),
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.s_axis_rq_seq_num_1(pcie_rq_seq_num1_reg),
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.s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1_reg),
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/*
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* Transmit flow control
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*/
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.pcie_tx_fc_nph_av(cfg_fc_nph),
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.pcie_tx_fc_ph_av(cfg_fc_ph),
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.pcie_tx_fc_pd_av(cfg_fc_pd),
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/*
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* Read descriptor
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*/
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.rd_desc_req(dma_rd_desc),
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.rd_desc_sts(dma_rd_desc),
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/*
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* Write descriptor
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*/
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.wr_desc_req(dma_wr_desc),
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.wr_desc_sts(dma_wr_desc),
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/*
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* RAM interface
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*/
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.dma_ram_wr(dma_ram),
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.dma_ram_rd(dma_ram),
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/*
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* Configuration
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*/
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.read_enable(1'b1),
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.write_enable(1'b1),
|
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.ext_tag_en(1'b0), // TODO
|
||||
.rcb_128b(cfg_rcb_status[0]),
|
||||
.requester_id('0),
|
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.requester_id_en(1'b0),
|
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.max_rd_req_size(cfg_max_read_req),
|
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.max_payload_size(cfg_max_payload),
|
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/*
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* Status
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*/
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.stat_rd_busy(stat_rd_busy),
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.stat_wr_busy(stat_wr_busy),
|
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.stat_err_cor(stat_err_cor),
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.stat_err_uncor(stat_err_uncor),
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/*
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* Statistics
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*/
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.stat_rd_op_start_tag(stat_rd_op_start_tag),
|
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.stat_rd_op_start_valid(stat_rd_op_start_valid),
|
||||
.stat_rd_op_finish_tag(stat_rd_op_finish_tag),
|
||||
.stat_rd_op_finish_status(stat_rd_op_finish_status),
|
||||
.stat_rd_op_finish_valid(stat_rd_op_finish_valid),
|
||||
.stat_rd_req_start_tag(stat_rd_req_start_tag),
|
||||
.stat_rd_req_start_len(stat_rd_req_start_len),
|
||||
.stat_rd_req_start_valid(stat_rd_req_start_valid),
|
||||
.stat_rd_req_finish_tag(stat_rd_req_finish_tag),
|
||||
.stat_rd_req_finish_status(stat_rd_req_finish_status),
|
||||
.stat_rd_req_finish_valid(stat_rd_req_finish_valid),
|
||||
.stat_rd_req_timeout(stat_rd_req_timeout),
|
||||
.stat_rd_op_tbl_full(stat_rd_op_tbl_full),
|
||||
.stat_rd_no_tags(stat_rd_no_tags),
|
||||
.stat_rd_tx_limit(stat_rd_tx_limit),
|
||||
.stat_rd_tx_stall(stat_rd_tx_stall),
|
||||
.stat_wr_op_start_tag(stat_wr_op_start_tag),
|
||||
.stat_wr_op_start_valid(stat_wr_op_start_valid),
|
||||
.stat_wr_op_finish_tag(stat_wr_op_finish_tag),
|
||||
.stat_wr_op_finish_status(stat_wr_op_finish_status),
|
||||
.stat_wr_op_finish_valid(stat_wr_op_finish_valid),
|
||||
.stat_wr_req_start_tag(stat_wr_req_start_tag),
|
||||
.stat_wr_req_start_len(stat_wr_req_start_len),
|
||||
.stat_wr_req_start_valid(stat_wr_req_start_valid),
|
||||
.stat_wr_req_finish_tag(stat_wr_req_finish_tag),
|
||||
.stat_wr_req_finish_status(stat_wr_req_finish_status),
|
||||
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
|
||||
.stat_wr_op_tbl_full(stat_wr_op_tbl_full),
|
||||
.stat_wr_tx_limit(stat_wr_tx_limit),
|
||||
.stat_wr_tx_stall(stat_wr_tx_stall)
|
||||
);
|
||||
|
||||
wire [PORTS-1:0] irq;
|
||||
wire [31:0] msi_irq = 32'(irq);
|
||||
|
||||
taxi_pcie_us_msi #(
|
||||
.MSI_CNT(32)
|
||||
)
|
||||
msi_inst (
|
||||
.clk(pcie_clk),
|
||||
.rst(pcie_rst),
|
||||
|
||||
/*
|
||||
* Interrupt request inputs
|
||||
*/
|
||||
.msi_irq(msi_irq),
|
||||
|
||||
/*
|
||||
* Interface to UltraScale PCIe IP core
|
||||
*/
|
||||
/* verilator lint_off WIDTHEXPAND */
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
|
||||
/* verilator lint_on WIDTHEXPAND */
|
||||
);
|
||||
|
||||
cndm_proto_core #(
|
||||
.PORTS(PORTS)
|
||||
)
|
||||
core_inst (
|
||||
.clk(pcie_clk),
|
||||
.rst(pcie_rst),
|
||||
|
||||
/*
|
||||
* Control register interface
|
||||
*/
|
||||
.s_axil_wr(axil_ctrl_bar),
|
||||
.s_axil_rd(axil_ctrl_bar),
|
||||
|
||||
/*
|
||||
* DMA
|
||||
*/
|
||||
.dma_rd_desc_req(dma_rd_desc),
|
||||
.dma_rd_desc_sts(dma_rd_desc),
|
||||
.dma_wr_desc_req(dma_wr_desc),
|
||||
.dma_wr_desc_sts(dma_wr_desc),
|
||||
.dma_ram_wr(dma_ram),
|
||||
.dma_ram_rd(dma_ram),
|
||||
|
||||
.irq(irq),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.mac_tx_clk(mac_tx_clk),
|
||||
.mac_tx_rst(mac_tx_rst),
|
||||
.mac_axis_tx(mac_axis_tx),
|
||||
.mac_axis_tx_cpl(mac_axis_tx_cpl),
|
||||
|
||||
.mac_rx_clk(mac_rx_clk),
|
||||
.mac_rx_rst(mac_rx_rst),
|
||||
.mac_axis_rx(mac_axis_rx)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user