diff --git a/rtl/eth/taxi_axis_baser_tx_64.sv b/rtl/eth/taxi_axis_baser_tx_64.sv
index cd4df2a..f3b725b 100644
--- a/rtl/eth/taxi_axis_baser_tx_64.sv
+++ b/rtl/eth/taxi_axis_baser_tx_64.sv
@@ -51,7 +51,7 @@ module taxi_axis_baser_tx_64 #
     /*
      * Configuration
      */
-    input  wire logic [7:0]           cfg_ifg,
+    input  wire logic [7:0]           cfg_ifg = 8'd12,
     input  wire logic                 cfg_tx_enable,
 
     /*
diff --git a/rtl/eth/taxi_axis_gmii_tx.sv b/rtl/eth/taxi_axis_gmii_tx.sv
index 220a024..b6f97e5 100644
--- a/rtl/eth/taxi_axis_gmii_tx.sv
+++ b/rtl/eth/taxi_axis_gmii_tx.sv
@@ -55,7 +55,7 @@ module taxi_axis_gmii_tx #
     /*
      * Configuration
      */
-    input  wire logic [7:0]           cfg_ifg,
+    input  wire logic [7:0]           cfg_ifg = 8'd12,
     input  wire logic                 cfg_tx_enable,
 
     /*
diff --git a/rtl/eth/taxi_axis_xgmii_tx_32.sv b/rtl/eth/taxi_axis_xgmii_tx_32.sv
index f749229..2792e88 100644
--- a/rtl/eth/taxi_axis_xgmii_tx_32.sv
+++ b/rtl/eth/taxi_axis_xgmii_tx_32.sv
@@ -50,7 +50,7 @@ module taxi_axis_xgmii_tx_32 #
     /*
      * Configuration
      */
-    input  wire logic [7:0]           cfg_ifg,
+    input  wire logic [7:0]           cfg_ifg = 8'd12,
     input  wire logic                 cfg_tx_enable,
 
     /*
diff --git a/rtl/eth/taxi_axis_xgmii_tx_64.sv b/rtl/eth/taxi_axis_xgmii_tx_64.sv
index 0d50a67..163bc8e 100644
--- a/rtl/eth/taxi_axis_xgmii_tx_64.sv
+++ b/rtl/eth/taxi_axis_xgmii_tx_64.sv
@@ -51,7 +51,7 @@ module taxi_axis_xgmii_tx_64 #
     /*
      * Configuration
      */
-    input  wire logic [7:0]           cfg_ifg,
+    input  wire logic [7:0]           cfg_ifg = 8'd12,
     input  wire logic                 cfg_tx_enable,
 
     /*
diff --git a/rtl/eth/taxi_eth_mac_phy_10g_tx.sv b/rtl/eth/taxi_eth_mac_phy_10g_tx.sv
index f2b15a7..ebf8d96 100644
--- a/rtl/eth/taxi_eth_mac_phy_10g_tx.sv
+++ b/rtl/eth/taxi_eth_mac_phy_10g_tx.sv
@@ -61,7 +61,7 @@ module taxi_eth_mac_phy_10g_tx #
     /*
      * Configuration
      */
-    input  wire logic [7:0]           cfg_ifg,
+    input  wire logic [7:0]           cfg_ifg = 8'd12,
     input  wire logic                 cfg_tx_enable,
     input  wire logic                 cfg_tx_prbs31_enable
 );