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eth: Fix family in KC705 testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-04-13 13:26:59 -07:00
parent f35ff7aa32
commit 766e91a224
2 changed files with 2 additions and 2 deletions
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2
src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py
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@@ -217,7 +217,7 @@ def test_fpga_core(request, phy_type):
parameters['SIM'] = "1'b1"
parameters['VENDOR'] = "\"XILINX\""
parameters['FAMILY'] = "\"artix7\""
parameters['FAMILY'] = "\"kintex7\""
parameters['USE_CLK90'] = "1'b1"
parameters['BASET_PHY_TYPE'] = f"\"{phy_type}\""
parameters['SFP_INVERT'] = "1'b1"

2
src/eth/example/KC705/fpga_10g/tb/fpga_core/test_fpga_core.py
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@@ -287,7 +287,7 @@ def test_fpga_core(request, phy_type):
parameters['SIM'] = "1'b1"
parameters['VENDOR'] = "\"XILINX\""
parameters['FAMILY'] = "\"artix7\""
parameters['FAMILY'] = "\"kintex7\""
parameters['USE_CLK90'] = "1'b1"
parameters['BASET_PHY_TYPE'] = f"\"{phy_type}\""
parameters['SFP_INVERT'] = "1'b1"