mirror of
https://github.com/fpganinja/taxi.git
synced 2026-02-28 14:05:10 -08:00
cndm: Add support for Alveo U280
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -47,6 +47,12 @@ This design targets the Xilinx Alveo series.
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* PCIe: gen 3 x16 (~128 Gbps)
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* Reference oscillator: 156.25 MHz from Si570
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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* AU280
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* FPGA: xcu280-fsvh2892-2L-e
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* USB UART: FTDI FT4232H
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* PCIe: gen 3 x16 (~128 Gbps) or dual bifurcated gen 4 x8 (~256 Gbps)
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* Reference oscillator: 156.25 MHz from Si570
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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* VCU1525
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* FPGA: xcvu9p-fsgd2104-2L-e
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* USB UART: FTDI FT4232H
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98
src/cndm/board/Alveo/fpga/fpga_AU280/Makefile
Normal file
98
src/cndm/board/Alveo/fpga/fpga_AU280/Makefile
Normal file
@@ -0,0 +1,98 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# FPGA settings
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FPGA_PART = xcu280-fsvh2892-2L-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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RTL_DIR = ../rtl
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LIB_DIR = ../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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# Files for synthesis
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SYN_FILES = $(RTL_DIR)/fpga_au280.sv
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SYN_FILES += $(RTL_DIR)/fpga_core.sv
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SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
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SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
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SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
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SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
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SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
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SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
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SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f
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# XDC files
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XDC_FILES = ../fpga_au280.xdc
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XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
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# IP
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IP_TCL_FILES = ../ip/pcie4c_uscale_plus_0.tcl
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IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(PROJECT).bit
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(PROJECT).mcs $(PROJECT).prm
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echo "open_hw_manager" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
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echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
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echo "program_hw_devices [current_hw_device]" >> flash.tcl
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echo "refresh_hw_device [current_hw_device]" >> flash.tcl
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echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
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echo "boot_hw_device [current_hw_device]" >> flash.tcl
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echo "exit" >> flash.tcl
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vivado -nojournal -nolog -mode batch -source flash.tcl
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131
src/cndm/board/Alveo/fpga/fpga_AU280/config.tcl
Normal file
131
src/cndm/board/Alveo/fpga/fpga_AU280/config.tcl
Normal file
@@ -0,0 +1,131 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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set params [dict create]
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# collect build information
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set build_date [clock seconds]
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set git_hash 00000000
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set git_tag ""
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if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
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puts "Error running git or project not under version control"
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}
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if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
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puts "Error running git, project not under version control, or no tag found"
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}
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puts "Build date: ${build_date}"
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puts "Git hash: ${git_hash}"
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puts "Git tag: ${git_tag}"
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if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
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puts "Failed to extract version from git tag"
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set tag_ver 0.0.1
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}
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puts "Tag version: ${tag_ver}"
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# FW and board IDs
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set fpga_id [expr 0x4B7D093]
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set fw_id [expr 0x0000C001]
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set fw_ver $tag_ver
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set board_vendor_id [expr 0x10ee]
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set board_device_id [expr 0x9118]
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set board_ver 1.0
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set release_info [expr 0x00000000]
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# PCIe IDs
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set pcie_vendor_id [expr 0x1234]
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set pcie_device_id [expr 0xC001]
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set pcie_class_code [expr 0x020000]
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set pcie_revision_id [expr 0x00]
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set pcie_subsystem_device_id $board_device_id
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set pcie_subsystem_vendor_id $board_vendor_id
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# FW ID
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dict set params FPGA_ID [format "32'h%08x" $fpga_id]
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dict set params FW_ID [format "32'h%08x" $fw_id]
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dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
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dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
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dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
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dict set params BUILD_DATE "32'd${build_date}"
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dict set params GIT_HASH "32'h${git_hash}"
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dict set params RELEASE_INFO [format "32'h%08x" $release_info]
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# PTP configuration
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dict set params PTP_TS_EN "1"
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# AXI lite interface configuration (control)
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dict set params AXIL_CTRL_DATA_W "32"
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dict set params AXIL_CTRL_ADDR_W "24"
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# MAC configuration
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dict set params CFG_LOW_LATENCY "1"
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dict set params COMBINED_MAC_PCS "1"
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dict set params MAC_DATA_W "64"
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# PCIe IP core settings
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set pcie [get_ips pcie4c_uscale_plus_0]
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# configure BAR settings
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proc configure_bar {pcie pf bar aperture} {
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set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
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for { set i 0 } { $i < [llength $size_list] } { incr i } {
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set scale [lindex $size_list $i]
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if {$aperture > 0 && $aperture < ($i+1)*10} {
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set size [expr 1 << $aperture - ($i*10)]
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puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
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set pcie_config [dict create]
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
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dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
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set_property -dict $pcie_config $pcie
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return
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}
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}
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puts "${pcie} PF${pf} BAR${bar}: disabled"
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set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
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}
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# Control BAR (BAR 0)
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configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
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# PCIe IP core configuration
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set pcie_config [dict create]
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# PCIe IDs
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dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
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dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
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dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
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dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
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dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
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dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
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# MSI
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dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
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set_property -dict $pcie_config $pcie
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# apply parameters to top-level
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set param_list {}
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dict for {name value} $params {
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lappend param_list $name=$value
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}
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set_property generic $param_list [get_filesets sources_1]
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98
src/cndm/board/Alveo/fpga/fpga_AU280_10g/Makefile
Normal file
98
src/cndm/board/Alveo/fpga/fpga_AU280_10g/Makefile
Normal file
@@ -0,0 +1,98 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# FPGA settings
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FPGA_PART = xcu280-fsvh2892-2L-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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RTL_DIR = ../rtl
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LIB_DIR = ../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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# Files for synthesis
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SYN_FILES = $(RTL_DIR)/fpga_au280.sv
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SYN_FILES += $(RTL_DIR)/fpga_core.sv
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SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
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SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
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SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
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SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
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SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
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SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
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SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f
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# XDC files
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XDC_FILES = ../fpga_au280.xdc
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XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
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# IP
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IP_TCL_FILES = ../ip/pcie4c_uscale_plus_0.tcl
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IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(PROJECT).bit
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(PROJECT).mcs $(PROJECT).prm
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echo "open_hw_manager" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
131
src/cndm/board/Alveo/fpga/fpga_AU280_10g/config.tcl
Normal file
131
src/cndm/board/Alveo/fpga/fpga_AU280_10g/config.tcl
Normal file
@@ -0,0 +1,131 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0x4B7D093]
|
||||
set fw_id [expr 0x0000C001]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x10ee]
|
||||
set board_device_id [expr 0x9118]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0xC001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
|
||||
# FW ID
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_TS_EN "1"
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_W "32"
|
||||
dict set params AXIL_CTRL_ADDR_W "24"
|
||||
|
||||
# MAC configuration
|
||||
dict set params CFG_LOW_LATENCY "1"
|
||||
dict set params COMBINED_MAC_PCS "1"
|
||||
dict set params MAC_DATA_W "32"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4c_uscale_plus_0]
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {pcie pf bar aperture} {
|
||||
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||
set scale [lindex $size_list $i]
|
||||
|
||||
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||
set size [expr 1 << $aperture - ($i*10)]
|
||||
|
||||
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||
|
||||
set pcie_config [dict create]
|
||||
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
return
|
||||
}
|
||||
}
|
||||
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
|
||||
|
||||
# PCIe IP core configuration
|
||||
set pcie_config [dict create]
|
||||
|
||||
# PCIe IDs
|
||||
dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
|
||||
dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
|
||||
dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
|
||||
dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
|
||||
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
|
||||
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
|
||||
|
||||
# MSI
|
||||
dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
503
src/cndm/board/Alveo/fpga/fpga_au280.xdc
Normal file
503
src/cndm/board/Alveo/fpga/fpga_au280.xdc
Normal file
@@ -0,0 +1,503 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx Alveo U280 board
|
||||
# part: xcu280-fsvh2892-2L-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p]
|
||||
#set_property -dict {LOC F31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n]
|
||||
#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p]
|
||||
|
||||
# SI570 user clock
|
||||
#set_property -dict {LOC G30 IOSTANDARD LVDS} [get_ports clk_si570_p]
|
||||
#set_property -dict {LOC F30 IOSTANDARD LVDS} [get_ports clk_si570_n]
|
||||
#create_clock -period 6.4 -name clk_si570 [get_ports clk_si570_p]
|
||||
|
||||
# Reset button
|
||||
set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset]
|
||||
|
||||
set_false_path -from [get_ports {reset}]
|
||||
set_input_delay 0 [get_ports {reset}]
|
||||
|
||||
# UART (U34 FT4232H channel CDBUS)
|
||||
set_property -dict {LOC B33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.39 CDBUS1 RXD
|
||||
set_property -dict {LOC A28 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.38 CDBUS0 TXD
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# HBM overtemp
|
||||
set_property -dict {LOC D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip]
|
||||
|
||||
set_false_path -to [get_ports {hbm_cattrip}]
|
||||
set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC L53 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L54 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L48 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L49 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K51 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K52 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L44 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J53 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J54 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K46 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K47 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H51 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H52 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J48 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J49 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC T42 } [get_ports {qsfp0_mgt_refclk_0_p}] ;# MGTREFCLK0P_134 from SI570
|
||||
set_property -dict {LOC T43 } [get_ports {qsfp0_mgt_refclk_0_n}] ;# MGTREFCLK0N_134 from SI570
|
||||
#set_property -dict {LOC R40 } [get_ports {qsfp0_mgt_refclk_1_p}] ;# MGTREFCLK1P_134 from SI546
|
||||
#set_property -dict {LOC R41 } [get_ports {qsfp0_mgt_refclk_1_n}] ;# MGTREFCLK1N_134 from SI546
|
||||
set_property -dict {LOC H32 IOSTANDARD LVCMOS18} [get_ports {qsfp0_refclk_oe_b}]
|
||||
set_property -dict {LOC G32 IOSTANDARD LVCMOS18} [get_ports {qsfp0_refclk_fs}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports {qsfp0_mgt_refclk_0_p}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI546, fs = 0)
|
||||
#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI546, fs = 1)
|
||||
#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
|
||||
set_property -dict {LOC G53 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G54 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G48 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G49 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E48 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E49 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A49 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A50 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC P42 } [get_ports {qsfp1_mgt_refclk_0_p}] ;# MGTREFCLK0P_135 from SI570
|
||||
set_property -dict {LOC P43 } [get_ports {qsfp1_mgt_refclk_0_n}] ;# MGTREFCLK0N_135 from SI570
|
||||
#set_property -dict {LOC M42 } [get_ports {qsfp1_mgt_refclk_1_p}] ;# MGTREFCLK1P_135 from SI546
|
||||
#set_property -dict {LOC M43 } [get_ports {qsfp1_mgt_refclk_1_n}] ;# MGTREFCLK1N_135 from SI546
|
||||
set_property -dict {LOC H30 IOSTANDARD LVCMOS18} [get_ports {qsfp1_refclk_oe_b}]
|
||||
set_property -dict {LOC G33 IOSTANDARD LVCMOS18} [get_ports {qsfp1_refclk_fs}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports {qsfp1_mgt_refclk_0_p}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI546, fs = 0)
|
||||
#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI546, fs = 1)
|
||||
#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}]
|
||||
set_output_delay 0 [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}]
|
||||
|
||||
# PCIe Interface
|
||||
set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AL15} [get_ports {pcie_refclk_0_p}] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AL14} [get_ports {pcie_refclk_0_n}] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK13} [get_ports {pcie_refclk_2_p}] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK12} [get_ports {pcie_refclk_2_n}] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7)
|
||||
set_property -dict {LOC AR15} [get_ports {pcie_refclk_1_p}] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
set_property -dict {LOC AR14} [get_ports {pcie_refclk_1_n}] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP13} [get_ports {pcie_refclk_3_p}] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP12} [get_ports {pcie_refclk_3_n}] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
set_property -dict {LOC BH26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports {pcie_refclk_0_p}]
|
||||
create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_1_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports {pcie_refclk_2_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports {pcie_refclk_3_p}]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
#set_property -dict {LOC BF46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
#set_property -dict {LOC BG43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
#set_property -dict {LOC BK45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
#set_property -dict {LOC BF42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
#set_property -dict {LOC BL45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
#set_property -dict {LOC BF43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
#set_property -dict {LOC BG42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
#set_property -dict {LOC BL43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
#set_property -dict {LOC BK43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
#set_property -dict {LOC BM42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
#set_property -dict {LOC BG45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
#set_property -dict {LOC BD41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
#set_property -dict {LOC BL42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
#set_property -dict {LOC BE44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
#set_property -dict {LOC BE43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
#set_property -dict {LOC BL46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
#set_property -dict {LOC BH44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
#set_property -dict {LOC BH45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
#set_property -dict {LOC BM47 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
#set_property -dict {LOC BF41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
#set_property -dict {LOC BE41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
#set_property -dict {LOC BH46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t}]
|
||||
#set_property -dict {LOC BJ46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c}]
|
||||
#set_property -dict {LOC BH42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
#set_property -dict {LOC BK46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
#set_property -dict {LOC BH41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
#set_property -dict {LOC BG44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
#set_property -dict {LOC BF45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
#set_property -dict {LOC BG33 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
#set_property -dict {LOC BN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
#set_property -dict {LOC BP32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
#set_property -dict {LOC BL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
#set_property -dict {LOC BM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
#set_property -dict {LOC BP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
#set_property -dict {LOC BP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
#set_property -dict {LOC BP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
#set_property -dict {LOC BN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
#set_property -dict {LOC BJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
#set_property -dict {LOC BH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
#set_property -dict {LOC BH29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
#set_property -dict {LOC BH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
#set_property -dict {LOC BF31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
#set_property -dict {LOC BG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
#set_property -dict {LOC BK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
#set_property -dict {LOC BL31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
#set_property -dict {LOC BK33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
#set_property -dict {LOC BL33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
#set_property -dict {LOC BL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
#set_property -dict {LOC BM33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
#set_property -dict {LOC BN34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
#set_property -dict {LOC BP34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
#set_property -dict {LOC BH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
#set_property -dict {LOC BH35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
#set_property -dict {LOC BJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
#set_property -dict {LOC BJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
#set_property -dict {LOC BG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
#set_property -dict {LOC BG35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
#set_property -dict {LOC BM52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
#set_property -dict {LOC BL53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
#set_property -dict {LOC BL52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
#set_property -dict {LOC BL51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
#set_property -dict {LOC BN50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
#set_property -dict {LOC BN51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
#set_property -dict {LOC BN49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
#set_property -dict {LOC BM48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
#set_property -dict {LOC BE50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
#set_property -dict {LOC BE49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
#set_property -dict {LOC BE51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
#set_property -dict {LOC BD51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
#set_property -dict {LOC BF52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
#set_property -dict {LOC BF51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
#set_property -dict {LOC BG50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
#set_property -dict {LOC BF50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
#set_property -dict {LOC BH50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
#set_property -dict {LOC BJ51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
#set_property -dict {LOC BH51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
#set_property -dict {LOC BH49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
#set_property -dict {LOC BK50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
#set_property -dict {LOC BK51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
#set_property -dict {LOC BJ49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
#set_property -dict {LOC BJ48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
#set_property -dict {LOC BN44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
#set_property -dict {LOC BN45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
#set_property -dict {LOC BM44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
#set_property -dict {LOC BM45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
#set_property -dict {LOC BP43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
#set_property -dict {LOC BP44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
#set_property -dict {LOC BN47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
#set_property -dict {LOC BP47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
#set_property -dict {LOC BG54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
#set_property -dict {LOC BG53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
#set_property -dict {LOC BE53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
#set_property -dict {LOC BE54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
#set_property -dict {LOC BH52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
#set_property -dict {LOC BG52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
#set_property -dict {LOC BK54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
#set_property -dict {LOC BK53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
#set_property -dict {LOC BN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
#set_property -dict {LOC BN30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
#set_property -dict {LOC BM28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
#set_property -dict {LOC BM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
#set_property -dict {LOC BJ29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
#set_property -dict {LOC BK30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
#set_property -dict {LOC BG29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
#set_property -dict {LOC BG30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
#set_property -dict {LOC BL35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
#set_property -dict {LOC BM35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
#set_property -dict {LOC BM34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
#set_property -dict {LOC BN35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
#set_property -dict {LOC BK34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
#set_property -dict {LOC BK35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
#set_property -dict {LOC BH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
#set_property -dict {LOC BJ32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
#set_property -dict {LOC BM49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
#set_property -dict {LOC BM50 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
#set_property -dict {LOC BP48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
#set_property -dict {LOC BP49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
#set_property -dict {LOC BF47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
#set_property -dict {LOC BF48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
#set_property -dict {LOC BG48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
#set_property -dict {LOC BG49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
#set_property -dict {LOC BH47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
#set_property -dict {LOC BJ47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
#set_property -dict {LOC BK48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
#set_property -dict {LOC BK49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
#set_property -dict {LOC BN46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
#set_property -dict {LOC BP46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
#set_property -dict {LOC BN42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
#set_property -dict {LOC BP42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
#set_property -dict {LOC BH54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
#set_property -dict {LOC BJ54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
#set_property -dict {LOC BJ52 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
#set_property -dict {LOC BJ53 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
#set_property -dict {LOC BF7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC BK1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC BF6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC BF5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC BE3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC BE6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC BE5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC BG7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC BJ1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC BG2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC BJ8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC BE4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC BL2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC BK5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC BK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC BJ4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC BF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC BG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC BK4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC BF3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC BF2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
#set_property -dict {LOC BJ3 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t}]
|
||||
#set_property -dict {LOC BJ2 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c}]
|
||||
#set_property -dict {LOC BE1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
#set_property -dict {LOC BL3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
#set_property -dict {LOC BG3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC BH2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
#set_property -dict {LOC BH1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC BH12 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
#set_property -dict {LOC A10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
#set_property -dict {LOC A9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
#set_property -dict {LOC A8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
#set_property -dict {LOC B12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
#set_property -dict {LOC C12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
#set_property -dict {LOC D11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
#set_property -dict {LOC E12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
#set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
#set_property -dict {LOC J11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
#set_property -dict {LOC J12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
#set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
#set_property -dict {LOC E14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
#set_property -dict {LOC BM3 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
#set_property -dict {LOC BM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
#set_property -dict {LOC BM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
#set_property -dict {LOC BL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
#set_property -dict {LOC BN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
#set_property -dict {LOC BN5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
#set_property -dict {LOC BN6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
#set_property -dict {LOC BN7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
#set_property -dict {LOC BJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
#set_property -dict {LOC BK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
#set_property -dict {LOC BK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
#set_property -dict {LOC BL10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
#set_property -dict {LOC BM9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
#set_property -dict {LOC BN9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
#set_property -dict {LOC BN10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
#set_property -dict {LOC BM10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
#set_property -dict {LOC BM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
#set_property -dict {LOC BM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
#set_property -dict {LOC BL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
#set_property -dict {LOC BM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
#set_property -dict {LOC BN12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
#set_property -dict {LOC BM12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
#set_property -dict {LOC BP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
#set_property -dict {LOC BP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
#set_property -dict {LOC BJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
#set_property -dict {LOC BJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
#set_property -dict {LOC BH15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
#set_property -dict {LOC BH14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
#set_property -dict {LOC BK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
#set_property -dict {LOC BK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
#set_property -dict {LOC BL12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
#set_property -dict {LOC BL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
#set_property -dict {LOC BE9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
#set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
#set_property -dict {LOC BE11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
#set_property -dict {LOC BG13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
#set_property -dict {LOC BG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
#set_property -dict {LOC BG9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
#set_property -dict {LOC BG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
#set_property -dict {LOC B13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
#set_property -dict {LOC A13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
#set_property -dict {LOC C10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
#set_property -dict {LOC C9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
#set_property -dict {LOC D9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
#set_property -dict {LOC H10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
#set_property -dict {LOC G10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
#set_property -dict {LOC H15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
#set_property -dict {LOC K14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
#set_property -dict {LOC D12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
#set_property -dict {LOC BL7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
#set_property -dict {LOC BM7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
#set_property -dict {LOC BP7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
#set_property -dict {LOC BP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
#set_property -dict {LOC BL8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
#set_property -dict {LOC BM8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
#set_property -dict {LOC BP9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
#set_property -dict {LOC BP8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
#set_property -dict {LOC BN15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
#set_property -dict {LOC BN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
#set_property -dict {LOC BP12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
#set_property -dict {LOC BP11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
#set_property -dict {LOC BJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
#set_property -dict {LOC BK13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
#set_property -dict {LOC BJ11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
#set_property -dict {LOC BK11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
#set_property -dict {LOC BF12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
#set_property -dict {LOC BF11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
#set_property -dict {LOC BH10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
#set_property -dict {LOC BH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
18
src/cndm/board/Alveo/fpga/ip/ddr4_0_au280.tcl
Normal file
18
src/cndm/board/Alveo/fpga/ip/ddr4_0_au280.tcl
Normal file
@@ -0,0 +1,18 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.System_Clock {No_Buffer} \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {9996} \
|
||||
CONFIG.C0.DDR4_MemoryType {RDIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
913
src/cndm/board/Alveo/fpga/rtl/fpga_au280.sv
Normal file
913
src/cndm/board/Alveo/fpga/rtl/fpga_au280.sv
Normal file
@@ -0,0 +1,913 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
|
||||
// FW ID
|
||||
parameter FPGA_ID = 32'h4B7D093,
|
||||
parameter FW_ID = 32'h0000C001,
|
||||
parameter FW_VER = 32'h000_01_000,
|
||||
parameter BOARD_ID = 32'h10ee_9118,
|
||||
parameter BOARD_VER = 32'h001_00_000,
|
||||
parameter BUILD_DATE = 32'd602976000,
|
||||
parameter GIT_HASH = 32'h5f87c2e8,
|
||||
parameter RELEASE_INFO = 32'h00000000,
|
||||
|
||||
// PTP configuration
|
||||
parameter logic PTP_TS_EN = 1'b1,
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
parameter AXIL_CTRL_DATA_W = 32,
|
||||
parameter AXIL_CTRL_ADDR_W = 24,
|
||||
|
||||
// MAC configuration
|
||||
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||
parameter MAC_DATA_W = 64
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire logic reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic hbm_cattrip,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic uart_txd,
|
||||
input wire logic uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic qsfp0_tx_p[4],
|
||||
output wire logic qsfp0_tx_n[4],
|
||||
input wire logic qsfp0_rx_p[4],
|
||||
input wire logic qsfp0_rx_n[4],
|
||||
input wire logic qsfp0_mgt_refclk_0_p,
|
||||
input wire logic qsfp0_mgt_refclk_0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_1_n,
|
||||
output wire logic qsfp0_refclk_oe_b,
|
||||
output wire logic qsfp0_refclk_fs,
|
||||
|
||||
output wire logic qsfp1_tx_p[4],
|
||||
output wire logic qsfp1_tx_n[4],
|
||||
input wire logic qsfp1_rx_p[4],
|
||||
input wire logic qsfp1_rx_n[4],
|
||||
input wire logic qsfp1_mgt_refclk_0_p,
|
||||
input wire logic qsfp1_mgt_refclk_0_n,
|
||||
// input wire logic qsfp1_mgt_refclk_1_p,
|
||||
// input wire logic qsfp1_mgt_refclk_1_n,
|
||||
output wire logic qsfp1_refclk_oe_b,
|
||||
output wire logic qsfp1_refclk_fs,
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
input wire logic [15:0] pcie_rx_p,
|
||||
input wire logic [15:0] pcie_rx_n,
|
||||
output wire logic [15:0] pcie_tx_p,
|
||||
output wire logic [15:0] pcie_tx_n,
|
||||
input wire logic pcie_refclk_1_p,
|
||||
input wire logic pcie_refclk_1_n,
|
||||
input wire logic pcie_reset_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
wire pcie_user_rst;
|
||||
|
||||
wire clk_156mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = ~reset;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 156.25 MHz input
|
||||
.CLKIN1_PERIOD(6.4),
|
||||
.REF_JITTER1(0.010),
|
||||
// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(8),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 156.25 MHz input
|
||||
.CLKIN1(clk_156mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
assign qsfp0_refclk_oe_b = 1'b0;
|
||||
assign qsfp0_refclk_fs = 1'b1;
|
||||
assign qsfp1_refclk_oe_b = 1'b0;
|
||||
assign qsfp1_refclk_fs = 1'b1;
|
||||
|
||||
localparam PORT_CNT = 2;
|
||||
localparam GTY_QUAD_CNT = PORT_CNT;
|
||||
localparam GTY_CNT = GTY_QUAD_CNT*4;
|
||||
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
|
||||
|
||||
wire eth_gty_tx_p[GTY_CNT];
|
||||
wire eth_gty_tx_n[GTY_CNT];
|
||||
wire eth_gty_rx_p[GTY_CNT];
|
||||
wire eth_gty_rx_n[GTY_CNT];
|
||||
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
|
||||
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
|
||||
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
|
||||
|
||||
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
|
||||
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
|
||||
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
|
||||
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
|
||||
|
||||
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
|
||||
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
|
||||
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
|
||||
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
|
||||
|
||||
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p;
|
||||
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n;
|
||||
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p;
|
||||
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
|
||||
|
||||
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
|
||||
|
||||
// Flash
|
||||
wire qspi_clk_int;
|
||||
wire [3:0] qspi_dq_int;
|
||||
wire [3:0] qspi_dq_i_int;
|
||||
wire [3:0] qspi_dq_o_int;
|
||||
wire [3:0] qspi_dq_oe_int;
|
||||
wire qspi_cs_int;
|
||||
|
||||
reg qspi_clk_reg;
|
||||
reg [3:0] qspi_dq_o_reg;
|
||||
reg [3:0] qspi_dq_oe_reg;
|
||||
reg qspi_cs_reg;
|
||||
|
||||
always_ff @(posedge pcie_user_clk) begin
|
||||
qspi_clk_reg <= qspi_clk_int;
|
||||
qspi_dq_o_reg <= qspi_dq_o_int;
|
||||
qspi_dq_oe_reg <= qspi_dq_oe_int;
|
||||
qspi_cs_reg <= qspi_cs_int;
|
||||
end
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(8),
|
||||
.N(2)
|
||||
)
|
||||
flash_sync_inst (
|
||||
.clk(pcie_user_clk),
|
||||
.in({qspi_dq_int}),
|
||||
.out({qspi_dq_i_int})
|
||||
);
|
||||
|
||||
STARTUPE3
|
||||
startupe3_inst (
|
||||
.CFGCLK(),
|
||||
.CFGMCLK(),
|
||||
.DI(qspi_dq_int),
|
||||
.DO(qspi_dq_o_reg),
|
||||
.DTS(~qspi_dq_oe_reg),
|
||||
.EOS(),
|
||||
.FCSBO(qspi_cs_reg),
|
||||
.FCSBTS(1'b0),
|
||||
.GSR(1'b0),
|
||||
.GTS(1'b0),
|
||||
.KEYCLEARB(1'b1),
|
||||
.PACK(1'b0),
|
||||
.PREQ(),
|
||||
.USRCCLKO(qspi_clk_reg),
|
||||
.USRCCLKTS(1'b0),
|
||||
.USRDONEO(1'b0),
|
||||
.USRDONETS(1'b1)
|
||||
);
|
||||
|
||||
// FPGA boot
|
||||
wire fpga_boot;
|
||||
wire fpga_boot_sync;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
fpga_boot_sync_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({fpga_boot}),
|
||||
.out({fpga_boot_sync})
|
||||
);
|
||||
|
||||
wire icap_avail;
|
||||
logic [2:0] icap_state_reg = 0;
|
||||
logic icap_csib_reg = 1'b1;
|
||||
logic icap_rdwrb_reg = 1'b0;
|
||||
logic [31:0] icap_di_reg = 32'hffffffff;
|
||||
|
||||
wire [31:0] icap_di_rev;
|
||||
|
||||
assign icap_di_rev[ 7] = icap_di_reg[ 0];
|
||||
assign icap_di_rev[ 6] = icap_di_reg[ 1];
|
||||
assign icap_di_rev[ 5] = icap_di_reg[ 2];
|
||||
assign icap_di_rev[ 4] = icap_di_reg[ 3];
|
||||
assign icap_di_rev[ 3] = icap_di_reg[ 4];
|
||||
assign icap_di_rev[ 2] = icap_di_reg[ 5];
|
||||
assign icap_di_rev[ 1] = icap_di_reg[ 6];
|
||||
assign icap_di_rev[ 0] = icap_di_reg[ 7];
|
||||
|
||||
assign icap_di_rev[15] = icap_di_reg[ 8];
|
||||
assign icap_di_rev[14] = icap_di_reg[ 9];
|
||||
assign icap_di_rev[13] = icap_di_reg[10];
|
||||
assign icap_di_rev[12] = icap_di_reg[11];
|
||||
assign icap_di_rev[11] = icap_di_reg[12];
|
||||
assign icap_di_rev[10] = icap_di_reg[13];
|
||||
assign icap_di_rev[ 9] = icap_di_reg[14];
|
||||
assign icap_di_rev[ 8] = icap_di_reg[15];
|
||||
|
||||
assign icap_di_rev[23] = icap_di_reg[16];
|
||||
assign icap_di_rev[22] = icap_di_reg[17];
|
||||
assign icap_di_rev[21] = icap_di_reg[18];
|
||||
assign icap_di_rev[20] = icap_di_reg[19];
|
||||
assign icap_di_rev[19] = icap_di_reg[20];
|
||||
assign icap_di_rev[18] = icap_di_reg[21];
|
||||
assign icap_di_rev[17] = icap_di_reg[22];
|
||||
assign icap_di_rev[16] = icap_di_reg[23];
|
||||
|
||||
assign icap_di_rev[31] = icap_di_reg[24];
|
||||
assign icap_di_rev[30] = icap_di_reg[25];
|
||||
assign icap_di_rev[29] = icap_di_reg[26];
|
||||
assign icap_di_rev[28] = icap_di_reg[27];
|
||||
assign icap_di_rev[27] = icap_di_reg[28];
|
||||
assign icap_di_rev[26] = icap_di_reg[29];
|
||||
assign icap_di_rev[25] = icap_di_reg[30];
|
||||
assign icap_di_rev[24] = icap_di_reg[31];
|
||||
|
||||
always_ff @(posedge clk_125mhz_int) begin
|
||||
case (icap_state_reg)
|
||||
0: begin
|
||||
icap_state_reg <= 0;
|
||||
icap_csib_reg <= 1'b1;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
|
||||
if (fpga_boot_sync && icap_avail) begin
|
||||
icap_state_reg <= 1;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
end
|
||||
end
|
||||
1: begin
|
||||
icap_state_reg <= 2;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hAA995566; // sync word
|
||||
end
|
||||
2: begin
|
||||
icap_state_reg <= 3;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
3: begin
|
||||
icap_state_reg <= 4;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h30008001; // write 1 word to CMD
|
||||
end
|
||||
4: begin
|
||||
icap_state_reg <= 5;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h0000000F; // IPROG
|
||||
end
|
||||
5: begin
|
||||
icap_state_reg <= 0;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
ICAPE3
|
||||
icape3_inst (
|
||||
.AVAIL(icap_avail),
|
||||
.CLK(clk_125mhz_int),
|
||||
.CSIB(icap_csib_reg),
|
||||
.I(icap_di_rev),
|
||||
.O(),
|
||||
.PRDONE(),
|
||||
.PRERROR(),
|
||||
.RDWRB(icap_rdwrb_reg)
|
||||
);
|
||||
|
||||
// PCIe
|
||||
localparam AXIS_PCIE_DATA_W = 512;
|
||||
localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32);
|
||||
localparam AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161;
|
||||
localparam AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137;
|
||||
localparam AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183;
|
||||
localparam AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81;
|
||||
localparam RC_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 256;
|
||||
localparam RQ_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 512;
|
||||
localparam CQ_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 512;
|
||||
localparam CC_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 512;
|
||||
|
||||
localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6;
|
||||
localparam RQ_SEQ_NUM_EN = 1;
|
||||
|
||||
localparam PCIE_TAG_CNT = AXIS_PCIE_RQ_USER_W == 60 ? 64 : 256;
|
||||
localparam BAR0_APERTURE = 24;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_CQ_USER_W)
|
||||
) axis_pcie_cq();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_CC_USER_W)
|
||||
) axis_pcie_cc();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_RQ_USER_W)
|
||||
) axis_pcie_rq();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_RC_USER_W)
|
||||
) axis_pcie_rc();
|
||||
|
||||
wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0;
|
||||
wire pcie_rq_seq_num_vld0;
|
||||
wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1;
|
||||
wire pcie_rq_seq_num_vld1;
|
||||
|
||||
wire [2:0] cfg_max_payload;
|
||||
wire [2:0] cfg_max_read_req;
|
||||
wire [3:0] cfg_rcb_status;
|
||||
|
||||
wire [9:0] cfg_mgmt_addr;
|
||||
wire [7:0] cfg_mgmt_function_number;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [31:0] cfg_mgmt_read_data;
|
||||
wire cfg_mgmt_read_write_done;
|
||||
|
||||
wire [7:0] cfg_fc_ph;
|
||||
wire [11:0] cfg_fc_pd;
|
||||
wire [7:0] cfg_fc_nph;
|
||||
wire [11:0] cfg_fc_npd;
|
||||
wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire cfg_ext_read_received;
|
||||
wire cfg_ext_write_received;
|
||||
wire [9:0] cfg_ext_register_number;
|
||||
wire [7:0] cfg_ext_function_number;
|
||||
wire [31:0] cfg_ext_write_data;
|
||||
wire [3:0] cfg_ext_write_byte_enable;
|
||||
wire [31:0] cfg_ext_read_data;
|
||||
wire cfg_ext_read_data_valid;
|
||||
|
||||
// wire [3:0] cfg_interrupt_msix_enable;
|
||||
// wire [3:0] cfg_interrupt_msix_mask;
|
||||
// wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
// wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
// wire [63:0] cfg_interrupt_msix_address;
|
||||
// wire [31:0] cfg_interrupt_msix_data;
|
||||
// wire cfg_interrupt_msix_int;
|
||||
// wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
// wire cfg_interrupt_msix_vec_pending_status;
|
||||
// wire cfg_interrupt_msix_sent;
|
||||
// wire cfg_interrupt_msix_fail;
|
||||
// wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [1:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [1:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [7:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire stat_err_cor;
|
||||
wire stat_err_uncor;
|
||||
|
||||
wire pcie_sys_clk;
|
||||
wire pcie_sys_clk_gt;
|
||||
|
||||
IBUFDS_GTE4 #(
|
||||
.REFCLK_HROW_CK_SEL(2'b00)
|
||||
)
|
||||
ibufds_gte4_pcie_refclk_inst (
|
||||
.I (pcie_refclk_1_p),
|
||||
.IB (pcie_refclk_1_n),
|
||||
.CEB (1'b0),
|
||||
.O (pcie_sys_clk_gt),
|
||||
.ODIV2 (pcie_sys_clk)
|
||||
);
|
||||
|
||||
pcie4c_uscale_plus_0
|
||||
pcie4c_uscale_plus_inst (
|
||||
.pci_exp_txn(pcie_tx_n),
|
||||
.pci_exp_txp(pcie_tx_p),
|
||||
.pci_exp_rxn(pcie_rx_n),
|
||||
.pci_exp_rxp(pcie_rx_p),
|
||||
.user_clk(pcie_user_clk),
|
||||
.user_reset(pcie_user_rst),
|
||||
.user_lnk_up(),
|
||||
|
||||
.s_axis_rq_tdata(axis_pcie_rq.tdata),
|
||||
.s_axis_rq_tkeep(axis_pcie_rq.tkeep),
|
||||
.s_axis_rq_tlast(axis_pcie_rq.tlast),
|
||||
.s_axis_rq_tready(axis_pcie_rq.tready),
|
||||
.s_axis_rq_tuser(axis_pcie_rq.tuser),
|
||||
.s_axis_rq_tvalid(axis_pcie_rq.tvalid),
|
||||
|
||||
.m_axis_rc_tdata(axis_pcie_rc.tdata),
|
||||
.m_axis_rc_tkeep(axis_pcie_rc.tkeep),
|
||||
.m_axis_rc_tlast(axis_pcie_rc.tlast),
|
||||
.m_axis_rc_tready(axis_pcie_rc.tready),
|
||||
.m_axis_rc_tuser(axis_pcie_rc.tuser),
|
||||
.m_axis_rc_tvalid(axis_pcie_rc.tvalid),
|
||||
|
||||
.m_axis_cq_tdata(axis_pcie_cq.tdata),
|
||||
.m_axis_cq_tkeep(axis_pcie_cq.tkeep),
|
||||
.m_axis_cq_tlast(axis_pcie_cq.tlast),
|
||||
.m_axis_cq_tready(axis_pcie_cq.tready),
|
||||
.m_axis_cq_tuser(axis_pcie_cq.tuser),
|
||||
.m_axis_cq_tvalid(axis_pcie_cq.tvalid),
|
||||
|
||||
.s_axis_cc_tdata(axis_pcie_cc.tdata),
|
||||
.s_axis_cc_tkeep(axis_pcie_cc.tkeep),
|
||||
.s_axis_cc_tlast(axis_pcie_cc.tlast),
|
||||
.s_axis_cc_tready(axis_pcie_cc.tready),
|
||||
.s_axis_cc_tuser(axis_pcie_cc.tuser),
|
||||
.s_axis_cc_tvalid(axis_pcie_cc.tvalid),
|
||||
|
||||
.pcie_rq_seq_num0(pcie_rq_seq_num0),
|
||||
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
|
||||
.pcie_rq_seq_num1(pcie_rq_seq_num1),
|
||||
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
|
||||
.pcie_rq_tag0(),
|
||||
.pcie_rq_tag1(),
|
||||
.pcie_rq_tag_av(),
|
||||
.pcie_rq_tag_vld0(),
|
||||
.pcie_rq_tag_vld1(),
|
||||
|
||||
.pcie_tfc_nph_av(),
|
||||
.pcie_tfc_npd_av(),
|
||||
|
||||
.pcie_cq_np_req(1'b1),
|
||||
.pcie_cq_np_req_count(),
|
||||
|
||||
.cfg_phy_link_down(),
|
||||
.cfg_phy_link_status(),
|
||||
.cfg_negotiated_width(),
|
||||
.cfg_current_speed(),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_function_status(),
|
||||
.cfg_function_power_state(),
|
||||
.cfg_vf_status(),
|
||||
.cfg_vf_power_state(),
|
||||
.cfg_link_power_state(),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_mgmt_debug_access(1'b0),
|
||||
|
||||
.cfg_err_cor_out(),
|
||||
.cfg_err_nonfatal_out(),
|
||||
.cfg_err_fatal_out(),
|
||||
.cfg_local_error_valid(),
|
||||
.cfg_local_error_out(),
|
||||
.cfg_ltssm_state(),
|
||||
.cfg_rx_pm_state(),
|
||||
.cfg_tx_pm_state(),
|
||||
.cfg_rcb_status(cfg_rcb_status),
|
||||
.cfg_obff_enable(),
|
||||
.cfg_pl_status_change(),
|
||||
.cfg_tph_requester_enable(),
|
||||
.cfg_tph_st_mode(),
|
||||
.cfg_vf_tph_requester_enable(),
|
||||
.cfg_vf_tph_st_mode(),
|
||||
|
||||
.cfg_msg_received(),
|
||||
.cfg_msg_received_data(),
|
||||
.cfg_msg_received_type(),
|
||||
.cfg_msg_transmit(1'b0),
|
||||
.cfg_msg_transmit_type(3'd0),
|
||||
.cfg_msg_transmit_data(32'd0),
|
||||
.cfg_msg_transmit_done(),
|
||||
|
||||
.cfg_fc_ph(cfg_fc_ph),
|
||||
.cfg_fc_pd(cfg_fc_pd),
|
||||
.cfg_fc_nph(cfg_fc_nph),
|
||||
.cfg_fc_npd(cfg_fc_npd),
|
||||
.cfg_fc_cplh(cfg_fc_cplh),
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_dsn(64'd0),
|
||||
|
||||
.cfg_bus_number(),
|
||||
|
||||
.cfg_power_state_change_ack(1'b1),
|
||||
.cfg_power_state_change_interrupt(),
|
||||
|
||||
.cfg_err_cor_in(stat_err_cor),
|
||||
.cfg_err_uncor_in(stat_err_uncor),
|
||||
.cfg_flr_in_process(),
|
||||
.cfg_flr_done(4'd0),
|
||||
.cfg_vf_flr_in_process(),
|
||||
.cfg_vf_flr_func_num(8'd0),
|
||||
.cfg_vf_flr_done(8'd0),
|
||||
|
||||
.cfg_link_training_enable(1'b1),
|
||||
|
||||
.cfg_ext_read_received(cfg_ext_read_received),
|
||||
.cfg_ext_write_received(cfg_ext_write_received),
|
||||
.cfg_ext_register_number(cfg_ext_register_number),
|
||||
.cfg_ext_function_number(cfg_ext_function_number),
|
||||
.cfg_ext_write_data(cfg_ext_write_data),
|
||||
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||
.cfg_ext_read_data(cfg_ext_read_data),
|
||||
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
// .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
// .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
// .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
// .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
// .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
// .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
// .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
// .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
// .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
// .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
// .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
// .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
.cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
|
||||
|
||||
.cfg_hot_reset_out(),
|
||||
|
||||
.cfg_config_space_enable(1'b1),
|
||||
.cfg_req_pm_transition_l23_ready(1'b0),
|
||||
.cfg_hot_reset_in(1'b0),
|
||||
|
||||
.cfg_ds_port_number(8'd0),
|
||||
.cfg_ds_bus_number(8'd0),
|
||||
.cfg_ds_device_number(5'd0),
|
||||
|
||||
.sys_clk(pcie_sys_clk),
|
||||
.sys_clk_gt(pcie_sys_clk_gt),
|
||||
.sys_reset(pcie_reset_n),
|
||||
|
||||
.phy_rdy_out()
|
||||
);
|
||||
|
||||
wire uart_rxd_int[1];
|
||||
wire uart_txd_int[1];
|
||||
|
||||
assign uart_txd = uart_txd_int[0];
|
||||
assign uart_rxd_int[0] = uart_rxd;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
// Board configuration
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(1),
|
||||
.PORT_CNT(PORT_CNT),
|
||||
.GTY_QUAD_CNT(GTY_QUAD_CNT),
|
||||
.GTY_CNT(GTY_CNT),
|
||||
.GTY_CLK_CNT(GTY_CLK_CNT),
|
||||
|
||||
// FW ID
|
||||
.FPGA_ID(FPGA_ID),
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.BUILD_DATE(BUILD_DATE),
|
||||
.GIT_HASH(GIT_HASH),
|
||||
.RELEASE_INFO(RELEASE_INFO),
|
||||
|
||||
// PTP configuration
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_CLK_PER_NS_NUM(32),
|
||||
.PTP_CLK_PER_NS_DENOM(5),
|
||||
|
||||
// PCIe interface configuration
|
||||
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
.AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
|
||||
.AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W),
|
||||
|
||||
// MAC configuration
|
||||
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||
.MAC_DATA_W(MAC_DATA_W)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd_int),
|
||||
.uart_rxd(uart_rxd_int),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p(eth_gty_tx_p),
|
||||
.eth_gty_tx_n(eth_gty_tx_n),
|
||||
.eth_gty_rx_p(eth_gty_rx_p),
|
||||
.eth_gty_rx_n(eth_gty_rx_n),
|
||||
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
|
||||
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
|
||||
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode(),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
.pcie_clk(pcie_user_clk),
|
||||
.pcie_rst(pcie_user_rst),
|
||||
.s_axis_pcie_cq(axis_pcie_cq),
|
||||
.m_axis_pcie_cc(axis_pcie_cc),
|
||||
.m_axis_pcie_rq(axis_pcie_rq),
|
||||
.s_axis_pcie_rc(axis_pcie_rc),
|
||||
|
||||
.pcie_rq_seq_num0(pcie_rq_seq_num0),
|
||||
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
|
||||
.pcie_rq_seq_num1(pcie_rq_seq_num1),
|
||||
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
|
||||
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_rcb_status(cfg_rcb_status),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
|
||||
.cfg_fc_ph(cfg_fc_ph),
|
||||
.cfg_fc_pd(cfg_fc_pd),
|
||||
.cfg_fc_nph(cfg_fc_nph),
|
||||
.cfg_fc_npd(cfg_fc_npd),
|
||||
.cfg_fc_cplh(cfg_fc_cplh),
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_ext_read_received(cfg_ext_read_received),
|
||||
.cfg_ext_write_received(cfg_ext_write_received),
|
||||
.cfg_ext_register_number(cfg_ext_register_number),
|
||||
.cfg_ext_function_number(cfg_ext_function_number),
|
||||
.cfg_ext_write_data(cfg_ext_write_data),
|
||||
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||
.cfg_ext_read_data(cfg_ext_read_data),
|
||||
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||
|
||||
// .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
// .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
// .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
// .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
// .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
// .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
// .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
// .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
// .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
// .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
// .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
// .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
.fpga_boot(fpga_boot),
|
||||
.qspi_clk(qspi_clk_int),
|
||||
.qspi_dq_i(qspi_dq_i_int),
|
||||
.qspi_dq_o(qspi_dq_o_int),
|
||||
.qspi_dq_oe(qspi_dq_oe_int),
|
||||
.qspi_cs(qspi_cs_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user