diff --git a/src/eth/example/KC705/fpga/fpga.xdc b/src/eth/example/KC705/fpga/fpga.xdc
index 7ab5cc3..73e7bc5 100644
--- a/src/eth/example/KC705/fpga/fpga.xdc
+++ b/src/eth/example/KC705/fpga/fpga.xdc
@@ -151,6 +151,7 @@ set_property -dict {LOC G7   } [get_ports sgmii_mgt_refclk_n] ;# MGTREFCLK0N_117
 #set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
 
 set_property -dict {LOC Y20  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
+set_property -dict {LOC P19  IOSTANDARD LVCMOS25} [get_ports {sfp_rx_los}]
 
 # 125 MHz MGT reference clock (SGMII, 1000BASE-X)
 #create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p]
diff --git a/src/eth/example/KC705/fpga/rtl/fpga.sv b/src/eth/example/KC705/fpga/rtl/fpga.sv
index c371f74..b646a9f 100644
--- a/src/eth/example/KC705/fpga/rtl/fpga.sv
+++ b/src/eth/example/KC705/fpga/rtl/fpga.sv
@@ -80,6 +80,7 @@ module fpga #
     input  wire logic        sgmii_mgt_refclk_n,
 
     output wire logic        sfp_tx_disable_b,
+    input  wire logic        sfp_rx_los,
 
     /*
      * Ethernet: 1000BASE-T GMII, RGMII, or SGMII
@@ -700,6 +701,7 @@ core_inst (
     .sfp_gmii_tx_en(sfp_gmii_tx_en_int),
     .sfp_gmii_tx_er(sfp_gmii_tx_er_int),
     .sfp_tx_disable_b(sfp_tx_disable_b),
+    .sfp_rx_los(sfp_rx_los),
 
     /*
      * Ethernet: 1000BASE-T GMII/RGMII/SGMII
diff --git a/src/eth/example/KC705/fpga/rtl/fpga_core.sv b/src/eth/example/KC705/fpga/rtl/fpga_core.sv
index b72b60e..8d92cd2 100644
--- a/src/eth/example/KC705/fpga/rtl/fpga_core.sv
+++ b/src/eth/example/KC705/fpga/rtl/fpga_core.sv
@@ -79,6 +79,7 @@ module fpga_core #
     output wire logic        sfp_gmii_tx_en,
     output wire logic        sfp_gmii_tx_er,
     output wire logic        sfp_tx_disable_b,
+    input  wire logic        sfp_rx_los,
 
     /*
      * Ethernet: 1000BASE-T
diff --git a/src/eth/example/KC705/fpga_10g/fpga.xdc b/src/eth/example/KC705/fpga_10g/fpga.xdc
index 7afceba..b26cd32 100644
--- a/src/eth/example/KC705/fpga_10g/fpga.xdc
+++ b/src/eth/example/KC705/fpga_10g/fpga.xdc
@@ -151,6 +151,7 @@ set_property -dict {LOC AE20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports
 set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
 
 set_property -dict {LOC Y20  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
+set_property -dict {LOC P19  IOSTANDARD LVCMOS25} [get_ports {sfp_rx_los}]
 
 # 125 MHz MGT reference clock (SGMII, 1000BASE-X)
 #create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p]
diff --git a/src/eth/example/KC705/fpga_10g/rtl/fpga.sv b/src/eth/example/KC705/fpga_10g/rtl/fpga.sv
index a281307..d54cc3c 100644
--- a/src/eth/example/KC705/fpga_10g/rtl/fpga.sv
+++ b/src/eth/example/KC705/fpga_10g/rtl/fpga.sv
@@ -84,6 +84,7 @@ module fpga #
     input  wire logic        si5324_int,
 
     output wire logic        sfp_tx_disable_b,
+    input  wire logic        sfp_rx_los,
 
     /*
      * Ethernet: 1000BASE-T GMII or RGMII
@@ -526,6 +527,7 @@ core_inst (
     .sfp_mgt_refclk_n(sfp_mgt_refclk_n),
 
     .sfp_tx_disable_b(sfp_tx_disable_b),
+    .sfp_rx_los(sfp_rx_los),
 
     /*
      * Ethernet: 1000BASE-T GMII/RGMII/SGMII
diff --git a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv
index 8f4b40c..3b2d834 100644
--- a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv
+++ b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv
@@ -81,6 +81,7 @@ module fpga_core #
     input  wire logic        sfp_mgt_refclk_n,
 
     output wire logic        sfp_tx_disable_b,
+    input  wire logic        sfp_rx_los,
 
     /*
      * Ethernet: 1000BASE-T