diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile b/src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile index 970fd59..f490b30 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile +++ b/src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile @@ -35,7 +35,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk @@ -86,4 +86,3 @@ flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $( echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/fpga/config.tcl b/src/eth/example/ADM_PCIE_9V3/fpga/fpga/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/ADM_PCIE_9V3/fpga/fpga/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile b/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile index 931743f..ee28624 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile +++ b/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile @@ -32,10 +32,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk @@ -86,4 +86,3 @@ flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $( echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/config.tcl b/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv index 6abe6a7..6e42145 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv @@ -17,9 +17,16 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", - parameter string FAMILY = "virtexuplus" + // device family + parameter string FAMILY = "virtexuplus", + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -76,12 +83,12 @@ wire mmcm_clkfb; IBUFGDS #( .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") + .IBUF_LOW_PWR("FALSE") ) clk_300mhz_ibufg_inst ( .O (clk_300mhz_ibufg), .I (clk_300mhz_p), - .IB (clk_300mhz_n) + .IB (clk_300mhz_n) ); // MMCM instance @@ -195,7 +202,10 @@ debounce_switch_inst ( fpga_core #( .SIM(SIM), .VENDOR(VENDOR), - .FAMILY(FAMILY) + .FAMILY(FAMILY), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index 6a7a572..4f6ee13 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -17,9 +17,16 @@ Authors: */ module fpga_core # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", - parameter string FAMILY = "virtexuplus" + // device family + parameter string FAMILY = "virtexuplus", + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -82,9 +89,9 @@ wire qsfp_0_mgt_refclk_bufg; wire qsfp_rst; -taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[8](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_tx[8](); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8](); -taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[8](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_rx[8](); taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat[2](); if (SIM) begin @@ -151,12 +158,14 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .CNT(CNT), // GT config - .CFG_LOW_LATENCY(1), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), // GT type .GT_TYPE("GTY"), // PHY parameters + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .DATA_W(MAC_DATA_W), .PADDING_EN(1'b1), .DIC_EN(1'b1), .MIN_FRAME_LEN(64), diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile index e791e57..913087b 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile @@ -39,6 +39,9 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) export PARAM_SIM := "1'b1" export PARAM_VENDOR := "\"XILINX\"" export PARAM_FAMILY := "\"virtexuplus\"" +export PARAM_CFG_LOW_LATENCY := "1'b1" +export PARAM_COMBINED_MAC_PCS := "1'b1" +export PARAM_MAC_DATA_W := "64" ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py index 9b19602..ac890b3 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py @@ -13,6 +13,7 @@ import logging import os import sys +import pytest import cocotb_test.simulator import cocotb @@ -50,12 +51,20 @@ class TB: for ch in inst.mac_inst.ch: gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) + else: + clk = 2.56 + gbx_cfg = None else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) @@ -108,6 +117,8 @@ async def mac_test(tb, source, sink): for k in range(1200): await RisingEdge(tb.dut.clk_125mhz) + sink.clear() + tb.log.info("Multiple small packets") count = 64 @@ -186,7 +197,8 @@ def process_f_files(files): return list(lst.values()) -def test_fpga_core(request): +@pytest.mark.parametrize("mac_data_w", [32, 64]) +def test_fpga_core(request, mac_data_w): dut = "fpga_core" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -207,6 +219,9 @@ def test_fpga_core(request): parameters['SIM'] = "1'b1" parameters['VENDOR'] = "\"XILINX\"" parameters['FAMILY'] = "\"virtexuplus\"" + parameters['CFG_LOW_LATENCY'] = "1'b1" + parameters['COMBINED_MAC_PCS'] = "1'b1" + parameters['MAC_DATA_W'] = mac_data_w extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}