diff --git a/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py b/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py index 1e74897..759340b 100644 --- a/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py +++ b/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py @@ -17,7 +17,6 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge -from cocotb.regression import TestFactory from cocotbext.axi import AxiStreamSource, AxiStreamSink, AxiStreamBus from cocotbext.i2c import I2cMemory @@ -96,6 +95,7 @@ class TB: await FallingEdge(self.dut.bus_active) +@cocotb.test() async def run_test_write(dut): tb = TB(dut) @@ -121,6 +121,7 @@ async def run_test_write(dut): await RisingEdge(dut.clk) +@cocotb.test() async def run_test_read(dut): tb = TB(dut) @@ -146,6 +147,7 @@ async def run_test_read(dut): await RisingEdge(dut.clk) +@cocotb.test() async def run_test_nack(dut): tb = TB(dut) @@ -161,18 +163,6 @@ async def run_test_nack(dut): await RisingEdge(dut.clk) -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_write, - run_test_read, - run_test_nack, - ]: - - factory = TestFactory(test) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py b/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py index a2e9f00..3ac8868 100644 --- a/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py +++ b/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py @@ -17,7 +17,6 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge -from cocotb.regression import TestFactory from cocotbext.i2c import I2cMaster @@ -49,6 +48,7 @@ class TB: await RisingEdge(self.dut.clk) +@cocotb.test() async def run_test_write(dut): tb = TB(dut) @@ -64,6 +64,7 @@ async def run_test_write(dut): await RisingEdge(dut.clk) +@cocotb.test() async def run_test_null_write(dut): tb = TB(dut) @@ -85,6 +86,7 @@ async def run_test_null_write(dut): await RisingEdge(dut.clk) +@cocotb.test() async def run_test_read(dut): tb = TB(dut) @@ -108,6 +110,7 @@ async def run_test_read(dut): await RisingEdge(dut.clk) +@cocotb.test() async def run_test_nack(dut): tb = TB(dut) @@ -131,19 +134,6 @@ async def run_test_nack(dut): await RisingEdge(dut.clk) -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_write, - run_test_null_write, - run_test_read, - run_test_nack, - ]: - - factory = TestFactory(test) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py b/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py index e72e77e..ca65e35 100644 --- a/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py +++ b/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py @@ -17,7 +17,6 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge -from cocotb.regression import TestFactory from cocotbext.axi import AxiStreamSource, AxiStreamSink, AxiStreamBus from cocotbext.i2c import I2cMaster @@ -55,7 +54,8 @@ class TB: await RisingEdge(self.dut.clk) -async def run_test(dut, payload_lengths=None, payload_data=None): +@cocotb.test() +async def run_test(dut): tb = TB(dut) @@ -95,12 +95,6 @@ async def run_test(dut, payload_lengths=None, payload_data=None): await RisingEdge(dut.clk) -if getattr(cocotb, 'top', None) is not None: - - factory = TestFactory(run_test) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/lss/tb/taxi_i2c_slave_apb_master/test_taxi_i2c_slave_apb_master.py b/src/lss/tb/taxi_i2c_slave_apb_master/test_taxi_i2c_slave_apb_master.py index 4ae66f4..aa8ccd5 100644 --- a/src/lss/tb/taxi_i2c_slave_apb_master/test_taxi_i2c_slave_apb_master.py +++ b/src/lss/tb/taxi_i2c_slave_apb_master/test_taxi_i2c_slave_apb_master.py @@ -19,7 +19,6 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge -from cocotb.regression import TestFactory from cocotbext.i2c import I2cMaster from cocotbext.axi import ApbBus, ApbRam @@ -58,7 +57,15 @@ class TB: await RisingEdge(self.dut.clk) -async def run_test_write(dut, data_in=None, backpressure_inserter=None): +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_write(dut, backpressure_inserter=None): tb = TB(dut) @@ -89,7 +96,11 @@ async def run_test_write(dut, data_in=None, backpressure_inserter=None): await RisingEdge(dut.clk) -async def run_test_read(dut, data_in=None, backpressure_inserter=None): +@cocotb.test() +@cocotb.parametrize( + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_read(dut, backpressure_inserter=None): tb = TB(dut) @@ -117,19 +128,6 @@ async def run_test_read(dut, data_in=None, backpressure_inserter=None): await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [run_test_write, run_test_read]: - - factory = TestFactory(test) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py b/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py index a2ce5b6..0403a40 100644 --- a/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py +++ b/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py @@ -12,15 +12,13 @@ Authors: import itertools import logging import os -import random import struct import cocotb_test.simulator import cocotb from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, Timer -from cocotb.regression import TestFactory +from cocotb.triggers import RisingEdge from cocotbext.i2c import I2cMaster from cocotbext.axi import AxiLiteBus, AxiLiteRam @@ -66,7 +64,16 @@ class TB: await RisingEdge(self.dut.clk) -async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -98,7 +105,12 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins await RisingEdge(dut.clk) -async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -127,20 +139,6 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [run_test_write, run_test_read]: - - factory = TestFactory(test) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/lss/tb/taxi_uart/test_taxi_uart.py b/src/lss/tb/taxi_uart/test_taxi_uart.py index 3aa2abf..b33d41c 100644 --- a/src/lss/tb/taxi_uart/test_taxi_uart.py +++ b/src/lss/tb/taxi_uart/test_taxi_uart.py @@ -18,7 +18,6 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer -from cocotb.regression import TestFactory from cocotbext.axi import AxiStreamSource, AxiStreamSink, AxiStreamBus from cocotbext.uart import UartSource, UartSink @@ -53,6 +52,34 @@ class TB: await RisingEdge(self.dut.clk) +def prbs31(state=0x7fffffff): + while True: + for i in range(8): + if bool(state & 0x08000000) ^ bool(state & 0x40000000): + state = ((state & 0x3fffffff) << 1) | 1 + else: + state = (state & 0x3fffffff) << 1 + yield state & 0xff + + +def size_list(): + return list(range(1, 16)) + [128] + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def prbs_payload(length): + gen = prbs31() + return bytearray([next(gen) for x in range(length)]) + + +@cocotb.test() +@cocotb.parametrize( + ("payload_lengths", [size_list]), + ("payload_data", [incrementing_payload, prbs_payload]), +) async def run_test_tx(dut, payload_lengths=None, payload_data=None): tb = TB(dut) @@ -78,6 +105,11 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("payload_lengths", [size_list]), + ("payload_data", [incrementing_payload, prbs_payload]), +) async def run_test_rx(dut, payload_lengths=None, payload_data=None): tb = TB(dut) @@ -103,38 +135,6 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None): await RisingEdge(dut.clk) -def prbs31(state=0x7fffffff): - while True: - for i in range(8): - if bool(state & 0x08000000) ^ bool(state & 0x40000000): - state = ((state & 0x3fffffff) << 1) | 1 - else: - state = (state & 0x3fffffff) << 1 - yield state & 0xff - - -def size_list(): - return list(range(1, 16)) + [128] - - -def incrementing_payload(length): - return bytearray(itertools.islice(itertools.cycle(range(256)), length)) - - -def prbs_payload(length): - gen = prbs31() - return bytearray([next(gen) for x in range(length)]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [run_test_tx, run_test_rx]: - factory = TestFactory(test) - factory.add_option("payload_lengths", [size_list]) - factory.add_option("payload_data", [incrementing_payload, prbs_payload]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__))