xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-11 18:33:57 -07:00
parent 8d4ad59727
commit 7df14e54e5
12 changed files with 432 additions and 432 deletions

View File

@@ -47,8 +47,8 @@ class TB(object):
self.uart_source = UartSource(dut.uart_rxd, baud=baud, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=baud, bits=8, stop_bits=1)
self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.dn_xfcp_in), dut.clk, dut.rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.dn_xfcp_out), dut.clk, dut.rst)
self.dsp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_dsp_us), dut.clk, dut.rst)
self.dsp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_dsp_ds), dut.clk, dut.rst)
dut.prescale.setimmediatevalue(int(1/8e-9/baud/8))
@@ -78,7 +78,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None):
pkt.ptype = 1
pkt.payload = test_data
await tb.axis_source.write(pkt.build())
await tb.dsp_source.write(pkt.build())
rx_data = bytearray()
while True:
@@ -114,13 +114,13 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None):
await tb.uart_source.write(pkt.build_cobs())
rx_frame = await tb.axis_sink.recv()
rx_frame = await tb.dsp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
print(rx_pkt)
assert rx_pkt == pkt
assert tb.axis_sink.empty()
assert tb.dsp_sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

View File

@@ -30,7 +30,7 @@ logic rst;
logic uart_rxd;
logic uart_txd;
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) dn_xfcp_in(), dn_xfcp_out();
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_dsp_ds(), xfcp_dsp_us();
logic [15:0] prescale;
@@ -51,8 +51,8 @@ uut (
/*
* XFCP downstream port
*/
.dn_xfcp_in(dn_xfcp_in),
.dn_xfcp_out(dn_xfcp_out),
.xfcp_dsp_ds(xfcp_dsp_ds),
.xfcp_dsp_us(xfcp_dsp_us),
/*
* Configuration