From 7e08164e8d7d8b50657b6e379860ab592d5333d0 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 4 Oct 2025 17:01:53 -0700 Subject: [PATCH] eth: Add term_first_cycle_reg to reduce fanin Signed-off-by: Alex Forencich --- src/eth/rtl/taxi_axis_xgmii_rx_32.sv | 13 ++++++++----- src/eth/rtl/taxi_axis_xgmii_rx_64.sv | 17 +++++++++++------ 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv index 513776c..1034e09 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv @@ -109,8 +109,9 @@ logic [1:0] state_reg = STATE_IDLE, state_next; // datapath control signals logic reset_crc; -logic [1:0] term_lane_reg = 0, term_lane_d0_reg = 0; logic term_present_reg = 1'b0; +logic term_first_cycle_reg = 1'b0; +logic [1:0] term_lane_reg = 0, term_lane_d0_reg = 0; logic framing_error_reg = 1'b0; logic [DATA_W-1:0] xgmii_rxd_d0 = '0; @@ -396,11 +397,11 @@ always_comb begin state_next = STATE_IDLE; end else if (term_present_reg) begin reset_crc = 1'b1; - if (term_lane_reg == 0) begin + if (term_first_cycle_reg) begin // end this cycle m_axis_rx_tkeep_next = 4'b1111; m_axis_rx_tlast_next = 1'b1; - if (term_lane_reg == 0 && crc_valid_save[3]) begin + if (crc_valid_save[3]) begin // CRC valid if (frame_oversize_next) begin // too long @@ -524,14 +525,16 @@ always_ff @(posedge clk) begin stat_rx_err_preamble_reg <= stat_rx_err_preamble_next; if (!GBX_IF_EN || xgmii_rx_valid) begin - term_lane_reg <= 0; term_present_reg <= 1'b0; + term_first_cycle_reg <= 1'b0; + term_lane_reg <= 0; framing_error_reg <= xgmii_rxc != 0; for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin - term_lane_reg <= 2'(i); term_present_reg <= 1'b1; + term_first_cycle_reg <= i == 0; + term_lane_reg <= 2'(i); framing_error_reg <= (xgmii_rxc & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; end end diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv index b724d00..3423c8e 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv @@ -114,8 +114,9 @@ logic [31:0] swap_rxd = 32'd0; logic [3:0] swap_rxc = 4'd0; logic [3:0] swap_rxc_term = 4'd0; -logic [2:0] term_lane_reg = 0, term_lane_d0_reg = 0; logic term_present_reg = 1'b0; +logic term_first_cycle_reg = 1'b0; +logic [2:0] term_lane_reg = 0, term_lane_d0_reg = 0; logic framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0; logic [DATA_W-1:0] xgmii_rxd_d0 = '0; @@ -393,7 +394,7 @@ always_comb begin state_next = STATE_IDLE; end else if (term_present_reg) begin reset_crc = 1'b1; - if (term_lane_reg <= 4) begin + if (term_first_cycle_reg) begin // end this cycle m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg); m_axis_rx_tlast_next = 1'b1; @@ -552,14 +553,16 @@ always_ff @(posedge clk) begin xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd}; xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc}; - term_lane_reg <= 0; term_present_reg <= 1'b0; + term_first_cycle_reg <= 1'b0; + term_lane_reg <= 0; framing_error_reg <= {xgmii_rxc[3:0], swap_rxc} != 0; for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin if ({xgmii_term[3:0], swap_rxc_term}[i]) begin - term_lane_reg <= 3'(i); term_present_reg <= 1'b1; + term_first_cycle_reg <= i <= 4; + term_lane_reg <= 3'(i); framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc} & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; end end @@ -567,14 +570,16 @@ always_ff @(posedge clk) begin xgmii_rxd_d0 <= xgmii_rxd_masked; xgmii_rxc_d0 <= xgmii_rxc; - term_lane_reg <= 0; term_present_reg <= 1'b0; + term_first_cycle_reg <= 1'b0; + term_lane_reg <= 0; framing_error_reg <= xgmii_rxc != 0; for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin - term_lane_reg <= 3'(i); term_present_reg <= 1'b1; + term_first_cycle_reg <= i <= 4; + term_lane_reg <= 3'(i); framing_error_reg <= (xgmii_rxc & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; end end