diff --git a/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py b/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py index 7bbab4c..9a80271 100644 --- a/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py +++ b/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py @@ -18,7 +18,6 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer -from cocotb.regression import TestFactory from cocotbext.axi import AxiStreamSource, AxiStreamSink, AxiStreamBus @@ -58,6 +57,15 @@ class TB(object): await RisingEdge(self.dut.clk) +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_irq(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -122,22 +130,6 @@ async def run_test_irq(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_irq - ]: - - factory = TestFactory(test) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py b/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py index 818ce6c..361fe0c 100644 --- a/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py +++ b/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py @@ -22,7 +22,6 @@ import pytest import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer -from cocotb.regression import TestFactory from cocotbext.pcie.core import RootComplex from cocotbext.axi import AxiLiteBus, AxiLiteRam @@ -128,6 +127,15 @@ class TB(object): await RisingEdge(self.dut.clk) +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -173,6 +181,11 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -218,6 +231,11 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -281,24 +299,6 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_write, - run_test_read, - run_test_bad_ops - ]: - - factory = TestFactory(test) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py b/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py index 0ed5a1d..a51e9f3 100644 --- a/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py +++ b/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py @@ -22,7 +22,6 @@ import pytest import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer -from cocotb.regression import TestFactory from cocotbext.pcie.core import RootComplex from cocotbext.axi import AxiLiteBus, AxiLiteRam @@ -127,6 +126,15 @@ class TB(object): await RisingEdge(self.dut.clk) +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -169,6 +177,11 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -211,6 +224,11 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -316,24 +334,6 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_write, - run_test_read, - run_test_bad_ops - ]: - - factory = TestFactory(test) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/pcie/tb/taxi_pcie_msix_apb/test_taxi_pcie_msix_apb.py b/src/pcie/tb/taxi_pcie_msix_apb/test_taxi_pcie_msix_apb.py index 0e94a5e..a24507c 100644 --- a/src/pcie/tb/taxi_pcie_msix_apb/test_taxi_pcie_msix_apb.py +++ b/src/pcie/tb/taxi_pcie_msix_apb/test_taxi_pcie_msix_apb.py @@ -22,7 +22,6 @@ import pytest import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge -from cocotb.regression import TestFactory from cocotbext.axi import ApbBus, ApbMaster from cocotbext.axi import AxiStreamBus, AxiStreamSource @@ -92,7 +91,16 @@ class TB(object): await RisingEdge(self.dut.clk) -async def run_test_table_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_table_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -121,7 +129,12 @@ async def run_test_table_write(dut, data_in=None, idle_inserter=None, backpressu await RisingEdge(dut.clk) -async def run_test_table_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_table_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -148,6 +161,11 @@ async def run_test_table_read(dut, data_in=None, idle_inserter=None, backpressur await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_msix(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -272,24 +290,6 @@ async def run_test_msix(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_table_write, - run_test_table_read, - run_test_msix - ]: - - factory = TestFactory(test) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.py b/src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.py index 70bf706..5308fc1 100644 --- a/src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.py +++ b/src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.py @@ -22,7 +22,6 @@ import pytest import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge -from cocotb.regression import TestFactory from cocotbext.axi import AxiLiteBus, AxiLiteMaster from cocotbext.axi import AxiStreamBus, AxiStreamSource @@ -96,7 +95,16 @@ class TB(object): await RisingEdge(self.dut.clk) -async def run_test_table_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_table_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -125,7 +133,12 @@ async def run_test_table_write(dut, data_in=None, idle_inserter=None, backpressu await RisingEdge(dut.clk) -async def run_test_table_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) +async def run_test_table_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -152,6 +165,11 @@ async def run_test_table_read(dut, data_in=None, idle_inserter=None, backpressur await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_msix(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -276,24 +294,6 @@ async def run_test_msix(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_table_write, - run_test_table_read, - run_test_msix - ]: - - factory = TestFactory(test) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) diff --git a/src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.py b/src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.py index a539886..8814c99 100644 --- a/src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.py +++ b/src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.py @@ -20,7 +20,6 @@ import pytest import cocotb from cocotb.triggers import RisingEdge, FallingEdge, Timer -from cocotb.regression import TestFactory from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex @@ -158,6 +157,15 @@ class TB(object): self.stat_err_uncor_asserted = True +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -199,6 +207,11 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -241,6 +254,11 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_io_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -280,6 +298,11 @@ async def run_test_io_write(dut, idle_inserter=None, backpressure_inserter=None) await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_io_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -322,6 +345,11 @@ async def run_test_io_read(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) +@cocotb.test() +@cocotb.parametrize( + ("idle_inserter", [None, cycle_pause]), + ("backpressure_inserter", [None, cycle_pause]), +) async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) @@ -383,26 +411,6 @@ async def run_test_bad_ops(dut, idle_inserter=None, backpressure_inserter=None): await RisingEdge(dut.clk) -def cycle_pause(): - return itertools.cycle([1, 1, 1, 0]) - - -if getattr(cocotb, 'top', None) is not None: - - for test in [ - run_test_write, - run_test_read, - run_test_io_write, - run_test_io_read, - run_test_bad_ops - ]: - - factory = TestFactory(test) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) - factory.generate_tests() - - # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__))