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lss: Rename I2C data ports to reduce ambiguity

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-08-02 14:40:33 -07:00
parent 4620370035
commit 8017534c45
8 changed files with 131 additions and 131 deletions
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4
src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py
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@@ -41,8 +41,8 @@ class TB:
self.cmd_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_cmd), dut.clk, dut.rst)
self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_data), dut.clk, dut.rst)
self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_data), dut.clk, dut.rst)
self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
self.i2c_mem = []

8
src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.sv
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@@ -22,8 +22,8 @@ logic clk;
logic rst;
taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) s_axis_cmd();
taxi_axis_if #(.DATA_W(8)) s_axis_data();
taxi_axis_if #(.DATA_W(8)) m_axis_data();
taxi_axis_if #(.DATA_W(8)) s_axis_tx();
taxi_axis_if #(.DATA_W(8)) m_axis_rx();
logic scl_i;
logic scl_o;
@@ -47,8 +47,8 @@ uut (
* Host interface
*/
.s_axis_cmd(s_axis_cmd),
.s_axis_data(s_axis_data),
.m_axis_data(m_axis_data),
.s_axis_tx(s_axis_tx),
.m_axis_rx(m_axis_rx),
/*
* I2C interface

4
src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py
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@@ -32,8 +32,8 @@ class TB:
cocotb.fork(Clock(dut.clk, 8, units="ns").start())
self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_data), dut.clk, dut.rst)
self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_data), dut.clk, dut.rst)
self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
self.i2c_master = I2cMaster(sda=dut.sda_o, sda_o=dut.sda_i,
scl=dut.scl_o, scl_o=dut.scl_i, speed=4000e3)

8
src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.sv
View File

@@ -27,8 +27,8 @@ logic clk;
logic rst;
logic release_bus;
taxi_axis_if #(.DATA_W(8)) s_axis_data();
taxi_axis_if #(.DATA_W(8)) m_axis_data();
taxi_axis_if #(.DATA_W(8)) s_axis_tx();
taxi_axis_if #(.DATA_W(8)) m_axis_rx();
logic scl_i;
logic scl_o;
@@ -58,8 +58,8 @@ uut (
* Host interface
*/
.release_bus(release_bus),
.s_axis_data(s_axis_data),
.m_axis_data(m_axis_data),
.s_axis_tx(s_axis_tx),
.m_axis_rx(m_axis_rx),
/*
* I2C interface