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lss: Rename I2C data ports to reduce ambiguity

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-08-02 14:40:33 -07:00
parent 4620370035
commit 8017534c45
8 changed files with 131 additions and 131 deletions
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78
src/lss/rtl/taxi_i2c_master.sv
View File

@@ -23,8 +23,8 @@ module taxi_i2c_master (
* Host interface * Host interface
*/ */
taxi_axis_if.snk s_axis_cmd, taxi_axis_if.snk s_axis_cmd,
taxi_axis_if.snk s_axis_data, taxi_axis_if.snk s_axis_tx,
taxi_axis_if.src m_axis_data, taxi_axis_if.src m_axis_rx,
/* /*
* I2C interface * I2C interface
@@ -81,7 +81,7 @@ read
set start to force generation of a start condition set start to force generation of a start condition
start is implied when bus is inactive or active with write or different address start is implied when bus is inactive or active with write or different address
set stop to issue a stop condition after reading current byte set stop to issue a stop condition after reading current byte
if stop is set with read command, then m_axis_data_tlast will be set if stop is set with read command, then m_axis_rx.tlast will be set
write write
write data byte write data byte
@@ -90,7 +90,7 @@ write
set stop to issue a stop condition after writing current byte set stop to issue a stop condition after writing current byte
write multiple write multiple
write multiple data bytes (until s_axis_data_tlast) write multiple data bytes (until s_axis_tx.tlast)
set start to force generation of a start condition set start to force generation of a start condition
start is implied when bus is inactive or active with read or different address start is implied when bus is inactive or active with read or different address
set stop to issue a stop condition after writing block set stop to issue a stop condition after writing block
@@ -213,11 +213,11 @@ logic [3:0] bit_count_reg = '0, bit_count_next;
logic s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next; logic s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next;
logic s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next; logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next;
logic [7:0] m_axis_data_tdata_reg = '0, m_axis_data_tdata_next; logic [7:0] m_axis_rx_tdata_reg = '0, m_axis_rx_tdata_next;
logic m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next;
logic m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next; logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next;
logic scl_i_reg = 1'b1; logic scl_i_reg = 1'b1;
logic sda_i_reg = 1'b1; logic sda_i_reg = 1'b1;
@@ -242,16 +242,16 @@ wire s_axis_cmd_stop = s_axis_cmd.tdata[11];
assign s_axis_cmd.tready = s_axis_cmd_ready_reg; assign s_axis_cmd.tready = s_axis_cmd_ready_reg;
assign s_axis_data.tready = s_axis_data_tready_reg; assign s_axis_tx.tready = s_axis_tx_tready_reg;
assign m_axis_data.tdata = m_axis_data_tdata_reg; assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_data.tkeep = '1; assign m_axis_rx.tkeep = '1;
assign m_axis_data.tstrb = m_axis_data.tkeep; assign m_axis_rx.tstrb = m_axis_rx.tkeep;
assign m_axis_data.tvalid = m_axis_data_tvalid_reg; assign m_axis_rx.tvalid = m_axis_rx_tvalid_reg;
assign m_axis_data.tlast = m_axis_data_tlast_reg; assign m_axis_rx.tlast = m_axis_rx_tlast_reg;
assign m_axis_data.tid = '0; assign m_axis_rx.tid = '0;
assign m_axis_data.tdest = '0; assign m_axis_rx.tdest = '0;
assign m_axis_data.tuser = '0; assign m_axis_rx.tuser = '0;
assign scl_o = scl_o_reg; assign scl_o = scl_o_reg;
assign sda_o = sda_o_reg; assign sda_o = sda_o_reg;
@@ -291,11 +291,11 @@ always_comb begin
s_axis_cmd_ready_next = 1'b0; s_axis_cmd_ready_next = 1'b0;
s_axis_data_tready_next = 1'b0; s_axis_tx_tready_next = 1'b0;
m_axis_data_tdata_next = m_axis_data_tdata_reg; m_axis_rx_tdata_next = m_axis_rx_tdata_reg;
m_axis_data_tvalid_next = m_axis_data_tvalid_reg && !m_axis_data.tready; m_axis_rx_tvalid_next = m_axis_rx_tvalid_reg && !m_axis_rx.tready;
m_axis_data_tlast_next = m_axis_data_tlast_reg; m_axis_rx_tlast_next = m_axis_rx_tlast_reg;
missed_ack_next = 1'b0; missed_ack_next = 1'b0;
@@ -363,7 +363,7 @@ always_comb begin
// address and mode match // address and mode match
// start write // start write
s_axis_data_tready_next = 1'b1; s_axis_tx_tready_next = 1'b1;
state_next = STATE_WRITE_1; state_next = STATE_WRITE_1;
end end
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin
@@ -386,7 +386,7 @@ always_comb begin
end end
STATE_ACTIVE_READ: begin STATE_ACTIVE_READ: begin
// line active to current address // line active to current address
s_axis_cmd_ready_next = !m_axis_data.tvalid; s_axis_cmd_ready_next = !m_axis_rx.tvalid;
if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
// command valid // command valid
@@ -490,19 +490,19 @@ always_comb begin
state_next = STATE_READ; state_next = STATE_READ;
end else begin end else begin
// start write // start write
s_axis_data_tready_next = 1'b1; s_axis_tx_tready_next = 1'b1;
state_next = STATE_WRITE_1; state_next = STATE_WRITE_1;
end end
end end
STATE_WRITE_1: begin STATE_WRITE_1: begin
s_axis_data_tready_next = 1'b1; s_axis_tx_tready_next = 1'b1;
if (s_axis_data.tready && s_axis_data.tvalid) begin if (s_axis_tx.tready && s_axis_tx.tvalid) begin
// got data, start write // got data, start write
data_next = s_axis_data.tdata; data_next = s_axis_tx.tdata;
last_next = s_axis_data.tlast; last_next = s_axis_tx.tlast;
bit_count_next = 4'd8; bit_count_next = 4'd8;
s_axis_data_tready_next = 1'b0; s_axis_tx_tready_next = 1'b0;
state_next = STATE_WRITE_2; state_next = STATE_WRITE_2;
end else begin end else begin
// wait for data // wait for data
@@ -550,12 +550,12 @@ always_comb begin
state_next = STATE_READ; state_next = STATE_READ;
end else begin end else begin
// output data word // output data word
m_axis_data_tdata_next = data_next; m_axis_rx_tdata_next = data_next;
m_axis_data_tvalid_next = 1'b1; m_axis_rx_tvalid_next = 1'b1;
m_axis_data_tlast_next = 1'b0; m_axis_rx_tlast_next = 1'b0;
if (mode_stop_reg) begin if (mode_stop_reg) begin
// send nack and stop // send nack and stop
m_axis_data_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
phy_write_bit = 1'b1; phy_write_bit = 1'b1;
phy_tx_data = 1'b1; phy_tx_data = 1'b1;
state_next = STATE_STOP; state_next = STATE_STOP;
@@ -832,11 +832,11 @@ always_ff @(posedge clk) begin
s_axis_cmd_ready_reg <= s_axis_cmd_ready_next; s_axis_cmd_ready_reg <= s_axis_cmd_ready_next;
s_axis_data_tready_reg <= s_axis_data_tready_next; s_axis_tx_tready_reg <= s_axis_tx_tready_next;
m_axis_data_tdata_reg <= m_axis_data_tdata_next; m_axis_rx_tdata_reg <= m_axis_rx_tdata_next;
m_axis_data_tlast_reg <= m_axis_data_tlast_next; m_axis_rx_tlast_reg <= m_axis_rx_tlast_next;
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; m_axis_rx_tvalid_reg <= m_axis_rx_tvalid_next;
scl_i_reg <= scl_i; scl_i_reg <= scl_i;
sda_i_reg <= sda_i; sda_i_reg <= sda_i;
@@ -867,8 +867,8 @@ always_ff @(posedge clk) begin
delay_scl_reg <= 1'b0; delay_scl_reg <= 1'b0;
delay_sda_reg <= 1'b0; delay_sda_reg <= 1'b0;
s_axis_cmd_ready_reg <= 1'b0; s_axis_cmd_ready_reg <= 1'b0;
s_axis_data_tready_reg <= 1'b0; s_axis_tx_tready_reg <= 1'b0;
m_axis_data_tvalid_reg <= 1'b0; m_axis_rx_tvalid_reg <= 1'b0;
scl_o_reg <= 1'b1; scl_o_reg <= 1'b1;
sda_o_reg <= 1'b1; sda_o_reg <= 1'b1;
busy_reg <= 1'b0; busy_reg <= 1'b0;

78
src/lss/rtl/taxi_i2c_slave.sv
View File

@@ -26,8 +26,8 @@ module taxi_i2c_slave #(
* Host interface * Host interface
*/ */
input wire logic release_bus, input wire logic release_bus,
taxi_axis_if.snk s_axis_data, taxi_axis_if.snk s_axis_tx,
taxi_axis_if.src m_axis_data, taxi_axis_if.src m_axis_rx,
/* /*
* I2C interface * I2C interface
@@ -157,11 +157,11 @@ logic mode_read_reg = 1'b0, mode_read_next;
logic [3:0] bit_count_reg = '0, bit_count_next; logic [3:0] bit_count_reg = '0, bit_count_next;
logic s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next; logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next;
logic [7:0] m_axis_data_tdata_reg = '0, m_axis_data_tdata_next; logic [7:0] m_axis_rx_tdata_reg = '0, m_axis_rx_tdata_next;
logic m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next;
logic m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next; logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next;
logic [FILTER_LEN-1:0] scl_i_filter_reg = '1; logic [FILTER_LEN-1:0] scl_i_filter_reg = '1;
logic [FILTER_LEN-1:0] sda_i_filter_reg = '1; logic [FILTER_LEN-1:0] sda_i_filter_reg = '1;
@@ -181,16 +181,16 @@ logic bus_addressed_reg = 1'b0, bus_addressed_next;
assign bus_address = addr_reg; assign bus_address = addr_reg;
assign s_axis_data.tready = s_axis_data_tready_reg; assign s_axis_tx.tready = s_axis_tx_tready_reg;
assign m_axis_data.tdata = m_axis_data_tdata_reg; assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_data.tkeep = 1'b1; assign m_axis_rx.tkeep = 1'b1;
assign m_axis_data.tstrb = m_axis_data.tkeep; assign m_axis_rx.tstrb = m_axis_rx.tkeep;
assign m_axis_data.tvalid = m_axis_data_tvalid_reg; assign m_axis_rx.tvalid = m_axis_rx_tvalid_reg;
assign m_axis_data.tlast = m_axis_data_tlast_reg; assign m_axis_rx.tlast = m_axis_rx_tlast_reg;
assign m_axis_data.tid = '0; assign m_axis_rx.tid = '0;
assign m_axis_data.tdest = '0; assign m_axis_rx.tdest = '0;
assign m_axis_data.tuser = '0; assign m_axis_rx.tuser = '0;
assign scl_o = scl_o_reg; assign scl_o = scl_o_reg;
assign sda_o = sda_o_reg; assign sda_o = sda_o_reg;
@@ -220,11 +220,11 @@ always_comb begin
bit_count_next = bit_count_reg; bit_count_next = bit_count_reg;
s_axis_data_tready_next = 1'b0; s_axis_tx_tready_next = 1'b0;
m_axis_data_tdata_next = m_axis_data_tdata_reg; m_axis_rx_tdata_next = m_axis_rx_tdata_reg;
m_axis_data_tvalid_next = m_axis_data_tvalid_reg && !m_axis_data.tready; m_axis_rx_tvalid_next = m_axis_rx_tvalid_reg && !m_axis_rx.tready;
m_axis_data_tlast_next = m_axis_data_tlast_reg; m_axis_rx_tlast_next = m_axis_rx_tlast_reg;
scl_o_next = scl_o_reg; scl_o_next = scl_o_reg;
sda_o_next = sda_o_reg; sda_o_next = sda_o_reg;
@@ -239,8 +239,8 @@ always_comb begin
data_valid_next = 1'b0; data_valid_next = 1'b0;
data_out_reg_valid_next = 1'b0; data_out_reg_valid_next = 1'b0;
bit_count_next = 4'd7; bit_count_next = 4'd7;
m_axis_data_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
m_axis_data_tvalid_next = data_out_reg_valid_reg; m_axis_rx_tvalid_next = data_out_reg_valid_reg;
bus_addressed_next = 1'b0; bus_addressed_next = 1'b0;
state_next = STATE_ADDRESS; state_next = STATE_ADDRESS;
end else if (release_bus || stop_bit) begin end else if (release_bus || stop_bit) begin
@@ -250,8 +250,8 @@ always_comb begin
data_valid_next = 1'b0; data_valid_next = 1'b0;
data_out_reg_valid_next = 1'b0; data_out_reg_valid_next = 1'b0;
m_axis_data_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
m_axis_data_tvalid_next = data_out_reg_valid_reg; m_axis_rx_tvalid_next = data_out_reg_valid_reg;
bus_addressed_next = 1'b0; bus_addressed_next = 1'b0;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else begin
@@ -304,7 +304,7 @@ always_comb begin
bit_count_next = 4'd7; bit_count_next = 4'd7;
if (mode_read_reg) begin if (mode_read_reg) begin
// reading // reading
s_axis_data_tready_next = 1'b1; s_axis_tx_tready_next = 1'b1;
data_valid_next = 1'b0; data_valid_next = 1'b0;
state_next = STATE_READ_1; state_next = STATE_READ_1;
end else begin end else begin
@@ -321,7 +321,7 @@ always_comb begin
if (scl_negedge || !scl_o_reg) begin if (scl_negedge || !scl_o_reg) begin
sda_o_next = 1'b1; sda_o_next = 1'b1;
if (m_axis_data.tvalid && !m_axis_data.tready) begin if (m_axis_rx.tvalid && !m_axis_rx.tready) begin
// data waiting in output register, so stretch clock // data waiting in output register, so stretch clock
scl_o_next = 1'b0; scl_o_next = 1'b0;
state_next = STATE_WRITE_1; state_next = STATE_WRITE_1;
@@ -329,8 +329,8 @@ always_comb begin
scl_o_next = 1'b1; scl_o_next = 1'b1;
if (data_valid_reg) begin if (data_valid_reg) begin
// store data in output register // store data in output register
m_axis_data_tdata_next = data_reg; m_axis_rx_tdata_next = data_reg;
m_axis_data_tlast_next = 1'b0; m_axis_rx_tlast_next = 1'b0;
end end
data_valid_next = 1'b0; data_valid_next = 1'b0;
data_out_reg_valid_next = data_valid_reg; data_out_reg_valid_next = data_valid_reg;
@@ -352,7 +352,7 @@ always_comb begin
state_next = STATE_WRITE_2; state_next = STATE_WRITE_2;
end else begin end else begin
// latch out previous data byte since we now know it's not the last one // latch out previous data byte since we now know it's not the last one
m_axis_data_tvalid_next = data_out_reg_valid_reg; m_axis_rx_tvalid_next = data_out_reg_valid_reg;
data_out_reg_valid_next = 1'b0; data_out_reg_valid_next = 1'b0;
data_valid_next = 1'b1; data_valid_next = 1'b1;
state_next = STATE_ACK; state_next = STATE_ACK;
@@ -363,14 +363,14 @@ always_comb begin
end end
STATE_READ_1: begin STATE_READ_1: begin
// read data byte // read data byte
if (s_axis_data.tready && s_axis_data.tvalid) begin if (s_axis_tx.tready && s_axis_tx.tvalid) begin
// data valid; latch it in // data valid; latch it in
s_axis_data_tready_next = 1'b0; s_axis_tx_tready_next = 1'b0;
data_next = s_axis_data.tdata; data_next = s_axis_tx.tdata;
data_valid_next = 1'b1; data_valid_next = 1'b1;
end else begin end else begin
// keep ready high if we're waiting for data // keep ready high if we're waiting for data
s_axis_data_tready_next = !data_valid_reg; s_axis_tx_tready_next = !data_valid_reg;
end end
if (scl_negedge || !scl_o_reg) begin if (scl_negedge || !scl_o_reg) begin
@@ -418,7 +418,7 @@ always_comb begin
end else begin end else begin
// ACK, read another byte // ACK, read another byte
bit_count_next = 4'd7; bit_count_next = 4'd7;
s_axis_data_tready_next = 1'b1; s_axis_tx_tready_next = 1'b1;
data_valid_next = 1'b0; data_valid_next = 1'b0;
state_next = STATE_READ_1; state_next = STATE_READ_1;
end end
@@ -443,11 +443,11 @@ always_ff @(posedge clk) begin
bit_count_reg <= bit_count_next; bit_count_reg <= bit_count_next;
s_axis_data_tready_reg <= s_axis_data_tready_next; s_axis_tx_tready_reg <= s_axis_tx_tready_next;
m_axis_data_tdata_reg <= m_axis_data_tdata_next; m_axis_rx_tdata_reg <= m_axis_rx_tdata_next;
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; m_axis_rx_tvalid_reg <= m_axis_rx_tvalid_next;
m_axis_data_tlast_reg <= m_axis_data_tlast_next; m_axis_rx_tlast_reg <= m_axis_rx_tlast_next;
scl_i_filter_reg <= {scl_i_filter_reg[FILTER_LEN-2:0], scl_i}; scl_i_filter_reg <= {scl_i_filter_reg[FILTER_LEN-2:0], scl_i};
sda_i_filter_reg <= {sda_i_filter_reg[FILTER_LEN-2:0], sda_i}; sda_i_filter_reg <= {sda_i_filter_reg[FILTER_LEN-2:0], sda_i};
@@ -484,8 +484,8 @@ always_ff @(posedge clk) begin
if (rst) begin if (rst) begin
state_reg <= STATE_IDLE; state_reg <= STATE_IDLE;
s_axis_data_tready_reg <= 1'b0; s_axis_tx_tready_reg <= 1'b0;
m_axis_data_tvalid_reg <= 1'b0; m_axis_rx_tvalid_reg <= 1'b0;
scl_o_reg <= 1'b1; scl_o_reg <= 1'b1;
sda_o_reg <= 1'b1; sda_o_reg <= 1'b1;
busy_reg <= 1'b0; busy_reg <= 1'b0;

78
src/lss/rtl/taxi_i2c_slave_axil_master.sv
View File

@@ -206,20 +206,20 @@ logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
logic busy_reg = 1'b0; logic busy_reg = 1'b0;
taxi_axis_if #(.DATA_W(8)) data_in(); taxi_axis_if #(.DATA_W(8)) axis_tx();
taxi_axis_if #(.DATA_W(8)) data_out(); taxi_axis_if #(.DATA_W(8)) axis_rx();
logic [7:0] data_in_reg = '0, data_in_next; logic [7:0] axis_tx_reg = '0, axis_tx_next;
logic data_in_valid_reg = 1'b0, data_in_valid_next; logic axis_tx_valid_reg = 1'b0, axis_tx_valid_next;
assign data_in.tdata = data_in_reg; assign axis_tx.tdata = axis_tx_reg;
assign data_in.tvalid = data_in_valid_reg; assign axis_tx.tvalid = axis_tx_valid_reg;
assign data_in.tlast = 1'b1; assign axis_tx.tlast = 1'b1;
assign data_in.tid = '0; assign axis_tx.tid = '0;
assign data_in.tdest = '0; assign axis_tx.tdest = '0;
assign data_in.tuser = '0; assign axis_tx.tuser = '0;
logic data_out_ready_reg = 1'b0, data_out_ready_next; logic axis_rx_ready_reg = 1'b0, axis_rx_ready_next;
assign data_out.tready = data_out_ready_reg; assign axis_rx.tready = axis_rx_ready_reg;
assign m_axil_wr.awaddr = addr_reg; assign m_axil_wr.awaddr = addr_reg;
assign m_axil_wr.awprot = 3'b010; assign m_axil_wr.awprot = 3'b010;
@@ -241,10 +241,10 @@ always_comb begin
count_next = count_reg; count_next = count_reg;
data_in_next = data_in_reg; axis_tx_next = axis_tx_reg;
data_in_valid_next = data_in_valid_reg && !data_in.tready; axis_tx_valid_next = axis_tx_valid_reg && !axis_tx.tready;
data_out_ready_next = 1'b0; axis_rx_ready_next = 1'b0;
addr_next = addr_reg; addr_next = addr_reg;
data_next = data_reg; data_next = data_reg;
@@ -260,11 +260,11 @@ always_comb begin
STATE_IDLE: begin STATE_IDLE: begin
// idle, wait for I2C interface // idle, wait for I2C interface
if (data_out.tvalid) begin if (axis_rx.tvalid) begin
// store address and write // store address and write
count_next = 8'(ADDR_WORD_W-1); count_next = 8'(ADDR_WORD_W-1);
state_next = STATE_ADDRESS; state_next = STATE_ADDRESS;
end else if (data_in.tready && !data_in_valid_reg) begin end else if (axis_tx.tready && !axis_tx_valid_reg) begin
// read // read
m_axil_arvalid_next = 1'b1; m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b1; m_axil_rready_next = 1'b1;
@@ -273,11 +273,11 @@ always_comb begin
end end
STATE_ADDRESS: begin STATE_ADDRESS: begin
// store address // store address
data_out_ready_next = 1'b1; axis_rx_ready_next = 1'b1;
if (data_out_ready_reg && data_out.tvalid) begin if (axis_rx_ready_reg && axis_rx.tvalid) begin
// store pointers // store pointers
addr_next[8*count_reg +: 8] = data_out.tdata; addr_next[8*count_reg +: 8] = axis_rx.tdata;
count_next = count_reg - 1; count_next = count_reg - 1;
if (count_reg == 0) begin if (count_reg == 0) begin
// end of header // end of header
@@ -289,7 +289,7 @@ always_comb begin
end end
m_axil_wstrb_next = 'd0; m_axil_wstrb_next = 'd0;
data_next = 'd0; data_next = 'd0;
if (data_out.tlast) begin if (axis_rx.tlast) begin
// end of transaction // end of transaction
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else begin
@@ -297,7 +297,7 @@ always_comb begin
state_next = STATE_WRITE_1; state_next = STATE_WRITE_1;
end end
end else begin end else begin
if (data_out.tlast) begin if (axis_rx.tlast) begin
// end of transaction // end of transaction
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else begin
@@ -324,13 +324,13 @@ always_comb begin
end end
STATE_READ_2: begin STATE_READ_2: begin
// send data // send data
if (data_out.tvalid || !bus_addressed) begin if (axis_rx.tvalid || !bus_addressed) begin
// no longer addressed or now addressed for write, return to idle // no longer addressed or now addressed for write, return to idle
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (data_in.tready && !data_in_valid_reg) begin end else if (axis_tx.tready && !axis_tx_valid_reg) begin
// transfer word and update pointers // transfer word and update pointers
data_in_next = data_reg[8*count_reg +: 8]; axis_tx_next = data_reg[8*count_reg +: 8];
data_in_valid_next = 1'b1; axis_tx_valid_next = 1'b1;
count_next = count_reg + 1; count_next = count_reg + 1;
if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1)) begin if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1)) begin
// end of stored data word; return to idle // end of stored data word; return to idle
@@ -345,14 +345,14 @@ always_comb begin
end end
STATE_WRITE_1: begin STATE_WRITE_1: begin
// write data // write data
data_out_ready_next = 1'b1; axis_rx_ready_next = 1'b1;
if (data_out_ready_reg && data_out.tvalid) begin if (axis_rx_ready_reg && axis_rx.tvalid) begin
// store word // store word
data_next[8*count_reg +: 8] = data_out.tdata; data_next[8*count_reg +: 8] = axis_rx.tdata;
count_next = count_reg + 1; count_next = count_reg + 1;
m_axil_wstrb_next[count_reg >> ((BYTE_SIZE/8)-1)] = 1'b1; m_axil_wstrb_next[count_reg >> ((BYTE_SIZE/8)-1)] = 1'b1;
if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1) || data_out.tlast) begin if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1) || axis_rx.tlast) begin
// have full word or at end of block, start write operation // have full word or at end of block, start write operation
count_next = 0; count_next = 0;
m_axil_awvalid_next = 1'b1; m_axil_awvalid_next = 1'b1;
@@ -398,8 +398,8 @@ always_ff @(posedge clk) begin
count_reg <= count_next; count_reg <= count_next;
if (data_out_ready_reg & data_out.tvalid) begin if (axis_rx_ready_reg & axis_rx.tvalid) begin
last_cycle_reg <= data_out.tlast; last_cycle_reg <= axis_rx.tlast;
end end
addr_reg <= addr_next; addr_reg <= addr_next;
@@ -414,15 +414,15 @@ always_ff @(posedge clk) begin
busy_reg <= state_next != STATE_IDLE; busy_reg <= state_next != STATE_IDLE;
data_in_reg <= data_in_next; axis_tx_reg <= axis_tx_next;
data_in_valid_reg <= data_in_valid_next; axis_tx_valid_reg <= axis_tx_valid_next;
data_out_ready_reg <= data_out_ready_next; axis_rx_ready_reg <= axis_rx_ready_next;
if (rst) begin if (rst) begin
state_reg <= STATE_IDLE; state_reg <= STATE_IDLE;
data_in_valid_reg <= 1'b0; axis_tx_valid_reg <= 1'b0;
data_out_ready_reg <= 1'b0; axis_rx_ready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0; m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0; m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0; m_axil_bready_reg <= 1'b0;
@@ -441,8 +441,8 @@ i2c_slave_inst (
// Host interface // Host interface
.release_bus(1'b0), .release_bus(1'b0),
.s_axis_data(data_in), .s_axis_tx(axis_tx),
.m_axis_data(data_out), .m_axis_rx(axis_rx),
// I2C Interface // I2C Interface
.scl_i(i2c_scl_i), .scl_i(i2c_scl_i),

4
src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py
View File

@@ -41,8 +41,8 @@ class TB:
self.cmd_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_cmd), dut.clk, dut.rst) self.cmd_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_cmd), dut.clk, dut.rst)
self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_data), dut.clk, dut.rst) self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_data), dut.clk, dut.rst) self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
self.i2c_mem = [] self.i2c_mem = []

8
src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.sv
View File

@@ -22,8 +22,8 @@ logic clk;
logic rst; logic rst;
taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) s_axis_cmd(); taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) s_axis_cmd();
taxi_axis_if #(.DATA_W(8)) s_axis_data(); taxi_axis_if #(.DATA_W(8)) s_axis_tx();
taxi_axis_if #(.DATA_W(8)) m_axis_data(); taxi_axis_if #(.DATA_W(8)) m_axis_rx();
logic scl_i; logic scl_i;
logic scl_o; logic scl_o;
@@ -47,8 +47,8 @@ uut (
* Host interface * Host interface
*/ */
.s_axis_cmd(s_axis_cmd), .s_axis_cmd(s_axis_cmd),
.s_axis_data(s_axis_data), .s_axis_tx(s_axis_tx),
.m_axis_data(m_axis_data), .m_axis_rx(m_axis_rx),
/* /*
* I2C interface * I2C interface

4
src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py
View File

@@ -32,8 +32,8 @@ class TB:
cocotb.fork(Clock(dut.clk, 8, units="ns").start()) cocotb.fork(Clock(dut.clk, 8, units="ns").start())
self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_data), dut.clk, dut.rst) self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_data), dut.clk, dut.rst) self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
self.i2c_master = I2cMaster(sda=dut.sda_o, sda_o=dut.sda_i, self.i2c_master = I2cMaster(sda=dut.sda_o, sda_o=dut.sda_i,
scl=dut.scl_o, scl_o=dut.scl_i, speed=4000e3) scl=dut.scl_o, scl_o=dut.scl_i, speed=4000e3)

8
src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.sv
View File

@@ -27,8 +27,8 @@ logic clk;
logic rst; logic rst;
logic release_bus; logic release_bus;
taxi_axis_if #(.DATA_W(8)) s_axis_data(); taxi_axis_if #(.DATA_W(8)) s_axis_tx();
taxi_axis_if #(.DATA_W(8)) m_axis_data(); taxi_axis_if #(.DATA_W(8)) m_axis_rx();
logic scl_i; logic scl_i;
logic scl_o; logic scl_o;
@@ -58,8 +58,8 @@ uut (
* Host interface * Host interface
*/ */
.release_bus(release_bus), .release_bus(release_bus),
.s_axis_data(s_axis_data), .s_axis_tx(s_axis_tx),
.m_axis_data(m_axis_data), .m_axis_rx(m_axis_rx),
/* /*
* I2C interface * I2C interface

4
src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv
View File

@@ -784,8 +784,8 @@ i2c_master_inst (
* Host interface * Host interface
*/ */
.s_axis_cmd(i2c_cmd), .s_axis_cmd(i2c_cmd),
.s_axis_data(i2c_wr_data), .s_axis_tx(i2c_wr_data),
.m_axis_data(i2c_rd_data), .m_axis_rx(i2c_rd_data),
/* /*
* I2C interface * I2C interface