From 81a918d2237bff27c460ff1301a0c4d145c62ba1 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sat, 6 Sep 2025 16:50:38 -0700
Subject: [PATCH] apb: Add SV interface for APB

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 README.md                  |  2 ++
 src/apb/rtl/taxi_apb_if.sv | 57 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 src/apb/rtl/taxi_apb_if.sv

diff --git a/README.md b/README.md
index 9ddb736..ab0b7b6 100644
--- a/README.md
+++ b/README.md
@@ -24,6 +24,8 @@ To facilitate the dual-license model, contributions to the project can only be a
 
 ## Components
 
+*  APB
+    *  SV interface for APB
 *  AXI
     *  SV interface for AXI
     *  AXI to AXI lite adapter
diff --git a/src/apb/rtl/taxi_apb_if.sv b/src/apb/rtl/taxi_apb_if.sv
new file mode 100644
index 0000000..1f81c8f
--- /dev/null
+++ b/src/apb/rtl/taxi_apb_if.sv
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+interface taxi_apb_if #(
+    // Width of data bus in bits
+    parameter DATA_W = 32,
+    // Width of address bus in bits
+    parameter ADDR_W = 32,
+    // Width of pstrb (width of data bus in words)
+    parameter STRB_W = (DATA_W/8)
+)
+();
+    logic [ADDR_W-1:0]  paddr;
+    logic [2:0]         pprot;
+    logic               psel;
+    logic               penable;
+    logic               pwrite;
+    logic [DATA_W-1:0]  pwdata;
+    logic [STRB_W-1:0]  pstrb;
+    logic               pready;
+    logic [DATA_W-1:0]  prdata;
+    logic               pslverr;
+
+    modport mst (
+        output paddr,
+        output pprot,
+        output psel,
+        output penable,
+        output pwrite,
+        output pwdata,
+        output pstrb,
+        input  pready,
+        input  prdata,
+        input  pslverr
+    );
+
+    modport slv (
+        input  paddr,
+        input  pprot,
+        input  psel,
+        input  penable,
+        input  pwrite,
+        input  pwdata,
+        input  pstrb,
+        output pready,
+        output prdata,
+        output pslverr
+    );
+
+endinterface