apb: Update APB interconnect to support arbitration between multiple upstream devices

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/apb/rtl/taxi_apb_interconnect.f

@@ -0,0 +1,4 @@
+taxi_apb_interconnect.sv
+taxi_apb_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/apb/rtl/taxi_apb_interconnect.sv

@@ -17,6 +17,8 @@ Authors:
  */
 module taxi_apb_interconnect #
 (
+    // Number of upstream APB interfaces
+    parameter S_CNT = 4,
     // Number of downstream APB interfaces
     parameter M_CNT = 4,
     // Width of address decoder in bits
@@ -31,7 +33,13 @@ module taxi_apb_interconnect #
     // Master interface address widths
     // M_CNT concatenated fields of M_REGIONS concatenated fields of 32 bits
     parameter M_ADDR_W = {M_CNT{{M_REGIONS{32'd24}}}},
-    // Secure master (fail operations based on awprot/arprot)
+    // Read connections between interfaces
+    // M_CNT concatenated fields of S_CNT bits
+    parameter M_CONNECT_RD = {M_CNT{{S_CNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_CNT concatenated fields of S_CNT bits
+    parameter M_CONNECT_WR = {M_CNT{{S_CNT{1'b1}}}},
+    // Secure master (fail operations based on pprot)
     // M_CNT bits
     parameter M_SECURE = {M_CNT{1'b0}}
 )
@@ -42,7 +50,7 @@ module taxi_apb_interconnect #
     /*
      * APB slave interface
      */
-    taxi_apb_if.slv                 s_apb,
+    taxi_apb_if.slv                 s_apb[S_CNT],
 
     /*
      * APB master interface
@@ -51,24 +59,29 @@ module taxi_apb_interconnect #
 );
 
 // extract parameters
-localparam DATA_W = s_apb.DATA_W;
-localparam S_ADDR_W = s_apb.ADDR_W;
-localparam STRB_W = s_apb.STRB_W;
-localparam logic PAUSER_EN = s_apb.PAUSER_EN && m_apb[0].PAUSER_EN;
-localparam PAUSER_W = s_apb.PAUSER_W;
-localparam logic PWUSER_EN = s_apb.PWUSER_EN && m_apb[0].PWUSER_EN;
-localparam PWUSER_W = s_apb.PWUSER_W;
-localparam logic PRUSER_EN = s_apb.PRUSER_EN && m_apb[0].PRUSER_EN;
-localparam PRUSER_W = s_apb.PRUSER_W;
-localparam logic PBUSER_EN = s_apb.PBUSER_EN && m_apb[0].PBUSER_EN;
-localparam PBUSER_W = s_apb.PBUSER_W;
+localparam DATA_W = s_apb[0].DATA_W;
+localparam S_ADDR_W = s_apb[0].ADDR_W;
+localparam STRB_W = s_apb[0].STRB_W;
+localparam logic PAUSER_EN = s_apb[0].PAUSER_EN && m_apb[0].PAUSER_EN;
+localparam PAUSER_W = s_apb[0].PAUSER_W;
+localparam logic PWUSER_EN = s_apb[0].PWUSER_EN && m_apb[0].PWUSER_EN;
+localparam PWUSER_W = s_apb[0].PWUSER_W;
+localparam logic PRUSER_EN = s_apb[0].PRUSER_EN && m_apb[0].PRUSER_EN;
+localparam PRUSER_W = s_apb[0].PRUSER_W;
+localparam logic PBUSER_EN = s_apb[0].PBUSER_EN && m_apb[0].PBUSER_EN;
+localparam PBUSER_W = s_apb[0].PBUSER_W;
 
 localparam APB_M_ADDR_W = m_apb[0].ADDR_W;
 
+localparam CL_S_CNT = $clog2(S_CNT);
+localparam CL_S_CNT_INT = CL_S_CNT > 0 ? CL_S_CNT : 1;
+
 localparam CL_M_CNT = $clog2(M_CNT);
 localparam CL_M_CNT_INT = CL_M_CNT > 0 ? CL_M_CNT : 1;
 
 localparam [M_CNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_CNT-1:0][S_CNT-1:0] M_CONNECT_RD_INT = M_CONNECT_RD;
+localparam [M_CNT-1:0][S_CNT-1:0] M_CONNECT_WR_INT = M_CONNECT_WR;
 localparam [M_CNT-1:0] M_SECURE_INT = M_SECURE;
 
 // default address computation
@@ -98,7 +111,7 @@ endfunction
 localparam [M_CNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_CNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
 
 // check configuration
-if (s_apb.ADDR_W != ADDR_W)
+if (s_apb[0].ADDR_W != ADDR_W)
     $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
 
 if (m_apb[0].DATA_W != DATA_W)
@@ -173,24 +186,44 @@ initial begin
     end
 end
 
-logic [CL_M_CNT_INT-1:0] sel_reg = '0;
-logic act_reg = 1'b0;
+typedef enum logic [1:0] {
+    STATE_IDLE,
+    STATE_DECODE,
+    STATE_READ
+} state_t;
 
-logic s_apb_pready_reg = 1'b0;
-logic [DATA_W-1:0] s_apb_prdata_reg = '0;
-logic s_apb_pslverr_reg = 1'b0;
-logic [PRUSER_W-1:0] s_apb_pruser_reg = '0;
-logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0;
+state_t state_reg = STATE_IDLE, state_next;
 
-logic [ADDR_W-1:0] m_apb_paddr_reg = '0;
-logic [2:0] m_apb_pprot_reg = '0;
-logic [M_CNT-1:0] m_apb_psel_reg = '0;
-logic m_apb_penable_reg = 1'b0;
-logic m_apb_pwrite_reg = 1'b0;
-logic [DATA_W-1:0] m_apb_pwdata_reg = '0;
-logic [STRB_W-1:0] m_apb_pstrb_reg = '0;
-logic [PAUSER_W-1:0] m_apb_pauser_reg = '0;
-logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0;
+logic match;
+
+logic [CL_M_CNT_INT-1:0] m_sel_reg = '0, m_sel_next;
+
+logic [S_CNT-1:0] s_apb_pready_reg = '0, s_apb_pready_next;
+logic [DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
+logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
+logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
+logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
+
+logic [ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
+logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
+logic [M_CNT-1:0] m_apb_psel_reg = '0, m_apb_psel_next;
+logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
+logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
+logic [DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
+logic [STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
+logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
+logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
+
+// unpack interface array
+wire [ADDR_W-1:0] s_apb_paddr[S_CNT];
+wire [2:0] s_apb_pprot[S_CNT];
+wire [S_CNT-1:0] s_apb_psel;
+wire s_apb_penable[S_CNT];
+wire s_apb_pwrite[S_CNT];
+wire [DATA_W-1:0] s_apb_pwdata[S_CNT];
+wire [STRB_W-1:0] s_apb_pstrb[S_CNT];
+wire [PAUSER_W-1:0] s_apb_pauser[S_CNT];
+wire [PWUSER_W-1:0] s_apb_pwuser[S_CNT];
 
 wire [M_CNT-1:0] m_apb_pready;
 wire [DATA_W-1:0] m_apb_prdata[M_CNT];
@@ -198,13 +231,24 @@ wire m_apb_pslverr[M_CNT];
 wire [PRUSER_W-1:0] m_apb_pruser[M_CNT];
 wire [PBUSER_W-1:0] m_apb_pbuser[M_CNT];
 
-assign s_apb.pready = s_apb_pready_reg;
-assign s_apb.prdata = s_apb_prdata_reg;
-assign s_apb.pslverr = s_apb_pslverr_reg;
-assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
-assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+for (genvar n = 0; n < S_CNT; n = n + 1) begin
+    assign s_apb_paddr[n] = s_apb[n].paddr;
+    assign s_apb_pprot[n] = s_apb[n].pprot;
+    assign s_apb_psel[n] = s_apb[n].psel;
+    assign s_apb_penable[n] = s_apb[n].penable;
+    assign s_apb_pwrite[n] = s_apb[n].pwrite;
+    assign s_apb_pwdata[n] = s_apb[n].pwdata;
+    assign s_apb_pstrb[n] = s_apb[n].pstrb;
+    assign s_apb[n].pready = s_apb_pready_reg[n];
+    assign s_apb[n].prdata = s_apb_prdata_reg;
+    assign s_apb[n].pslverr = s_apb_pslverr_reg;
+    assign s_apb_pauser[n] = s_apb[n].pauser;
+    assign s_apb_pwuser[n] = s_apb[n].pwuser;
+    assign s_apb[n].pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
+    assign s_apb[n].pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+end
 
-for (genvar n = 0; n < M_CNT; n += 1) begin
+for (genvar n = 0; n < M_CNT; n = n + 1) begin
     assign m_apb[n].paddr = APB_M_ADDR_W'(m_apb_paddr_reg);
     assign m_apb[n].pprot = m_apb_pprot_reg;
     assign m_apb[n].psel = m_apb_psel_reg[n];
@@ -221,50 +265,195 @@ for (genvar n = 0; n < M_CNT; n += 1) begin
     assign m_apb_pbuser[n] = m_apb[n].pbuser;
 end
 
-always_ff @(posedge clk) begin
-    s_apb_pready_reg <= 1'b0;
-    m_apb_penable_reg <= act_reg && s_apb.penable;
+// slave side mux
+wire [CL_S_CNT_INT-1:0] s_sel;
 
-    s_apb_prdata_reg <= m_apb_prdata[sel_reg];
-    s_apb_pslverr_reg <= m_apb_pslverr[sel_reg] | (m_apb_psel_reg == 0);
-    s_apb_pruser_reg <= m_apb_pruser[sel_reg];
-    s_apb_pbuser_reg <= m_apb_pbuser[sel_reg];
+wire [ADDR_W-1:0]    cur_s_apb_paddr   = s_apb_paddr[s_sel];
+wire [2:0]           cur_s_apb_pprot   = s_apb_pprot[s_sel];
+wire                 cur_s_apb_psel    = s_apb_psel[s_sel];
+wire                 cur_s_apb_penable = s_apb_penable[s_sel];
+wire                 cur_s_apb_pwrite  = s_apb_pwrite[s_sel];
+wire [DATA_W-1:0]    cur_s_apb_pwdata  = s_apb_pwdata[s_sel];
+wire [STRB_W-1:0]    cur_s_apb_pstrb   = s_apb_pstrb[s_sel];
+wire [PAUSER_W-1:0]  cur_s_apb_pauser  = s_apb_pauser[s_sel];
+wire [PWUSER_W-1:0]  cur_s_apb_pwuser  = s_apb_pwuser[s_sel];
 
-    if ((m_apb_psel_reg & ~m_apb_pready) == 0) begin
-        m_apb_psel_reg <= '0;
-        m_apb_penable_reg <= 1'b0;
-        s_apb_pready_reg <= act_reg;
-        act_reg <= 1'b0;
+// master side mux
+wire                 cur_m_apb_pready   = m_apb_pready[m_sel_reg];
+wire [DATA_W-1:0]    cur_m_apb_prdata   = m_apb_prdata[m_sel_reg];
+wire                 cur_m_apb_pslverr  = m_apb_pslverr[m_sel_reg];
+wire [PRUSER_W-1:0]  cur_m_apb_pruser   = m_apb_pruser[m_sel_reg];
+wire [PBUSER_W-1:0]  cur_m_apb_pbuser   = m_apb_pbuser[m_sel_reg];
+
+// arbiter instance
+wire [S_CNT-1:0] req;
+wire [S_CNT-1:0] ack;
+wire [S_CNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_CNT_INT-1:0] grant_index;
+
+assign s_sel = grant_index;
+
+if (S_CNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_CNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
         end
 
-    if (!act_reg) begin
-        m_apb_paddr_reg <= s_apb.paddr;
-        m_apb_pprot_reg <= s_apb.pprot;
-        m_apb_pwrite_reg <= s_apb.pwrite;
-        m_apb_pwdata_reg <= s_apb.pwdata;
-        m_apb_pstrb_reg <= s_apb.pstrb;
-        m_apb_pauser_reg <= s_apb.pauser;
-        m_apb_pwuser_reg <= s_apb.pwuser;
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
 
-        m_apb_psel_reg <= '0;
-        m_apb_penable_reg <= 1'b0;
+    assign grant_valid = grant_valid_reg;
+    assign grant = grant_valid_reg;
+    assign grant_index = '0;
 
-        if (s_apb.psel && !s_apb_pready_reg) begin
-            act_reg <= 1'b1;
+end
+
+// req generation
+assign req = s_apb_psel & ~grant;
+assign ack = s_apb_pready_reg;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_sel_next = m_sel_reg;
+
+    s_apb_pready_next = '0;
+    s_apb_prdata_next = cur_m_apb_prdata;
+    s_apb_pslverr_next = cur_m_apb_pslverr;
+    s_apb_pruser_next = cur_m_apb_pruser;
+    s_apb_pbuser_next = cur_m_apb_pbuser;
+
+    m_apb_paddr_next = cur_s_apb_paddr;
+    m_apb_pprot_next = cur_s_apb_pprot;
+    m_apb_psel_next = '0;
+    m_apb_penable_next = 1'b0;
+    m_apb_pwrite_next = cur_s_apb_pwrite;
+    m_apb_pwdata_next = cur_s_apb_pwdata;
+    m_apb_pstrb_next = cur_s_apb_pstrb;
+    m_apb_pauser_next = cur_s_apb_pauser;
+    m_apb_pwuser_next = cur_s_apb_pwuser;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+            m_apb_paddr_next = cur_s_apb_paddr;
+            m_apb_pprot_next = cur_s_apb_pprot;
+            m_apb_pwrite_next = cur_s_apb_pwrite;
+            m_apb_pwdata_next = cur_s_apb_pwdata;
+            m_apb_pstrb_next = cur_s_apb_pstrb;
+            m_apb_pauser_next = cur_s_apb_pauser;
+            m_apb_pwuser_next = cur_s_apb_pwuser;
+
+            if (grant_valid && s_apb_pready_reg == 0) begin
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
             for (integer i = 0; i < M_CNT; i = i + 1) begin
                 for (integer j = 0; j < M_REGIONS; j = j + 1) begin
-                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_apb.pprot[1]) && (s_apb.paddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
-                        sel_reg <= CL_M_CNT_INT'(i);
-                        m_apb_psel_reg[i] <= 1'b1;
-                    end
-                end
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !m_apb_pprot_reg[1]) && (m_apb_pwrite_reg ? M_CONNECT_WR_INT[i][s_sel] : M_CONNECT_RD_INT[i][s_sel]) && (m_apb_paddr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_sel_next = CL_M_CNT_INT'(i);
+                        match = 1'b1;
                     end
                 end
             end
 
+            s_apb_prdata_next = '0;
+            s_apb_pslverr_next = 1'b1;
+
+            if (match) begin
+                m_apb_psel_next[m_sel_next] = 1'b1;
+                state_next = STATE_READ;
+            end else begin
+                // no match; return decode error
+                s_apb_pready_next[s_sel] = 1'b1;
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_READ: begin
+            // read state; store and forward read response
+            m_apb_psel_next[m_sel_reg] = 1'b1;
+            m_apb_penable_next = 1'b1;
+
+            s_apb_pready_next[s_sel] = cur_m_apb_pready;
+            s_apb_prdata_next = cur_m_apb_prdata;
+            s_apb_pslverr_next = cur_m_apb_pslverr;
+            s_apb_pruser_next = cur_m_apb_pruser;
+            s_apb_pbuser_next = cur_m_apb_pbuser;
+
+            if (cur_m_apb_pready) begin
+                m_apb_psel_next[m_sel_reg] = 1'b0;
+                m_apb_penable_next = 1'b0;
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_READ;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    m_sel_reg <= m_sel_next;
+
+    s_apb_pready_reg <= s_apb_pready_next;
+    s_apb_prdata_reg <= s_apb_prdata_next;
+    s_apb_pslverr_reg <= s_apb_pslverr_next;
+    s_apb_pruser_reg <= s_apb_pruser_next;
+    s_apb_pbuser_reg <= s_apb_pbuser_next;
+
+    m_apb_paddr_reg <= m_apb_paddr_next;
+    m_apb_pprot_reg <= m_apb_pprot_next;
+    m_apb_psel_reg <= m_apb_psel_next;
+    m_apb_penable_reg <= m_apb_penable_next;
+    m_apb_pwrite_reg <= m_apb_pwrite_next;
+    m_apb_pwdata_reg <= m_apb_pwdata_next;
+    m_apb_pstrb_reg <= m_apb_pstrb_next;
+    m_apb_pauser_reg <= m_apb_pauser_next;
+    m_apb_pwuser_reg <= m_apb_pwuser_next;
+
     if (rst) begin
-        act_reg <= 1'b0;
-        s_apb_pready_reg <= 1'b0;
+        state_reg <= STATE_IDLE;
+
+        s_apb_pready_reg <= '0;
+
         m_apb_psel_reg <= '0;
         m_apb_penable_reg <= 1'b0;
     end

src/apb/tb/taxi_apb_interconnect/Makefile

@@ -23,8 +23,7 @@ COCOTB_TOPLEVEL     = test_$(DUT)
 MODULE   = $(COCOTB_TEST_MODULES)
 TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
-VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
-VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
@@ -33,6 +32,7 @@ uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $
 VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 
 # module parameters
+export PARAM_S_CNT := 4
 export PARAM_M_CNT := 4
 export PARAM_DATA_W := 32
 export PARAM_ADDR_W := 32

src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.py

@@ -32,7 +32,10 @@ class TB(object):
 
         cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
 
-        self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst)
+        self.apb_master = [
+            ApbMaster(ApbBus.from_entity(ch), dut.clk, dut.rst)
+            for ch in dut.s_apb
+        ]
         self.apb_ram = [
             ApbRam(ApbBus.from_entity(ch), dut.clk, dut.rst, size=2**16)
             for ch in dut.m_apb
@@ -40,7 +43,8 @@ class TB(object):
 
     def set_idle_generator(self, generator=None):
         if generator:
-            self.apb_master.set_pause_generator(generator())
+            for master in self.apb_master:
+                master.set_pause_generator(generator())
 
     def set_backpressure_generator(self, generator=None):
         if generator:
@@ -60,11 +64,11 @@ class TB(object):
 
 
 async def run_test_write(
-    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
+    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0
 ):
     tb = TB(dut)
 
-    byte_lanes = tb.apb_master.byte_lanes
+    byte_lanes = tb.apb_master[s].byte_lanes
 
     await tb.cycle_reset()
 
@@ -80,7 +84,7 @@ async def run_test_write(
 
             tb.apb_ram[m].write(ram_addr - 128, b"\xaa" * (length + 256))
 
-            await tb.apb_master.write(addr, test_data)
+            await tb.apb_master[s].write(addr, test_data)
 
             tb.log.debug(
                 "%s",
@@ -99,11 +103,11 @@ async def run_test_write(
 
 
 async def run_test_read(
-    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
+    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0
 ):
     tb = TB(dut)
 
-    byte_lanes = tb.apb_master.byte_lanes
+    byte_lanes = tb.apb_master[s].byte_lanes
 
     await tb.cycle_reset()
 
@@ -119,7 +123,7 @@ async def run_test_read(
 
             tb.apb_ram[m].write(ram_addr, test_data)
 
-            data = await tb.apb_master.read(addr, length)
+            data = await tb.apb_master[s].read(addr, length)
 
             assert data.data == test_data
 
@@ -157,7 +161,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
         workers.append(
             cocotb.start_soon(
                 worker(
-                    tb.apb_master,
+                    tb.apb_master[k % len(tb.apb_master)],
                     k * 0x1000,
                     0x1000,
                     count=16,
@@ -177,12 +181,14 @@ def cycle_pause():
 
 
 if getattr(cocotb, "top", None) is not None:
+    s_cnt = len(cocotb.top.s_apb)
     m_cnt = len(cocotb.top.m_apb)
 
     for test in [run_test_write, run_test_read]:
         factory = TestFactory(test)
         factory.add_option("idle_inserter", [None, cycle_pause])
         factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("s", range(min(s_cnt, 2)))
         factory.add_option("m", range(min(m_cnt, 2)))
         factory.generate_tests()
 
@@ -215,15 +221,15 @@ def process_f_files(files):
 
 @pytest.mark.parametrize("data_w", [8, 16, 32])
 @pytest.mark.parametrize("m_cnt", [1, 4])
-def test_taxi_apb_interconnect(request, m_cnt, data_w):
+@pytest.mark.parametrize("s_cnt", [1, 4])
+def test_taxi_apb_interconnect(request, s_cnt, m_cnt, data_w):
     dut = "taxi_apb_interconnect"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = module
 
     verilog_sources = [
         os.path.join(tests_dir, f"{toplevel}.sv"),
-        os.path.join(rtl_dir, f"{dut}.sv"),
-        os.path.join(rtl_dir, "taxi_apb_if.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
     verilog_sources = process_f_files(verilog_sources)
@@ -231,6 +237,7 @@ def test_taxi_apb_interconnect(request, m_cnt, data_w):
     parameters = {}
 
     parameters["M_CNT"] = m_cnt
+    parameters["S_CNT"] = s_cnt
     parameters["DATA_W"] = data_w
     parameters["ADDR_W"] = 32
     parameters["STRB_W"] = parameters["DATA_W"] // 8

src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.sv

@@ -18,6 +18,7 @@ Authors:
 module test_taxi_apb_interconnect #
 (
     /* verilator lint_off WIDTHTRUNC */
+    parameter S_CNT = 4,
     parameter M_CNT = 4,
     parameter DATA_W = 32,
     parameter ADDR_W = 32,
@@ -33,6 +34,8 @@ module test_taxi_apb_interconnect #
     parameter M_REGIONS = 1,
     parameter M_BASE_ADDR = '0,
     parameter M_ADDR_W = {M_CNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_CNT{{S_CNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_CNT{{S_CNT{1'b1}}}},
     parameter M_SECURE = {M_CNT{1'b0}}
     /* verilator lint_on WIDTHTRUNC */
 )
@@ -53,14 +56,17 @@ taxi_apb_if #(
     .PRUSER_W(PRUSER_W),
     .PBUSER_EN(PBUSER_EN),
     .PBUSER_W(PBUSER_W)
-) s_apb(), m_apb[M_CNT]();
+) s_apb[S_CNT](), m_apb[M_CNT]();
 
 taxi_apb_interconnect #(
+    .S_CNT(S_CNT),
     .M_CNT(M_CNT),
     .ADDR_W(ADDR_W),
     .M_REGIONS(M_REGIONS),
     .M_BASE_ADDR(M_BASE_ADDR),
     .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
     .M_SECURE(M_SECURE)
 )
 uut (