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lss: Add I2C slave APB master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -172,6 +172,7 @@ The Taxi transport library contains many smaller components that can be composed
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* I2C master
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* I2C single register
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* I2C slave
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* I2C slave APB master
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* I2C slave AXI lite master
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* MDIO master
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* UART
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4
src/lss/rtl/taxi_i2c_slave_apb_master.f
Normal file
4
src/lss/rtl/taxi_i2c_slave_apb_master.f
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@@ -0,0 +1,4 @@
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taxi_i2c_slave_apb_master.sv
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taxi_i2c_slave.sv
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../lib/taxi/src/axis/rtl/taxi_axis_if.sv
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../lib/taxi/src/apb/rtl/taxi_apb_if.sv
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457
src/lss/rtl/taxi_i2c_slave_apb_master.sv
Normal file
457
src/lss/rtl/taxi_i2c_slave_apb_master.sv
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@@ -0,0 +1,457 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2019-2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* I2C slave APB master wrapper
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*/
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module taxi_i2c_slave_apb_master #
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(
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parameter FILTER_LEN = 4
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* I2C interface
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*/
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input wire logic i2c_scl_i,
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output wire logic i2c_scl_o,
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input wire logic i2c_sda_i,
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output wire logic i2c_sda_o,
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/*
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* APB master interface
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*/
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taxi_apb_if.mst m_apb,
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/*
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* Status
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*/
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output wire logic busy,
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output wire logic [6:0] bus_address,
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output wire logic bus_addressed,
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output wire logic bus_active,
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/*
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* Configuration
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*/
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input wire logic enable,
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input wire logic [6:0] device_address
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);
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/*
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I2C
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Read
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__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
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sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ R \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/
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____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
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scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
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Write
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__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
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sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_W___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/
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____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
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scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
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Operation:
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This module enables I2C control over an APB bus, useful for enabling a design
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to operate as a peripheral to an external microcontroller or similar. The APB
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interface are fully parametrizable, with the restriction that the bus must be
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divided into 2**m words of 8*2**n bits.
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Writing via I2C first accesses an internal address register, followed by the
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actual APB bus. The first k bytes go to the address register, where
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k = ceil(log2(ADDR_W+log2(DATA_W/SELECT_W))/8)
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. The address pointer will automatically increment with reads and writes. For
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buses with word size > 8 bits, the address register is in bytes and unaligned
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writes will be padded with zeros. Writes to the same bus address in the same
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I2C transaction are coalesced and written either once a complete word is ready
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or when the I2C transaction terminates with a stop or repeated start.
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Reading via the I2C interface immediately starts reading from the APB interface
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starting from the current value of the internal address register. Like writes,
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reads are also coalesced when possible. One APB read is performed on the first
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I2C read. Once that has been completely transferred out, another read will be
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performed on the start of the next I2C read operation.
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Read
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_|___|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_| |_|
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ST Device Addr W A Address MSB A Address LSB A RS Device Addr R A Data byte 0 A Data byte N N SP
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Write
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_|___|
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ST Device Addr W A Address MSB A Address LSB A Data byte 0 A Data byte N A SP
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Status:
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busy
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module is communicating over the bus
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bus_control
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module has control of bus in active state
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bus_active
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bus is active, not necessarily controlled by this module
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Parameters:
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device_address
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address of slave device
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Example of interfacing with tristate pins:
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assign scl_i = scl_pin;
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assign scl_pin = scl_o ? 1'bz : 1'b0;
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assign sda_i = sda_pin;
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assign sda_pin = sda_o ? 1'bz : 1'b0;
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Example of two interconnected internal I2C devices:
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assign scl_1_i = scl_1_o & scl_2_o;
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assign scl_2_i = scl_1_o & scl_2_o;
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assign sda_1_i = sda_1_o & sda_2_o;
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assign sda_2_i = sda_1_o & sda_2_o;
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Example of two I2C devices sharing the same pins:
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assign scl_1_i = scl_pin;
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assign scl_2_i = scl_pin;
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assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
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assign sda_1_i = sda_pin;
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assign sda_2_i = sda_pin;
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assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
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Notes:
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scl_o should not be connected directly to scl_i, only via AND logic or a tristate
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I/O pin. This would prevent devices from stretching the clock period.
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*/
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// TODO REMOVE THIS
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/* verilator lint_off WIDTHTRUNC */
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localparam DATA_W = m_apb.DATA_W;
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localparam ADDR_W = m_apb.ADDR_W;
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localparam STRB_W = m_apb.STRB_W;
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// for interfaces that are more than one word wide, disable address lines
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localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
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// width of data port in words
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localparam BYTE_LANES = STRB_W;
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// size of words
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localparam BYTE_SIZE = DATA_W/BYTE_LANES;
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localparam WORD_PART_ADDR_W = $clog2(BYTE_SIZE/8);
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localparam ADDR_W_ADJ = ADDR_W+WORD_PART_ADDR_W;
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localparam ADDR_WORD_W = (ADDR_W_ADJ+7)/8;
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// check configuration
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if (BYTE_LANES * BYTE_SIZE != DATA_W)
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$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
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if (2**$clog2(BYTE_LANES) != BYTE_LANES)
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$fatal(0, "Error: AXI word width must be even power of two (instance %m)");
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if (8*2**$clog2(BYTE_SIZE/8) != BYTE_SIZE)
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$fatal(0, "Error: AXI word size must be a power of two multiple of 8 bits (instance %m)");
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_ADDRESS = 3'd1,
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STATE_READ_1 = 3'd2,
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STATE_READ_2 = 3'd3,
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STATE_WRITE_1 = 3'd4,
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STATE_WRITE_2 = 3'd5;
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logic [2:0] state_reg = STATE_IDLE, state_next;
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logic [7:0] count_reg = '0, count_next;
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logic last_cycle_reg = 1'b0;
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logic [ADDR_W_ADJ-1:0] addr_reg = '0, addr_next;
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logic [DATA_W-1:0] data_reg = '0, data_next;
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logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
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logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
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logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
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logic [STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
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logic busy_reg = 1'b0;
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taxi_axis_if #(.DATA_W(8)) axis_tx();
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taxi_axis_if #(.DATA_W(8)) axis_rx();
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logic [7:0] axis_tx_reg = '0, axis_tx_next;
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logic axis_tx_valid_reg = 1'b0, axis_tx_valid_next;
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assign axis_tx.tdata = axis_tx_reg;
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assign axis_tx.tvalid = axis_tx_valid_reg;
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assign axis_tx.tlast = 1'b1;
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assign axis_tx.tid = '0;
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assign axis_tx.tdest = '0;
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assign axis_tx.tuser = '0;
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logic axis_rx_ready_reg = 1'b0, axis_rx_ready_next;
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assign axis_rx.tready = axis_rx_ready_reg;
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assign m_apb.paddr = addr_reg;
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assign m_apb.pprot = 3'b010;
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assign m_apb.psel = m_apb_psel_reg;
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assign m_apb.penable = m_apb_penable_reg;
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assign m_apb.pwrite = m_apb_pwrite_reg;
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assign m_apb.pwdata = data_reg;
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assign m_apb.pstrb = m_apb_pstrb_reg;
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assign m_apb.pauser = '0;
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assign m_apb.pwuser = '0;
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assign busy = busy_reg;
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always_comb begin
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state_next = STATE_IDLE;
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count_next = count_reg;
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axis_tx_next = axis_tx_reg;
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axis_tx_valid_next = axis_tx_valid_reg && !axis_tx.tready;
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axis_rx_ready_next = 1'b0;
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addr_next = addr_reg;
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data_next = data_reg;
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m_apb_psel_next = 1'b0;
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m_apb_penable_next = 1'b0;
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m_apb_pwrite_next = m_apb_pwrite_reg;
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m_apb_pstrb_next = m_apb_pstrb_reg;
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case (state_reg)
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STATE_IDLE: begin
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// idle, wait for I2C interface
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m_apb_pwrite_next = 1'b0;
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if (axis_rx.tvalid) begin
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// store address and write
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count_next = 8'(ADDR_WORD_W-1);
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state_next = STATE_ADDRESS;
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end else if (axis_tx.tready && !axis_tx_valid_reg) begin
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// read
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m_apb_psel_next = 1'b1;
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state_next = STATE_READ_1;
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end
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end
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STATE_ADDRESS: begin
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// store address
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axis_rx_ready_next = 1'b1;
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if (axis_rx_ready_reg && axis_rx.tvalid) begin
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// store pointers
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addr_next[8*count_reg +: 8] = axis_rx.tdata;
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count_next = count_reg - 1;
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if (count_reg == 0) begin
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// end of header
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// set initial word offset
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if (ADDR_W == VALID_ADDR_W && WORD_PART_ADDR_W == 0) begin
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count_next = '0;
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end else begin
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count_next = 8'(addr_next[ADDR_W_ADJ-VALID_ADDR_W-1:0]);
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end
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m_apb_pstrb_next = '0;
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data_next = '0;
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if (axis_rx.tlast) begin
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// end of transaction
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state_next = STATE_IDLE;
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end else begin
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// start writing
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state_next = STATE_WRITE_1;
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end
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end else begin
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if (axis_rx.tlast) begin
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// end of transaction
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_ADDRESS;
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end
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end
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end else begin
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state_next = STATE_ADDRESS;
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end
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end
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STATE_READ_1: begin
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// wait for data
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m_apb_psel_next = 1'b1;
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m_apb_penable_next = 1'b1;
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m_apb_pwrite_next = 1'b0;
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if (m_apb.psel && m_apb.penable && m_apb.pready) begin
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// read cycle complete, store result
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m_apb_psel_next = 1'b0;
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m_apb_penable_next = 1'b0;
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data_next = m_apb.prdata;
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addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+WORD_PART_ADDR_W));
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state_next = STATE_READ_2;
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end else begin
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state_next = STATE_READ_1;
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end
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end
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STATE_READ_2: begin
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// send data
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if (axis_rx.tvalid || !bus_addressed) begin
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// no longer addressed or now addressed for write, return to idle
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state_next = STATE_IDLE;
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end else if (axis_tx.tready && !axis_tx_valid_reg) begin
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// transfer word and update pointers
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axis_tx_next = data_reg[8*count_reg +: 8];
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axis_tx_valid_next = 1'b1;
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count_next = count_reg + 1;
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if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1)) begin
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// end of stored data word; return to idle
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count_next = 0;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_READ_2;
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end
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end else begin
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state_next = STATE_READ_2;
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end
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end
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STATE_WRITE_1: begin
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// write data
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axis_rx_ready_next = 1'b1;
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m_apb_pwrite_next = 1'b1;
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if (axis_rx_ready_reg && axis_rx.tvalid) begin
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// store word
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data_next[8*count_reg +: 8] = axis_rx.tdata;
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count_next = count_reg + 1;
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m_apb_pstrb_next[count_reg >> ((BYTE_SIZE/8)-1)] = 1'b1;
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if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1) || axis_rx.tlast) begin
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// have full word or at end of block, start write operation
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count_next = 0;
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m_apb_psel_next = 1'b1;
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state_next = STATE_WRITE_2;
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end else begin
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state_next = STATE_WRITE_1;
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end
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end else begin
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state_next = STATE_WRITE_1;
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end
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end
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STATE_WRITE_2: begin
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// wait for write completion
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m_apb_psel_next = 1'b1;
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m_apb_penable_next = 1'b1;
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m_apb_pwrite_next = 1'b1;
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if (m_apb.psel && m_apb.penable && m_apb.pready) begin
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// end of write operation
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data_next = '0;
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addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+WORD_PART_ADDR_W));
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m_apb_psel_next = 1'b0;
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m_apb_penable_next = 1'b0;
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m_apb_pstrb_next = '0;
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if (last_cycle_reg) begin
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// end of transaction
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WRITE_1;
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end
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end else begin
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state_next = STATE_WRITE_2;
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end
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end
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default: begin
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// invalid state - return to idle
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state_next = STATE_IDLE;
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end
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endcase
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end
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always_ff @(posedge clk) begin
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state_reg <= state_next;
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count_reg <= count_next;
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if (axis_rx_ready_reg & axis_rx.tvalid) begin
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last_cycle_reg <= axis_rx.tlast;
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end
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addr_reg <= addr_next;
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data_reg <= data_next;
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m_apb_psel_reg <= m_apb_psel_next;
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m_apb_penable_reg <= m_apb_penable_next;
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m_apb_pwrite_reg <= m_apb_pwrite_next;
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m_apb_pstrb_reg <= m_apb_pstrb_next;
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busy_reg <= state_next != STATE_IDLE;
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|
||||
axis_tx_reg <= axis_tx_next;
|
||||
axis_tx_valid_reg <= axis_tx_valid_next;
|
||||
|
||||
axis_rx_ready_reg <= axis_rx_ready_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
axis_tx_valid_reg <= 1'b0;
|
||||
axis_rx_ready_reg <= 1'b0;
|
||||
m_apb_psel_reg <= 1'b0;
|
||||
m_apb_penable_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
taxi_i2c_slave #(
|
||||
.FILTER_LEN(FILTER_LEN)
|
||||
)
|
||||
i2c_slave_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
// Host interface
|
||||
.release_bus(1'b0),
|
||||
.s_axis_tx(axis_tx),
|
||||
.m_axis_rx(axis_rx),
|
||||
|
||||
// I2C Interface
|
||||
.scl_i(i2c_scl_i),
|
||||
.scl_o(i2c_scl_o),
|
||||
.sda_i(i2c_sda_i),
|
||||
.sda_o(i2c_sda_o),
|
||||
|
||||
// Status
|
||||
.busy(),
|
||||
.bus_address(bus_address),
|
||||
.bus_addressed(bus_addressed),
|
||||
.bus_active(bus_active),
|
||||
|
||||
// Configuration
|
||||
.enable(enable),
|
||||
.device_address(device_address),
|
||||
.device_address_mask(7'h7f)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
52
src/lss/tb/taxi_i2c_slave_apb_master/Makefile
Normal file
52
src/lss/tb/taxi_i2c_slave_apb_master/Makefile
Normal file
@@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ns
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_i2c_slave_apb_master
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_FILTER_LEN := 4
|
||||
export PARAM_APB_DATA_W := 32
|
||||
export PARAM_APB_ADDR_W := 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,186 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import struct
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.i2c import I2cMaster
|
||||
from cocotbext.axi import ApbBus, ApbRam
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
|
||||
|
||||
self.i2c_master = I2cMaster(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
|
||||
scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, speed=4000e3)
|
||||
|
||||
self.apb_ram = ApbRam(ApbBus.from_entity(dut.m_apb), dut.clk, dut.rst, size=2**16)
|
||||
|
||||
dut.enable.setimmediatevalue(1)
|
||||
dut.device_address.setimmediatevalue(0x50)
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.apb_ram.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.apb_ram.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.apb_ram.write(addr-128, b'\xaa'*(length+256))
|
||||
|
||||
await tb.i2c_master.write(0x50, struct.pack('>H', addr)+test_data)
|
||||
await tb.i2c_master.send_stop()
|
||||
|
||||
tb.log.debug("%s", tb.apb_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
assert tb.apb_ram.read(addr, length) == test_data
|
||||
assert tb.apb_ram.read(addr-1, 1) == b'\xaa'
|
||||
assert tb.apb_ram.read(addr+length, 1) == b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.apb_ram.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.apb_ram.write(addr, test_data)
|
||||
|
||||
await tb.i2c_master.write(0x50, struct.pack('>H', addr))
|
||||
data = await tb.i2c_master.read(0x50, length)
|
||||
await tb.i2c_master.send_stop()
|
||||
|
||||
assert data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if getattr(cocotb, 'top', None) is not None:
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_taxi_i2c_slave_apb_master(request):
|
||||
dut = "taxi_i2c_slave_apb_master"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['FILTER_LEN'] = 4
|
||||
parameters['APB_DATA_W'] = 32
|
||||
parameters['APB_ADDR_W'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,93 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* I2C slave APB master testbench
|
||||
*/
|
||||
module test_taxi_i2c_slave_apb_master #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter FILTER_LEN = 4,
|
||||
parameter APB_DATA_W = 32,
|
||||
parameter APB_ADDR_W = 16
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
logic i2c_scl_i;
|
||||
logic i2c_scl_o;
|
||||
logic i2c_sda_i;
|
||||
logic i2c_sda_o;
|
||||
|
||||
taxi_apb_if #(
|
||||
.DATA_W(APB_DATA_W),
|
||||
.ADDR_W(APB_ADDR_W),
|
||||
.PAUSER_EN(0),
|
||||
.PWUSER_EN(0),
|
||||
.PRUSER_EN(0),
|
||||
.PBUSER_EN(0)
|
||||
) m_apb();
|
||||
|
||||
logic busy;
|
||||
logic [6:0] bus_address;
|
||||
logic bus_addressed;
|
||||
logic bus_active;
|
||||
|
||||
logic [15:0] prescale;
|
||||
logic stop_on_idle;
|
||||
|
||||
logic enable;
|
||||
logic [6:0] device_address;
|
||||
|
||||
taxi_i2c_slave_apb_master #(
|
||||
.FILTER_LEN(FILTER_LEN)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* I2C interface
|
||||
*/
|
||||
.i2c_scl_i(i2c_scl_i),
|
||||
.i2c_scl_o(i2c_scl_o),
|
||||
.i2c_sda_i(i2c_sda_i),
|
||||
.i2c_sda_o(i2c_sda_o),
|
||||
|
||||
/*
|
||||
* APB master interface
|
||||
*/
|
||||
.m_apb(m_apb),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.busy(busy),
|
||||
.bus_address(bus_address),
|
||||
.bus_addressed(bus_addressed),
|
||||
.bus_active(bus_active),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.enable(enable),
|
||||
.device_address(device_address)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user