From 86b994779489239738784bc39f42bca61c3f4bd5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 8 Mar 2026 14:43:31 -0700 Subject: [PATCH] stats: Clean up array init Signed-off-by: Alex Forencich --- src/stats/rtl/taxi_stats_collect.sv | 2 +- src/stats/rtl/taxi_stats_counter.sv | 25 +++++------------------- src/stats/rtl/taxi_stats_strings_full.sv | 20 +++---------------- 3 files changed, 9 insertions(+), 38 deletions(-) diff --git a/src/stats/rtl/taxi_stats_collect.sv b/src/stats/rtl/taxi_stats_collect.sv index fe007d5..882cffa 100644 --- a/src/stats/rtl/taxi_stats_collect.sv +++ b/src/stats/rtl/taxi_stats_collect.sv @@ -122,7 +122,7 @@ wire [ACC_W-1:0] acc_int[CNT]; logic [CNT-1:0] acc_clear; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) -logic [STAT_INC_W-1:0] mem_reg[CNT]; +logic [STAT_INC_W-1:0] mem_reg[CNT] = '{default: '0}; logic [STAT_INC_W-1:0] mem_rd_data_reg = '0; diff --git a/src/stats/rtl/taxi_stats_counter.sv b/src/stats/rtl/taxi_stats_counter.sv index 5dc5360..d89bf11 100644 --- a/src/stats/rtl/taxi_stats_counter.sv +++ b/src/stats/rtl/taxi_stats_counter.sv @@ -64,9 +64,9 @@ logic stage_active; logic [PIPELINE-1:0] op_axil_read_pipe_reg = 0, op_axil_read_pipe_next; logic [PIPELINE-1:0] op_acc_pipe_reg = 0, op_acc_pipe_next; -logic [STAT_ID_W-1:0] mem_addr_pipeline_reg[PIPELINE], mem_addr_pipeline_next[PIPELINE]; -logic [WORD_SELECT_W-1:0] axil_shift_pipeline_reg[PIPELINE], axil_shift_pipeline_next[PIPELINE]; -logic [STAT_INC_W-1:0] stat_inc_pipeline_reg[PIPELINE], stat_inc_pipeline_next[PIPELINE]; +logic [STAT_ID_W-1:0] mem_addr_pipeline_reg[PIPELINE] = '{default: '0}, mem_addr_pipeline_next[PIPELINE]; +logic [WORD_SELECT_W-1:0] axil_shift_pipeline_reg[PIPELINE] = '{default: '0}, axil_shift_pipeline_next[PIPELINE]; +logic [STAT_INC_W-1:0] stat_inc_pipeline_reg[PIPELINE] = '{default: '0}, stat_inc_pipeline_next[PIPELINE]; logic s_axis_stat_tready_reg = 1'b0, s_axis_stat_tready_next; @@ -78,14 +78,14 @@ logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next; logic s_axil_rvalid_reg = 0, s_axil_rvalid_next; (* ramstyle = "no_rw_check" *) -logic [STAT_COUNT_W-1:0] mem[2**STAT_ID_W]; +logic [STAT_COUNT_W-1:0] mem[2**STAT_ID_W] = '{default: '0}; logic [STAT_ID_W-1:0] mem_rd_addr; logic [STAT_ID_W-1:0] mem_wr_addr; logic [STAT_COUNT_W-1:0] mem_wr_data; logic mem_wr_en; logic [STAT_COUNT_W-1:0] mem_read_data_reg = 0; -logic [STAT_COUNT_W-1:0] mem_read_data_pipeline_reg[PIPELINE-1:1]; +logic [STAT_COUNT_W-1:0] mem_read_data_pipeline_reg[PIPELINE-1:1] = '{default: '0}; assign s_axis_stat.tready = s_axis_stat_tready_reg; @@ -102,21 +102,6 @@ assign s_axil_rd.rvalid = s_axil_rvalid_reg; wire [STAT_ID_W-1:0] s_axil_araddr_id = STAT_ID_W'(s_axil_rd.araddr >> ID_SHIFT); wire [WORD_SELECT_W-1:0] s_axil_araddr_shift = WORD_SELECT_W'(s_axil_rd.araddr >> WORD_SELECT_SHIFT); -initial begin - // break up loop to work around iteration termination - for (integer i = 0; i < 2**STAT_ID_W; i = i + 2**(STAT_ID_W/2)) begin - for (integer j = i; j < i + 2**(STAT_ID_W/2); j = j + 1) begin - mem[j] = 0; - end - end - - for (integer i = 0; i < PIPELINE; i = i + 1) begin - mem_addr_pipeline_reg[i] = 0; - axil_shift_pipeline_reg[i] = 0; - stat_inc_pipeline_reg[i] = 0; - end -end - always_comb begin init_next = init_reg; init_ptr_next = init_ptr_reg; diff --git a/src/stats/rtl/taxi_stats_strings_full.sv b/src/stats/rtl/taxi_stats_strings_full.sv index 1367eb0..3aed05e 100644 --- a/src/stats/rtl/taxi_stats_strings_full.sv +++ b/src/stats/rtl/taxi_stats_strings_full.sv @@ -61,8 +61,8 @@ logic stage_active; logic [PIPELINE-1:0] op_axil_read_pipe_reg = 0, op_axil_read_pipe_next; -logic [STAT_ID_W-1:0] mem_addr_pipeline_reg[PIPELINE], mem_addr_pipeline_next[PIPELINE]; -logic [WORD_SELECT_W-1:0] axil_shift_pipeline_reg[PIPELINE], axil_shift_pipeline_next[PIPELINE]; +logic [STAT_ID_W-1:0] mem_addr_pipeline_reg[PIPELINE] = '{default: '0}, mem_addr_pipeline_next[PIPELINE]; +logic [WORD_SELECT_W-1:0] axil_shift_pipeline_reg[PIPELINE] = '{default: '0}, axil_shift_pipeline_next[PIPELINE]; logic s_axil_awready_reg = 0, s_axil_awready_next; logic s_axil_wready_reg = 0, s_axil_wready_next; @@ -72,7 +72,7 @@ logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next; logic s_axil_rvalid_reg = 0, s_axil_rvalid_next; (* ramstyle = "no_rw_check" *) -logic [127:0] mem[2**STAT_ID_W]; +logic [127:0] mem[2**STAT_ID_W] = '{default: '0}; logic [STAT_ID_W-1:0] mem_rd_addr; logic [STAT_ID_W-1:0] mem_wr_addr; @@ -95,20 +95,6 @@ assign s_axil_rd.rvalid = s_axil_rvalid_reg; wire [STAT_ID_W-1:0] s_axil_araddr_id = STAT_ID_W'(s_axil_rd.araddr >> ID_SHIFT); wire [WORD_SELECT_W-1:0] s_axil_araddr_shift = WORD_SELECT_W'(s_axil_rd.araddr >> WORD_SELECT_SHIFT); -initial begin - // break up loop to work around iteration termination - for (integer i = 0; i < 2**STAT_ID_W; i = i + 2**(STAT_ID_W/2)) begin - for (integer j = i; j < i + 2**(STAT_ID_W/2); j = j + 1) begin - mem[j] = 0; - end - end - - for (integer i = 0; i < PIPELINE; i = i + 1) begin - mem_addr_pipeline_reg[i] = 0; - axil_shift_pipeline_reg[i] = 0; - end -end - always_comb begin init_next = init_reg; init_ptr_next = init_ptr_reg;