From 879b65cc70c7cd67e006becf4178ddc7dad1b063 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 4 Oct 2025 15:54:49 -0700 Subject: [PATCH] eth: Normalize CRC register naming in 10G RX modules Signed-off-by: Alex Forencich --- src/eth/rtl/taxi_axis_baser_rx_32.sv | 20 ++++++++++---------- src/eth/rtl/taxi_axis_baser_rx_64.sv | 28 ++++++++++++++-------------- src/eth/rtl/taxi_axis_xgmii_rx_32.sv | 20 ++++++++++---------- src/eth/rtl/taxi_axis_xgmii_rx_64.sv | 28 ++++++++++++++-------------- 4 files changed, 48 insertions(+), 48 deletions(-) diff --git a/src/eth/rtl/taxi_axis_baser_rx_32.sv b/src/eth/rtl/taxi_axis_baser_rx_32.sv index 1688ed4..cd7eff9 100644 --- a/src/eth/rtl/taxi_axis_baser_rx_32.sv +++ b/src/eth/rtl/taxi_axis_baser_rx_32.sv @@ -207,17 +207,17 @@ logic stat_rx_err_preamble_reg = 1'b0, stat_rx_err_preamble_next; logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next; -logic [31:0] crc_state = '1; +logic [31:0] crc_state_reg = '1; -wire [31:0] crc_next; +wire [31:0] crc_state_next; wire [3:0] crc_valid; logic [3:0] crc_valid_save; -assign crc_valid[3] = crc_next == ~32'h2144df1c; -assign crc_valid[2] = crc_next == ~32'hc622f71d; -assign crc_valid[1] = crc_next == ~32'hb1c2a1a3; -assign crc_valid[0] = crc_next == ~32'h9d6cdf7e; +assign crc_valid[3] = crc_state_next == ~32'h2144df1c; +assign crc_valid[2] = crc_state_next == ~32'hc622f71d; +assign crc_valid[1] = crc_state_next == ~32'hb1c2a1a3; +assign crc_valid[0] = crc_state_next == ~32'h9d6cdf7e; assign m_axis_rx.tdata = m_axis_rx_tdata_reg; assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg; @@ -263,9 +263,9 @@ taxi_lfsr #( ) eth_crc ( .data_in(input_data_d0), - .state_in(crc_state), + .state_in(crc_state_reg), .data_out(), - .state_out(crc_next) + .state_out(crc_state_next) ); always_comb begin @@ -774,9 +774,9 @@ always_ff @(posedge clk) begin end if (reset_crc) begin - crc_state <= '1; + crc_state_reg <= '1; end else begin - crc_state <= crc_next; + crc_state_reg <= crc_state_next; end crc_valid_save <= crc_valid; diff --git a/src/eth/rtl/taxi_axis_baser_rx_64.sv b/src/eth/rtl/taxi_axis_baser_rx_64.sv index c70fd26..4acec75 100644 --- a/src/eth/rtl/taxi_axis_baser_rx_64.sv +++ b/src/eth/rtl/taxi_axis_baser_rx_64.sv @@ -215,21 +215,21 @@ logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next; logic [PTP_TS_W-1:0] ptp_ts_adj_reg = '0; logic ptp_ts_borrow_reg = '0; -logic [31:0] crc_state = '1; +logic [31:0] crc_state_reg = '1; -wire [31:0] crc_next; +wire [31:0] crc_state_next; wire [7:0] crc_valid; logic [7:0] crc_valid_save; -assign crc_valid[7] = crc_next == ~32'h2144df1c; -assign crc_valid[6] = crc_next == ~32'hc622f71d; -assign crc_valid[5] = crc_next == ~32'hb1c2a1a3; -assign crc_valid[4] = crc_next == ~32'h9d6cdf7e; -assign crc_valid[3] = crc_next == ~32'h6522df69; -assign crc_valid[2] = crc_next == ~32'he60914ae; -assign crc_valid[1] = crc_next == ~32'he38a6876; -assign crc_valid[0] = crc_next == ~32'h6b87b1ec; +assign crc_valid[7] = crc_state_next == ~32'h2144df1c; +assign crc_valid[6] = crc_state_next == ~32'hc622f71d; +assign crc_valid[5] = crc_state_next == ~32'hb1c2a1a3; +assign crc_valid[4] = crc_state_next == ~32'h9d6cdf7e; +assign crc_valid[3] = crc_state_next == ~32'h6522df69; +assign crc_valid[2] = crc_state_next == ~32'he60914ae; +assign crc_valid[1] = crc_state_next == ~32'he38a6876; +assign crc_valid[0] = crc_state_next == ~32'h6b87b1ec; logic [4+16-1:0] last_ts_reg = '0; logic [4+16-1:0] ts_inc_reg = '0; @@ -276,9 +276,9 @@ taxi_lfsr #( ) eth_crc ( .data_in(input_data_d0), - .state_in(crc_state), + .state_in(crc_state_reg), .data_out(), - .state_out(crc_next) + .state_out(crc_state_next) ); // Mask input data @@ -837,9 +837,9 @@ always_ff @(posedge clk) begin input_data_d1 <= input_data_d0; if (reset_crc) begin - crc_state <= '1; + crc_state_reg <= '1; end else begin - crc_state <= crc_next; + crc_state_reg <= crc_state_next; end crc_valid_save <= crc_valid; diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv index 1b33058..513776c 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv @@ -160,17 +160,17 @@ logic stat_rx_err_preamble_reg = 1'b0, stat_rx_err_preamble_next; logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next; -logic [31:0] crc_state = '1; +logic [31:0] crc_state_reg = '1; -wire [31:0] crc_next; +wire [31:0] crc_state_next; wire [3:0] crc_valid; logic [3:0] crc_valid_save; -assign crc_valid[3] = crc_next == ~32'h2144df1c; -assign crc_valid[2] = crc_next == ~32'hc622f71d; -assign crc_valid[1] = crc_next == ~32'hb1c2a1a3; -assign crc_valid[0] = crc_next == ~32'h9d6cdf7e; +assign crc_valid[3] = crc_state_next == ~32'h2144df1c; +assign crc_valid[2] = crc_state_next == ~32'hc622f71d; +assign crc_valid[1] = crc_state_next == ~32'hb1c2a1a3; +assign crc_valid[0] = crc_state_next == ~32'h9d6cdf7e; assign m_axis_rx.tdata = m_axis_rx_tdata_reg; assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg; @@ -216,9 +216,9 @@ taxi_lfsr #( ) eth_crc ( .data_in(xgmii_rxd_d0), - .state_in(crc_state), + .state_in(crc_state_reg), .data_out(), - .state_out(crc_next) + .state_out(crc_state_next) ); always_comb begin @@ -539,9 +539,9 @@ always_ff @(posedge clk) begin term_lane_d0_reg <= term_lane_reg; if (reset_crc) begin - crc_state <= '1; + crc_state_reg <= '1; end else begin - crc_state <= crc_next; + crc_state_reg <= crc_state_next; end crc_valid_save <= crc_valid; diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv index 7d8132f..b724d00 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv @@ -167,21 +167,21 @@ logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next; logic [PTP_TS_W-1:0] ptp_ts_adj_reg = '0; logic ptp_ts_borrow_reg = '0; -logic [31:0] crc_state = '1; +logic [31:0] crc_state_reg = '1; -wire [31:0] crc_next; +wire [31:0] crc_state_next; wire [7:0] crc_valid; logic [7:0] crc_valid_save; -assign crc_valid[7] = crc_next == ~32'h2144df1c; -assign crc_valid[6] = crc_next == ~32'hc622f71d; -assign crc_valid[5] = crc_next == ~32'hb1c2a1a3; -assign crc_valid[4] = crc_next == ~32'h9d6cdf7e; -assign crc_valid[3] = crc_next == ~32'h6522df69; -assign crc_valid[2] = crc_next == ~32'he60914ae; -assign crc_valid[1] = crc_next == ~32'he38a6876; -assign crc_valid[0] = crc_next == ~32'h6b87b1ec; +assign crc_valid[7] = crc_state_next == ~32'h2144df1c; +assign crc_valid[6] = crc_state_next == ~32'hc622f71d; +assign crc_valid[5] = crc_state_next == ~32'hb1c2a1a3; +assign crc_valid[4] = crc_state_next == ~32'h9d6cdf7e; +assign crc_valid[3] = crc_state_next == ~32'h6522df69; +assign crc_valid[2] = crc_state_next == ~32'he60914ae; +assign crc_valid[1] = crc_state_next == ~32'he38a6876; +assign crc_valid[0] = crc_state_next == ~32'h6b87b1ec; logic [4+16-1:0] last_ts_reg = '0; logic [4+16-1:0] ts_inc_reg = '0; @@ -228,9 +228,9 @@ taxi_lfsr #( ) eth_crc ( .data_in(xgmii_rxd_d0), - .state_in(crc_state), + .state_in(crc_state_reg), .data_out(), - .state_out(crc_next) + .state_out(crc_state_next) ); // Mask input data @@ -618,9 +618,9 @@ always_ff @(posedge clk) begin framing_error_d0_reg <= framing_error_reg; if (reset_crc) begin - crc_state <= '1; + crc_state_reg <= '1; end else begin - crc_state <= crc_next; + crc_state_reg <= crc_state_next; end crc_valid_save <= crc_valid;