mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 17:08:38 -08:00
example/ZCU106: Add example design for ZCU106
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
54
example/ZCU106/fpga/tb/fpga_core/Makefile
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54
example/ZCU106/fpga/tb/fpga_core/Makefile
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2020-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = fpga_core
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = $(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += ../../rtl/$(DUT).sv
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VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
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VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
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VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f
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VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
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VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
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VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_SIM := "1'b1"
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export PARAM_VENDOR := "\"XILINX\""
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export PARAM_FAMILY := "\"zynquplus\""
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export PARAM_SFP_RATE := "1'b1"
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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1
example/ZCU106/fpga/tb/fpga_core/baser.py
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1
example/ZCU106/fpga/tb/fpga_core/baser.py
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../../lib/taxi/tb/eth/baser.py
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296
example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
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296
example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
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#!/usr/bin/env python
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# SPDX-License-Identifier: MIT
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"""
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Copyright (c) 2020-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import logging
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import os
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import sys
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import pytest
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import cocotb_test.simulator
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import cocotb
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from cocotb.log import SimLog
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Combine
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from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink
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from cocotbext.eth import XgmiiFrame
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from cocotbext.uart import UartSource, UartSink
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try:
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from baser import BaseRSerdesSource, BaseRSerdesSink
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except ImportError:
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# attempt import from current directory
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sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
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try:
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from baser import BaseRSerdesSource, BaseRSerdesSink
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finally:
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del sys.path[0]
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class TB:
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def __init__(self, dut, speed=1000e6):
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self.dut = dut
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self.log = SimLog("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
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self.sfp_sources = []
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self.sfp_sinks = []
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if dut.SFP_RATE.value == 0:
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cocotb.start_soon(Clock(dut.sfp0_gmii_clk, 8, units="ns").start())
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cocotb.start_soon(Clock(dut.sfp1_gmii_clk, 8, units="ns").start())
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self.sfp_sources.append(GmiiSource(dut.sfp0_gmii_rxd, dut.sfp0_gmii_rx_er, dut.sfp0_gmii_rx_dv,
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dut.sfp0_gmii_clk, dut.sfp0_gmii_rst, dut.sfp0_gmii_clk_en))
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self.sfp_sinks.append(GmiiSink(dut.sfp0_gmii_txd, dut.sfp0_gmii_tx_er, dut.sfp0_gmii_tx_en,
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dut.sfp0_gmii_clk, dut.sfp0_gmii_rst, dut.sfp0_gmii_clk_en))
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self.sfp_sources.append(GmiiSource(dut.sfp1_gmii_rxd, dut.sfp1_gmii_rx_er, dut.sfp1_gmii_rx_dv,
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dut.sfp1_gmii_clk, dut.sfp1_gmii_rst, dut.sfp1_gmii_clk_en))
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self.sfp_sinks.append(GmiiSink(dut.sfp1_gmii_txd, dut.sfp1_gmii_tx_er, dut.sfp1_gmii_tx_en,
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dut.sfp1_gmii_clk, dut.sfp1_gmii_rst, dut.sfp1_gmii_clk_en))
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else:
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cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start())
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for ch in dut.sfp_mac.sfp_mac_inst.ch:
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cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start())
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cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start())
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self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
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self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
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self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1)
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self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1)
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dut.btnu.setimmediatevalue(0)
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dut.btnl.setimmediatevalue(0)
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dut.btnd.setimmediatevalue(0)
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dut.btnr.setimmediatevalue(0)
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dut.btnc.setimmediatevalue(0)
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dut.sw.setimmediatevalue(0)
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dut.uart_rts.setimmediatevalue(0)
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async def init(self):
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self.dut.rst_125mhz.setimmediatevalue(0)
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self.dut.sfp0_gmii_rst.setimmediatevalue(0)
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self.dut.sfp1_gmii_rst.setimmediatevalue(0)
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for k in range(10):
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await RisingEdge(self.dut.clk_125mhz)
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self.dut.rst_125mhz.value = 1
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self.dut.sfp0_gmii_rst.value = 1
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self.dut.sfp1_gmii_rst.value = 1
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for k in range(10):
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await RisingEdge(self.dut.clk_125mhz)
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self.dut.rst_125mhz.value = 0
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self.dut.sfp0_gmii_rst.value = 0
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self.dut.sfp1_gmii_rst.value = 0
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for k in range(10):
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await RisingEdge(self.dut.clk_125mhz)
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async def uart_test(tb, source, sink):
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tb.log.info("Test UART")
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tx_data = b"FPGA Ninja"
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tb.log.info("UART TX: %s", tx_data)
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await source.write(tx_data)
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rx_data = bytearray()
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while len(rx_data) < len(tx_data):
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rx_data.extend(await sink.read())
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tb.log.info("UART RX: %s", rx_data)
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tb.log.info("UART test done")
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async def mac_test(tb, source, sink):
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tb.log.info("Test MAC")
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tb.log.info("Multiple small packets")
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count = 64
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pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
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for p in pkts:
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await source.send(GmiiFrame.from_payload(p))
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for k in range(count):
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rx_frame = await sink.recv()
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tb.log.info("RX frame: %s", rx_frame)
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assert rx_frame.get_payload() == pkts[k]
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assert rx_frame.check_fcs()
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assert rx_frame.error is None
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tb.log.info("Multiple large packets")
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count = 32
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pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
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for p in pkts:
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await source.send(GmiiFrame.from_payload(p))
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for k in range(count):
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rx_frame = await sink.recv()
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tb.log.info("RX frame: %s", rx_frame)
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assert rx_frame.get_payload() == pkts[k]
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assert rx_frame.check_fcs()
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assert rx_frame.error is None
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tb.log.info("MAC test done")
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async def mac_test_25g(tb, source, sink):
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tb.log.info("Test MAC")
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tb.log.info("Multiple small packets")
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count = 64
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pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
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for p in pkts:
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await source.send(XgmiiFrame.from_payload(p))
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for k in range(count):
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rx_frame = await sink.recv()
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tb.log.info("RX frame: %s", rx_frame)
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assert rx_frame.get_payload() == pkts[k]
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assert rx_frame.check_fcs()
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tb.log.info("Multiple large packets")
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count = 32
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pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
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for p in pkts:
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await source.send(XgmiiFrame.from_payload(p))
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for k in range(count):
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rx_frame = await sink.recv()
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tb.log.info("RX frame: %s", rx_frame)
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assert rx_frame.get_payload() == pkts[k]
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assert rx_frame.check_fcs()
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tb.log.info("MAC test done")
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@cocotb.test()
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async def run_test(dut):
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tb = TB(dut)
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await tb.init()
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tests = []
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tb.log.info("Start UART test")
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tests.append(cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink)))
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for k in range(len(tb.sfp_sources)):
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if dut.SFP_RATE.value == 0:
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tb.log.info("Start SFP %d 1G MAC loopback test", k)
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tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
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else:
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tb.log.info("Start SFP %d 10G MAC loopback test", k)
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tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
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await Combine(*tests)
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await RisingEdge(dut.clk_125mhz)
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await RisingEdge(dut.clk_125mhz)
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("sfp_rate", [0, 1])
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def test_fpga_core(request, sfp_rate):
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dut = "fpga_core"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, f"{dut}.sv"),
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os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"),
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os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"),
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os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"),
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os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
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os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
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os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['SIM'] = "1'b1"
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parameters['VENDOR'] = "\"XILINX\""
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parameters['FAMILY'] = "\"zynquplus\""
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parameters['SFP_RATE'] = f"1'b{sfp_rate}"
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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