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cndm: Add PTP support

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-02-14 00:44:42 -08:00
parent eb289eb045
commit 88310fd348
24 changed files with 804 additions and 85 deletions
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4
src/cndm/rtl/cndm_micro_core.f
View File

@@ -12,5 +12,5 @@ cndm_micro_cpl_wr.sv
../lib/taxi/src/axis/rtl/taxi_axis_async_fifo.f
../lib/taxi/src/axis/rtl/taxi_axis_arb_mux.f
../lib/taxi/src/axis/rtl/taxi_axis_demux.sv
../lib/taxi/src/ptp/rtl/taxi_ptp_td_phc.sv
../lib/taxi/src/ptp/rtl/taxi_ptp_td_leaf.sv
../lib/taxi/src/ptp/rtl/taxi_ptp_td_phc_axil.f
../lib/taxi/src/ptp/rtl/taxi_ptp_td_rel2tod.sv

129
src/cndm/rtl/cndm_micro_core.sv
View File

@@ -16,10 +16,11 @@ Authors:
* Corundum-micro core logic
*/
module cndm_micro_core #(
parameter PORTS = 2//,
// parameter logic PTP_TS_EN = 1'b1,
// parameter PTP_CLK_PER_NS_NUM = 512,
// parameter PTP_CLK_PER_NS_DENOM = 165
parameter PORTS = 2,
parameter logic PTP_TS_EN = 1'b1,
parameter logic PTP_TS_FMT_TOD = 1'b0,
parameter PTP_CLK_PER_NS_NUM = 512,
parameter PTP_CLK_PER_NS_DENOM = 165
)
(
input wire logic clk,
@@ -46,19 +47,20 @@ module cndm_micro_core #(
/*
* PTP
*/
// input wire logic ptp_clk = 1'b0,
// input wire logic ptp_rst = 1'b0,
// input wire logic ptp_sample_clk = 1'b0,
// output wire logic ptp_td_sdo,
// output wire logic ptp_pps,
// output wire logic ptp_pps_str,
// output wire logic ptp_sync_locked,
// output wire logic [63:0] ptp_sync_ts_rel,
// output wire logic ptp_sync_ts_rel_step,
// output wire logic [95:0] ptp_sync_ts_tod,
// output wire logic ptp_sync_ts_tod_step,
// output wire logic ptp_sync_pps,
// output wire logic ptp_sync_pps_str,
input wire logic ptp_clk = 1'b0,
input wire logic ptp_rst = 1'b0,
input wire logic ptp_sample_clk = 1'b0,
input wire logic ptp_td_sdi = 1'b0,
output wire logic ptp_td_sdo,
output wire logic ptp_pps,
output wire logic ptp_pps_str,
output wire logic ptp_sync_locked,
output wire logic [63:0] ptp_sync_ts_rel,
output wire logic ptp_sync_ts_rel_step,
output wire logic [95:0] ptp_sync_ts_tod,
output wire logic ptp_sync_ts_tod_step,
output wire logic ptp_sync_pps,
output wire logic ptp_sync_pps_str,
/*
* Ethernet
@@ -84,8 +86,7 @@ localparam RAM_SEG_DATA_W = dma_ram_wr.SEG_DATA_W;
localparam RAM_SEG_BE_W = dma_ram_wr.SEG_BE_W;
localparam RAM_SEL_W = dma_ram_wr.SEL_W;
localparam PORT_OFFSET = 1;
// localparam PORT_OFFSET = PTP_TS_EN ? 2 : 1;
localparam PORT_OFFSET = PTP_TS_EN ? 2 : 1;
taxi_axil_if #(
.DATA_W(s_axil_wr.DATA_W),
@@ -182,8 +183,7 @@ always_ff @(posedge clk) begin
case ({s_axil_ctrl[0].araddr[15:2], 2'b00})
16'h0100: s_axil_rdata_reg <= PORTS; // port count
16'h0104: s_axil_rdata_reg <= 32'h00010000; // port offset
// 16'h0104: s_axil_rdata_reg <= PTP_TS_EN ? 32'h00020000 : 32'h00010000; // port offset
16'h0104: s_axil_rdata_reg <= PTP_TS_EN ? 32'h00020000 : 32'h00010000; // port offset
16'h0108: s_axil_rdata_reg <= 32'h00010000; // port stride
default: begin end
endcase
@@ -199,47 +199,54 @@ always_ff @(posedge clk) begin
end
end
// if (PTP_TS_EN) begin : ptp
if (PTP_TS_EN) begin : ptp
// cndm_micro_ptp #(
// .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
// .PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM)
// )
// ptp_inst (
// .clk(clk),
// .rst(rst),
taxi_ptp_td_phc_axil #(
.PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
.PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM)
)
ptp_inst (
.clk(clk),
.rst(rst),
// /*
// * Control register interface
// */
// .s_axil_wr(s_axil_ctrl[1]),
// .s_axil_rd(s_axil_ctrl[1]),
/*
* Control register interface
*/
.s_axil_wr(s_axil_ctrl[1]),
.s_axil_rd(s_axil_ctrl[1]),
// /*
// * PTP
// */
// .ptp_clk(ptp_clk),
// .ptp_rst(ptp_rst),
// .ptp_sample_clk(ptp_sample_clk),
// .ptp_td_sdo(ptp_td_sdo),
// .ptp_pps(ptp_pps),
// .ptp_pps_str(ptp_pps_str),
// .ptp_sync_locked(ptp_sync_locked),
// .ptp_sync_ts_rel(ptp_sync_ts_rel),
// .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
// .ptp_sync_ts_tod(ptp_sync_ts_tod),
// .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
// .ptp_sync_pps(ptp_sync_pps),
// .ptp_sync_pps_str(ptp_sync_pps_str)
// );
/*
* PTP
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sdo(ptp_td_sdo),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_pps_str(ptp_sync_pps_str)
);
// end else begin : ptp
end else begin : ptp
// assign ptp_td_sdo = 1'b0;
// assign ptp_pps = 1'b0;
// assign ptp_pps_str = 1'b0;
assign ptp_td_sdo = 1'b0;
assign ptp_pps = 1'b0;
assign ptp_pps_str = 1'b0;
assign ptp_sync_locked = 1'b0;
assign ptp_sync_ts_rel = '0;
assign ptp_sync_ts_rel_step = 1'b0;
assign ptp_sync_ts_tod = '0;
assign ptp_sync_ts_tod_step = 1'b0;
assign ptp_sync_pps = 1'b0;
assign ptp_sync_pps_str = 1'b0;
// end
end
taxi_dma_desc_if #(
.SRC_ADDR_W(dma_rd_desc_req.SRC_ADDR_W),
@@ -325,7 +332,8 @@ dma_mux_inst (
for (genvar p = 0; p < PORTS; p = p + 1) begin : port
cndm_micro_port #(
// .PTP_TS_EN(PTP_TS_EN)
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD)
)
port_inst (
.clk(clk),
@@ -349,6 +357,13 @@ for (genvar p = 0; p < PORTS; p = p + 1) begin : port
.irq(irq[p]),
/*
* PTP
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sdo),
/*
* Ethernet
*/

46
src/cndm/rtl/cndm_micro_pcie_us.sv
View File

@@ -23,6 +23,10 @@ module cndm_micro_pcie_us #(
// device family
parameter string FAMILY = "virtexuplus",
parameter PORTS = 2,
parameter logic PTP_TS_EN = 1'b1,
parameter logic PTP_TS_FMT_TOD = 1'b0,
parameter PTP_CLK_PER_NS_NUM = 512,
parameter PTP_CLK_PER_NS_DENOM = 165,
parameter RQ_SEQ_NUM_W = 6,
parameter BAR0_APERTURE = 24
)
@@ -80,6 +84,24 @@ module cndm_micro_pcie_us #(
output wire [7:0] cfg_interrupt_msi_tph_st_tag,
output wire [7:0] cfg_interrupt_msi_function_number,
/*
* PTP
*/
input wire logic ptp_clk = 1'b0,
input wire logic ptp_rst = 1'b0,
input wire logic ptp_sample_clk = 1'b0,
input wire logic ptp_td_sdi = 1'b0,
output wire logic ptp_td_sdo,
output wire logic ptp_pps,
output wire logic ptp_pps_str,
output wire logic ptp_sync_locked,
output wire logic [63:0] ptp_sync_ts_rel,
output wire logic ptp_sync_ts_rel_step,
output wire logic [95:0] ptp_sync_ts_tod,
output wire logic ptp_sync_ts_tod_step,
output wire logic ptp_sync_pps,
output wire logic ptp_sync_pps_str,
/*
* Ethernet
*/
@@ -455,7 +477,11 @@ msi_inst (
);
cndm_micro_core #(
.PORTS(PORTS)
.PORTS(PORTS),
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
.PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM)
)
core_inst (
.clk(pcie_clk),
@@ -479,6 +505,24 @@ core_inst (
.irq(irq),
/*
* PTP
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_td_sdi(ptp_td_sdi),
.ptp_td_sdo(ptp_td_sdo),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_sync_locked(ptp_sync_locked),
.ptp_sync_ts_rel(ptp_sync_ts_rel),
.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
.ptp_sync_ts_tod(ptp_sync_ts_tod),
.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_pps_str(ptp_sync_pps_str),
/*
* Ethernet
*/

34
src/cndm/rtl/cndm_micro_port.sv
View File

@@ -16,7 +16,8 @@ Authors:
* Corundum-micro port module
*/
module cndm_micro_port #(
parameter logic PTP_TS_EN = 1'b1
parameter logic PTP_TS_EN = 1'b1,
parameter logic PTP_TS_FMT_TOD = 1'b0
)
(
input wire logic clk,
@@ -40,6 +41,13 @@ module cndm_micro_port #(
output wire logic irq,
/*
* PTP
*/
input wire logic ptp_clk = 1'b0,
input wire logic ptp_rst = 1'b0,
input wire logic ptp_td_sdi = 1'b0,
/*
* Ethernet
*/
@@ -454,7 +462,7 @@ taxi_axis_if #(
.KEEP_EN(mac_axis_tx_cpl.KEEP_EN),
.KEEP_W(mac_axis_tx_cpl.KEEP_W),
.USER_EN(1),
.USER_W(1)
.USER_W(mac_axis_tx_cpl.USER_W)
)
mac_tx_cpl_int();
@@ -507,12 +515,20 @@ tx_cpl_fifo (
);
cndm_micro_tx #(
.PTP_TS_EN(PTP_TS_EN)
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD)
)
tx_inst (
.clk(clk),
.rst(rst),
/*
* PTP
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sdi),
/*
* DMA
*/
@@ -530,7 +546,7 @@ tx_inst (
taxi_axis_if #(
.DATA_W(mac_axis_rx.DATA_W),
.USER_EN(1),
.USER_W(1)
.USER_W(mac_axis_rx.USER_W)
) mac_rx_int();
taxi_axis_async_fifo #(
@@ -582,12 +598,20 @@ rx_fifo (
);
cndm_micro_rx #(
.PTP_TS_EN(PTP_TS_EN)
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD)
)
rx_inst (
.clk(clk),
.rst(rst),
/*
* PTP
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sdi),
/*
* DMA
*/

96
src/cndm/rtl/cndm_micro_rx.sv
View File

@@ -16,12 +16,20 @@ Authors:
* Corundum-micro receive datapath
*/
module cndm_micro_rx #(
parameter logic PTP_TS_EN = 1'b1
parameter logic PTP_TS_EN = 1'b1,
parameter logic PTP_TS_FMT_TOD = 1'b0
)
(
input wire logic clk,
input wire logic rst,
/*
* PTP
*/
input wire logic ptp_clk = 1'b0,
input wire logic ptp_rst = 1'b0,
input wire logic ptp_td_sdi = 1'b0,
/*
* DMA
*/
@@ -50,7 +58,7 @@ taxi_dma_desc_if #(
.ID_EN(0),
.DEST_EN(0),
.USER_EN(1),
.USER_W(1)
.USER_W(rx_data.USER_W)
) dma_desc();
localparam [2:0]
@@ -65,6 +73,84 @@ logic desc_req_reg = 1'b0;
assign desc_req = desc_req_reg;
wire [95:0] rx_ptp_ts;
wire rx_ptp_ts_valid;
if (PTP_TS_EN) begin
if (PTP_TS_FMT_TOD) begin
assign rx_ptp_ts = dma_desc.sts_user[dma_desc.USER_W-1:1];
assign rx_ptp_ts_valid = dma_desc.sts_valid;
end else begin
taxi_axis_if #(
.DATA_W(48),
.KEEP_EN(0),
.KEEP_W(1),
.STRB_EN(0),
.LAST_EN(0),
.ID_EN(0),
.DEST_EN(0),
.USER_EN(1),
.USER_W(1)
) ptp_ts_rel();
assign ptp_ts_rel.tdata = dma_desc.sts_user[dma_desc.USER_W-1:1];
assign ptp_ts_rel.tuser = dma_desc.sts_user[0];
assign ptp_ts_rel.tvalid = dma_desc.sts_valid;
taxi_axis_if #(
.DATA_W(96),
.KEEP_EN(0),
.KEEP_W(1),
.STRB_EN(0),
.LAST_EN(0),
.ID_EN(0),
.DEST_EN(0),
.USER_EN(1),
.USER_W(1)
) ptp_ts_tod();
assign rx_ptp_ts = ptp_ts_tod.tdata;
assign rx_ptp_ts_valid = ptp_ts_tod.tvalid;
taxi_ptp_td_rel2tod #(
.TS_FNS_W(16),
.TS_REL_NS_W(ptp_ts_rel.DATA_W-16),
.TS_TOD_S_W(48),
.TS_REL_W(ptp_ts_rel.DATA_W),
.TS_TOD_W(96),
.TD_SDI_PIPELINE(2)
)
rel2tod_inst (
.clk(clk),
.rst(rst),
/*
* PTP clock interface
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sdi),
/*
* Timestamp conversion
*/
.s_axis_ts_rel(ptp_ts_rel),
.m_axis_ts_tod(ptp_ts_tod)
);
end
end else begin
assign rx_ptp_ts = '0;
assign rx_ptp_ts_valid = 1'b0;
end
always_ff @(posedge clk) begin
desc_req_reg <= 1'b0;
@@ -104,6 +190,12 @@ always_ff @(posedge clk) begin
axis_cpl.tlast <= 1'b1;
axis_cpl.tvalid <= axis_cpl.tvalid && !axis_cpl.tready;
if (rx_ptp_ts_valid) begin
axis_cpl.tdata[127:112] <= rx_ptp_ts[63:48]; // sec
axis_cpl.tdata[95:64] <= rx_ptp_ts[47:16]; // ns
axis_cpl.tdata[111:96] <= rx_ptp_ts[15:0]; // fns
end
case (state_reg)
STATE_IDLE: begin
dma_desc.req_valid <= 1'b1;

79
src/cndm/rtl/cndm_micro_tx.sv
View File

@@ -16,12 +16,20 @@ Authors:
* Corundum-micro transmit datapath
*/
module cndm_micro_tx #(
parameter logic PTP_TS_EN = 1'b1
parameter logic PTP_TS_EN = 1'b1,
parameter logic PTP_TS_FMT_TOD = 1'b0
)
(
input wire logic clk,
input wire logic rst,
/*
* PTP
*/
input wire logic ptp_clk = 1'b0,
input wire logic ptp_rst = 1'b0,
input wire logic ptp_td_sdi = 1'b0,
/*
* DMA
*/
@@ -66,6 +74,68 @@ logic desc_req_reg = 1'b0;
assign desc_req = desc_req_reg;
wire [95:0] tx_cpl_ptp_ts;
wire tx_cpl_valid;
if (PTP_TS_EN) begin
if (PTP_TS_FMT_TOD) begin
assign tx_cpl_ptp_ts = tx_cpl.tdata;
assign tx_cpl_valid = tx_cpl.tvalid;
end else begin
taxi_axis_if #(
.DATA_W(96),
.KEEP_EN(0),
.KEEP_W(1),
.STRB_EN(0),
.LAST_EN(0),
.ID_EN(0),
.DEST_EN(0),
.USER_EN(1),
.USER_W(1)
) tx_cpl_tod();
assign tx_cpl_ptp_ts = tx_cpl_tod.tdata;
assign tx_cpl_valid = tx_cpl_tod.tvalid;
taxi_ptp_td_rel2tod #(
.TS_FNS_W(16),
.TS_REL_NS_W(tx_cpl.DATA_W-16),
.TS_TOD_S_W(48),
.TS_REL_W(tx_cpl.DATA_W),
.TS_TOD_W(96),
.TD_SDI_PIPELINE(2)
)
rel2tod_inst (
.clk(clk),
.rst(rst),
/*
* PTP clock interface
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_td_sdi(ptp_td_sdi),
/*
* Timestamp conversion
*/
.s_axis_ts_rel(tx_cpl),
.m_axis_ts_tod(tx_cpl_tod)
);
end
end else begin
assign tx_cpl_ptp_ts = '0;
assign tx_cpl_valid = tx_cpl.tvalid;
end
always_ff @(posedge clk) begin
desc_req_reg <= 1'b0;
@@ -118,6 +188,8 @@ always_ff @(posedge clk) begin
dma_desc.req_src_addr <= '0;
dma_desc.req_len <= axis_desc.tdata[47:32];
axis_cpl.tdata[47:32] <= axis_desc.tdata[47:32];
if (axis_desc.tvalid && axis_desc.tready) begin
if (axis_desc.tuser) begin
// failed to read desc
@@ -135,7 +207,10 @@ always_ff @(posedge clk) begin
end
end
STATE_TX_DATA: begin
if (dma_desc.sts_valid) begin
axis_cpl.tdata[127:112] <= tx_cpl_ptp_ts[63:48]; // sec
axis_cpl.tdata[95:64] <= tx_cpl_ptp_ts[47:16]; // ns
axis_cpl.tdata[111:96] <= tx_cpl_ptp_ts[15:0]; // fns
if (tx_cpl_valid) begin
axis_cpl.tvalid <= 1'b1;
state_reg <= STATE_IDLE;
end