cndm: Add PTP support

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/cndm/tb/cndm_micro_pcie_us/Makefile

@@ -39,6 +39,10 @@ export PARAM_SIM := "1'b1"
 export PARAM_VENDOR := "\"XILINX\""
 export PARAM_FAMILY := "\"virtexuplus\""
 export PARAM_PORTS := 2
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_CLK_PER_NS_NUM := 512
+export PARAM_PTP_CLK_PER_NS_DENOM := 165
 export PARAM_MAC_DATA_W := 32
 export PARAM_AXIS_PCIE_DATA_W := 256
 export PARAM_BAR0_APERTURE := 24

src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py

@@ -271,6 +271,10 @@ class TB:
 
         self.dev.functions[0].configure_bar(0, 2**int(dut.uut.axil_ctrl_bar.ADDR_W))
 
+        # PTP
+        cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start())
+        cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
+
         # Ethernet
         self.port_mac = []
 
@@ -291,6 +295,9 @@ class TB:
                 rx_clk=dut.mac_rx_clk[k],
                 rx_rst=dut.mac_rx_rst[k],
                 rx_bus=AxiStreamBus.from_entity(dut.mac_axis_rx[k]),
+                tx_ptp_time=dut.mac_axis_tx[k].tid, # TODO
+                tx_ptp_ts=dut.mac_axis_tx_cpl[k].tdata, # TODO
+                tx_ptp_ts_valid=dut.mac_axis_tx_cpl[k].tvalid, # TODO
                 ifg=12, speed=eth_speed
             )
             self.port_mac.append(mac)
@@ -347,6 +354,8 @@ class TB:
 
     async def init(self):
 
+        self.dut.ptp_rst.setimmediatevalue(0)
+
         for mac in self.port_mac:
             mac.rx.reset.setimmediatevalue(0)
             mac.tx.reset.setimmediatevalue(0)
@@ -357,6 +366,8 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.pcie_clk)
 
+        self.dut.ptp_rst.value = 1
+
         for mac in self.port_mac:
             mac.rx.reset.value = 1
             mac.tx.reset.value = 1
@@ -364,6 +375,8 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.pcie_clk)
 
+        self.dut.ptp_rst.value = 0
+
         for mac in self.port_mac:
             mac.rx.reset.value = 0
             mac.tx.reset.value = 0
@@ -499,6 +512,10 @@ def test_cndm_micro_pcie_us(request, mac_data_w):
     parameters['VENDOR'] = "\"XILINX\""
     parameters['FAMILY'] = "\"virtexuplus\""
     parameters['PORTS'] = 2
+    parameters["PTP_TS_EN"] = 1
+    parameters["PTP_TS_FMT_TOD"] = 0
+    parameters["PTP_CLK_PER_NS_NUM"] = 512
+    parameters["PTP_CLK_PER_NS_DENOM"] = 165
     parameters['MAC_DATA_W'] = mac_data_w
     parameters['AXIS_PCIE_DATA_W'] = 256
     parameters['BAR0_APERTURE'] = 24

src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv

@@ -22,6 +22,10 @@ module test_cndm_micro_pcie_us #
     parameter string VENDOR = "XILINX",
     parameter string FAMILY = "virtexuplus",
     parameter PORTS = 2,
+    parameter logic PTP_TS_EN = 1'b1,
+    parameter logic PTP_TS_FMT_TOD = 1'b0,
+    parameter PTP_CLK_PER_NS_NUM = 512,
+    parameter PTP_CLK_PER_NS_DENOM = 165,
     parameter MAC_DATA_W = 32,
     parameter AXIS_PCIE_DATA_W = 256,
     parameter AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161,
@@ -33,6 +37,8 @@ module test_cndm_micro_pcie_us #
 )
 ();
 
+localparam PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 48;
+
 localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32);
 localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6;
 
@@ -122,6 +128,20 @@ logic [1:0]   cfg_interrupt_msi_tph_type;
 logic [7:0]   cfg_interrupt_msi_tph_st_tag;
 logic [7:0]   cfg_interrupt_msi_function_number;
 
+logic        ptp_rst;
+logic        ptp_clk;
+logic        ptp_sample_clk;
+logic        ptp_td_sdo;
+logic        ptp_pps;
+logic        ptp_pps_str;
+logic        ptp_sync_locked;
+logic [63:0] ptp_sync_ts_rel;
+logic        ptp_sync_ts_rel_step;
+logic [95:0] ptp_sync_ts_tod;
+logic        ptp_sync_ts_tod_step;
+logic        ptp_sync_pps;
+logic        ptp_sync_pps_str;
+
 logic mac_tx_clk[PORTS];
 logic mac_tx_rst[PORTS];
 
@@ -136,7 +156,7 @@ logic mac_rx_clk[PORTS];
 logic mac_rx_rst[PORTS];
 
 taxi_axis_if #(
-    .DATA_W(96),
+    .DATA_W(PTP_TS_W),
     .KEEP_W(1),
     .ID_W(8)
 ) mac_axis_tx_cpl[PORTS]();
@@ -145,7 +165,7 @@ taxi_axis_if #(
     .DATA_W(MAC_DATA_W),
     .ID_W(8),
     .USER_EN(1),
-    .USER_W(1)
+    .USER_W(PTP_TS_W+1)
 ) mac_axis_rx[PORTS]();
 
 cndm_micro_pcie_us #(
@@ -153,6 +173,9 @@ cndm_micro_pcie_us #(
     .VENDOR(VENDOR),
     .FAMILY(FAMILY),
     .PORTS(PORTS),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
+    .PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM),
     .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
     .BAR0_APERTURE(BAR0_APERTURE)
 )
@@ -210,6 +233,23 @@ uut (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * PTP
+     */
+    .ptp_clk(ptp_clk),
+    .ptp_rst(ptp_rst),
+    .ptp_sample_clk(ptp_sample_clk),
+    .ptp_td_sdo(ptp_td_sdo),
+    .ptp_pps(ptp_pps),
+    .ptp_pps_str(ptp_pps_str),
+    .ptp_sync_locked(ptp_sync_locked),
+    .ptp_sync_ts_rel(ptp_sync_ts_rel),
+    .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
+    .ptp_sync_ts_tod(ptp_sync_ts_tod),
+    .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
+    .ptp_sync_pps(ptp_sync_pps),
+    .ptp_sync_pps_str(ptp_sync_pps_str),
+
     /*
      * Ethernet: SFP+
      */