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axi: When tying AXI interfaces, permit widening the ID signals

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-03-15 16:13:08 -07:00
parent 87bc96e3fd
commit 89b47d0659
2 changed files with 10 additions and 5 deletions
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7
src/axi/rtl/taxi_axi_tie_rd.sv
View File

@@ -48,7 +48,10 @@ if (m_axi_rd.DATA_W != DATA_W)
if (m_axi_rd.STRB_W != STRB_W) if (m_axi_rd.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
assign m_axi_rd.arid = s_axi_rd.arid; if (m_axi_rd.ID_W < ID_W)
$fatal(0, "Error: Output ID_W is narrower than input ID_W, cannot discard ID bits (instance %m)");
assign m_axi_rd.arid = m_axi_rd.ID_W'(s_axi_rd.arid);
assign m_axi_rd.araddr = m_axi_wr.ADDR_W'(s_axi_rd.araddr); assign m_axi_rd.araddr = m_axi_wr.ADDR_W'(s_axi_rd.araddr);
assign m_axi_rd.arlen = s_axi_rd.arlen; assign m_axi_rd.arlen = s_axi_rd.arlen;
assign m_axi_rd.arsize = s_axi_rd.arsize; assign m_axi_rd.arsize = s_axi_rd.arsize;
@@ -62,7 +65,7 @@ assign m_axi_rd.aruser = ARUSER_EN ? s_axi_rd.aruser : '0;
assign m_axi_rd.arvalid = s_axi_rd.arvalid; assign m_axi_rd.arvalid = s_axi_rd.arvalid;
assign s_axi_rd.arready = m_axi_rd.arready; assign s_axi_rd.arready = m_axi_rd.arready;
assign s_axi_rd.rid = m_axi_rd.rid; assign s_axi_rd.rid = s_axi_rd.ID_W'(m_axi_rd.rid);
assign s_axi_rd.rdata = m_axi_rd.rdata; assign s_axi_rd.rdata = m_axi_rd.rdata;
assign s_axi_rd.rresp = m_axi_rd.rresp; assign s_axi_rd.rresp = m_axi_rd.rresp;
assign s_axi_rd.rlast = m_axi_rd.rlast; assign s_axi_rd.rlast = m_axi_rd.rlast;

8
src/axi/rtl/taxi_axi_tie_wr.sv
View File

@@ -50,8 +50,10 @@ if (m_axi_wr.DATA_W != DATA_W)
if (m_axi_wr.STRB_W != STRB_W) if (m_axi_wr.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
// bypass AW channel if (m_axi_wr.ID_W < ID_W)
assign m_axi_wr.awid = s_axi_wr.awid; $fatal(0, "Error: Output ID_W is narrower than input ID_W, cannot discard ID bits (instance %m)");
assign m_axi_wr.awid = m_axi_wr.ID_W'(s_axi_wr.awid);
assign m_axi_wr.awaddr = m_axi_wr.ADDR_W'(s_axi_wr.awaddr); assign m_axi_wr.awaddr = m_axi_wr.ADDR_W'(s_axi_wr.awaddr);
assign m_axi_wr.awlen = s_axi_wr.awlen; assign m_axi_wr.awlen = s_axi_wr.awlen;
assign m_axi_wr.awsize = s_axi_wr.awsize; assign m_axi_wr.awsize = s_axi_wr.awsize;
@@ -72,7 +74,7 @@ assign m_axi_wr.wuser = WUSER_EN ? s_axi_wr.wuser : '0;
assign m_axi_wr.wvalid = s_axi_wr.wvalid; assign m_axi_wr.wvalid = s_axi_wr.wvalid;
assign s_axi_wr.wready = m_axi_wr.wready; assign s_axi_wr.wready = m_axi_wr.wready;
assign s_axi_wr.bid = m_axi_wr.bid; assign s_axi_wr.bid = s_axi_wr.ID_W'(m_axi_wr.bid);
assign s_axi_wr.bresp = m_axi_wr.bresp; assign s_axi_wr.bresp = m_axi_wr.bresp;
assign s_axi_wr.buser = BUSER_EN ? m_axi_wr.buser : '0; assign s_axi_wr.buser = BUSER_EN ? m_axi_wr.buser : '0;
assign s_axi_wr.bvalid = m_axi_wr.bvalid; assign s_axi_wr.bvalid = m_axi_wr.bvalid;