diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index b13274b..f3b71a6 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -170,9 +170,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad */ .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py index 68ffc04..1fb82be 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py @@ -77,6 +77,10 @@ class TB: async def mac_test(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index 6f7fe79..07eaf1e 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -330,9 +330,19 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad */ .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py index 6cc71c2..8fb8e31 100644 --- a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -93,6 +93,10 @@ class TB: async def mac_test(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv index 4cbced9..37b7a85 100644 --- a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv @@ -567,9 +567,19 @@ end else begin : sfp_mac */ .xcvr_gtpowergood_out(sfp_gtpowergood), .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py index bc5ae55..5579af0 100644 --- a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py @@ -159,9 +159,13 @@ async def mac_test(tb, source, sink): tb.log.info("MAC test done") -async def mac_test_25g(tb, source, sink): +async def mac_test_10g(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk) + tb.log.info("Multiple small packets") count = 64 @@ -218,7 +222,7 @@ async def run_test(dut): tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) else: tb.log.info("Start SFP %d 10G MAC loopback test", k) - tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) + tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) await Combine(*tests) diff --git a/src/eth/example/KR260/fpga/rtl/fpga_core.sv b/src/eth/example/KR260/fpga/rtl/fpga_core.sv index 3fa9167..7bb878a 100644 --- a/src/eth/example/KR260/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KR260/fpga/rtl/fpga_core.sv @@ -427,9 +427,19 @@ end else begin : sfp_mac */ .xcvr_gtpowergood_out(sfp_gtpowergood), .xcvr_gtrefclk00_in(sfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py index d82875c..7f4b287 100644 --- a/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py @@ -143,9 +143,13 @@ async def mac_test(tb, source, sink): tb.log.info("MAC test done") -async def mac_test_25g(tb, source, sink): +async def mac_test_10g(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk) + tb.log.info("Multiple small packets") count = 64 @@ -205,7 +209,7 @@ async def run_test(dut): tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink))) else: tb.log.info("Start 10G SFP MAC loopback test") - tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_source, tb.sfp_sink))) + tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_source, tb.sfp_sink))) await Combine(*tests) diff --git a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv index 132910b..31bed57 100644 --- a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv @@ -189,9 +189,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad */ .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), .xcvr_gtrefclk00_in(qsfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py index 6d4d6eb..96acf54 100644 --- a/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py @@ -80,6 +80,10 @@ class TB: async def mac_test(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv index 17edf3b..6ad72ee 100644 --- a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv @@ -170,9 +170,19 @@ sfp_mac_inst ( */ .xcvr_gtpowergood_out(sfp_gtpowergood), .xcvr_gtrefclk00_in(sfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py index 3923c22..68f0c80 100644 --- a/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py @@ -77,6 +77,10 @@ class TB: async def mac_test(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv index 34a8794..eecc0a6 100644 --- a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv @@ -379,9 +379,19 @@ qsfp_mac_inst ( */ .xcvr_gtpowergood_out(qsfp_gtpowergood), .xcvr_gtrefclk00_in(qsfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py index 93505b3..5dd219e 100644 --- a/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py @@ -140,6 +140,10 @@ async def mac_test(tb, source, sink): async def mac_test_25g(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv index 09f4e06..ac521fd 100644 --- a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv @@ -575,9 +575,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad */ .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py index 771acdf..8db5d1d 100644 --- a/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py @@ -141,6 +141,10 @@ async def mac_test(tb, source, sink): async def mac_test_25g(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv index fca4e2e..2d629fc 100644 --- a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv +++ b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv @@ -388,9 +388,19 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad */ .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[n]), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[n]), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py index 1cda9a5..290d223 100644 --- a/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py @@ -82,6 +82,10 @@ class TB: async def mac_test(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv index 3ce4ee2..8567061 100644 --- a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv @@ -653,9 +653,19 @@ end else begin : sfp_mac */ .xcvr_gtpowergood_out(sfp_gtpowergood), .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index d448588..d32f138 100644 --- a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -166,9 +166,13 @@ async def mac_test(tb, source, sink): tb.log.info("MAC test done") -async def mac_test_25g(tb, source, sink): +async def mac_test_10g(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 @@ -221,7 +225,7 @@ async def run_test(dut): tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) else: tb.log.info("Start SFP %d 10G MAC loopback test", k) - tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) + tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) await Combine(*tests) diff --git a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv index dadd8d0..231568f 100644 --- a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv @@ -464,9 +464,19 @@ end else begin : sfp_mac */ .xcvr_gtpowergood_out(sfp_gtpowergood), .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py index d4ccfd6..b6fad36 100644 --- a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py @@ -148,9 +148,13 @@ async def mac_test(tb, source, sink): tb.log.info("MAC test done") -async def mac_test_25g(tb, source, sink): +async def mac_test_10g(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 @@ -203,7 +207,7 @@ async def run_test(dut): tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) else: tb.log.info("Start SFP %d 10G MAC loopback test", k) - tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) + tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) await Combine(*tests) diff --git a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv index 273e782..e7a155a 100644 --- a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv @@ -267,9 +267,19 @@ sfp_mac_inst ( */ .xcvr_gtpowergood_out(sfp_gtpowergood), .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py index 3dc9948..1adba08 100644 --- a/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py @@ -87,6 +87,10 @@ class TB: async def mac_test(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv index c9834c1..31b85a6 100644 --- a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv +++ b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv @@ -210,9 +210,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad */ .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), .xcvr_gtrefclk00_in(qsfp_mgt_refclk[CLK]), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_mgt_refclk[CLK]), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py index cf67911..d92ee69 100644 --- a/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py @@ -81,6 +81,10 @@ class TB: async def mac_test(tb, source, sink): tb.log.info("Test MAC") + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + tb.log.info("Multiple small packets") count = 64 diff --git a/src/eth/rtl/us/taxi_eth_mac_25g_us.sv b/src/eth/rtl/us/taxi_eth_mac_25g_us.sv index 93541c7..36ffefb 100644 --- a/src/eth/rtl/us/taxi_eth_mac_25g_us.sv +++ b/src/eth/rtl/us/taxi_eth_mac_25g_us.sv @@ -26,8 +26,25 @@ module taxi_eth_mac_25g_us # // GT type parameter string GT_TYPE = "GTY", + // PLL parameters + parameter logic QPLL0_PD = 1'b0, + parameter logic QPLL1_PD = 1'b1, + parameter logic QPLL0_EXT_CTRL = 1'b0, + parameter logic QPLL1_EXT_CTRL = 1'b0, + // GT parameters + parameter logic [CNT-1:0] GT_TX_PD = '0, + parameter logic [CNT-1:0] GT_TX_QPLL_SEL = '0, parameter logic [CNT-1:0] GT_TX_POLARITY = '0, + parameter logic [CNT-1:0] GT_TX_ELECIDLE = '0, + parameter logic [CNT-1:0] GT_TX_INHIBIT = '0, + parameter logic [CNT-1:0][4:0] GT_TX_DIFFCTRL = '{CNT{5'd16}}, + parameter logic [CNT-1:0][6:0] GT_TX_MAINCURSOR = '{CNT{7'd64}}, + parameter logic [CNT-1:0][4:0] GT_TX_POSTCURSOR = '{CNT{5'd0}}, + parameter logic [CNT-1:0][4:0] GT_TX_PRECURSOR = '{CNT{5'd0}}, + parameter logic [CNT-1:0] GT_RX_PD = '0, + parameter logic [CNT-1:0] GT_RX_QPLL_SEL = '0, + parameter logic [CNT-1:0] GT_RX_LPM_EN = '0, parameter logic [CNT-1:0] GT_RX_POLARITY = '0, // MAC/PHY parameters @@ -59,10 +76,20 @@ module taxi_eth_mac_25g_us # * Common */ output wire logic xcvr_gtpowergood_out, - input wire logic xcvr_gtrefclk00_in, + input wire logic xcvr_gtrefclk00_in = 1'b0, + input wire logic xcvr_qpll0pd_in = 1'b0, + input wire logic xcvr_qpll0reset_in = 1'b0, + input wire logic [2:0] xcvr_qpll0pcierate_in = 3'd0, output wire logic xcvr_qpll0lock_out, output wire logic xcvr_qpll0clk_out, output wire logic xcvr_qpll0refclk_out, + input wire logic xcvr_gtrefclk01_in = 1'b0, + input wire logic xcvr_qpll1pd_in = 1'b0, + input wire logic xcvr_qpll1reset_in = 1'b0, + input wire logic [2:0] xcvr_qpll1pcierate_in = 3'd0, + output wire logic xcvr_qpll1lock_out, + output wire logic xcvr_qpll1clk_out, + output wire logic xcvr_qpll1refclk_out, /* * Serial data @@ -76,12 +103,12 @@ module taxi_eth_mac_25g_us # * MAC clocks */ output wire logic [CNT-1:0] rx_clk, - input wire logic [CNT-1:0] rx_rst_in, + input wire logic [CNT-1:0] rx_rst_in = '0, output wire logic [CNT-1:0] rx_rst_out, output wire logic [CNT-1:0] tx_clk, - input wire logic [CNT-1:0] tx_rst_in, + input wire logic [CNT-1:0] tx_rst_in = '0, output wire logic [CNT-1:0] tx_rst_out, - input wire logic [CNT-1:0] ptp_sample_clk, + input wire logic [CNT-1:0] ptp_sample_clk = '0, /* * Transmit interface (AXI stream) @@ -283,6 +310,9 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch wire ch_qpll0lock_out; wire ch_qpll0clk_out; wire ch_qpll0refclk_out; + wire ch_qpll1lock_out; + wire ch_qpll1clk_out; + wire ch_qpll1refclk_out; if (HAS_COMMON) begin // drive outputs from common @@ -291,6 +321,9 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch assign xcvr_qpll0lock_out = ch_qpll0lock_out; assign xcvr_qpll0clk_out = ch_qpll0clk_out; assign xcvr_qpll0refclk_out = ch_qpll0refclk_out; + assign xcvr_qpll1lock_out = ch_qpll1lock_out; + assign xcvr_qpll1clk_out = ch_qpll1clk_out; + assign xcvr_qpll1refclk_out = ch_qpll1refclk_out; end taxi_eth_mac_25g_us_ch #( @@ -303,8 +336,25 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch // GT type .GT_TYPE(GT_TYPE), + // PLL parameters + .QPLL0_PD(QPLL0_PD), + .QPLL1_PD(QPLL1_PD), + .QPLL0_EXT_CTRL(QPLL0_EXT_CTRL), + .QPLL1_EXT_CTRL(QPLL1_EXT_CTRL), + // GT parameters + .GT_TX_PD(GT_TX_PD[n]), + .GT_TX_QPLL_SEL(GT_TX_QPLL_SEL[n]), .GT_TX_POLARITY(GT_TX_POLARITY[n]), + .GT_TX_ELECIDLE(GT_TX_ELECIDLE[n]), + .GT_TX_INHIBIT(GT_TX_INHIBIT[n]), + .GT_TX_DIFFCTRL(GT_TX_DIFFCTRL[n]), + .GT_TX_MAINCURSOR(GT_TX_MAINCURSOR[n]), + .GT_TX_POSTCURSOR(GT_TX_POSTCURSOR[n]), + .GT_TX_PRECURSOR(GT_TX_PRECURSOR[n]), + .GT_RX_PD(GT_RX_PD[n]), + .GT_RX_QPLL_SEL(GT_RX_QPLL_SEL[n]), + .GT_RX_LPM_EN(GT_RX_LPM_EN[n]), .GT_RX_POLARITY(GT_RX_POLARITY[n]), // MAC/PHY parameters @@ -341,17 +391,29 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch * PLL out */ .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0pd_in(xcvr_qpll0pd_in), + .xcvr_qpll0reset_in(xcvr_qpll0reset_in), + .xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in), .xcvr_qpll0lock_out(ch_qpll0lock_out), .xcvr_qpll0clk_out(ch_qpll0clk_out), .xcvr_qpll0refclk_out(ch_qpll0refclk_out), + .xcvr_gtrefclk01_in(xcvr_gtrefclk01_in), + .xcvr_qpll1pd_in(xcvr_qpll1pd_in), + .xcvr_qpll1reset_in(xcvr_qpll1reset_in), + .xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in), + .xcvr_qpll1lock_out(ch_qpll1lock_out), + .xcvr_qpll1clk_out(ch_qpll1clk_out), + .xcvr_qpll1refclk_out(ch_qpll1refclk_out), /* * PLL in */ .xcvr_qpll0lock_in(xcvr_qpll0lock_out), - .xcvr_qpll0reset_out(), .xcvr_qpll0clk_in(xcvr_qpll0clk_out), .xcvr_qpll0refclk_in(xcvr_qpll0refclk_out), + .xcvr_qpll1lock_in(xcvr_qpll1lock_out), + .xcvr_qpll1clk_in(xcvr_qpll1clk_out), + .xcvr_qpll1refclk_in(xcvr_qpll1refclk_out), /* * Serial data diff --git a/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv b/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv index b753eb7..b9dc322 100644 --- a/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv +++ b/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv @@ -26,8 +26,25 @@ module taxi_eth_mac_25g_us_ch # // GT type parameter string GT_TYPE = "GTY", + // PLL parameters + parameter logic QPLL0_PD = 1'b0, + parameter logic QPLL1_PD = 1'b1, + parameter logic QPLL0_EXT_CTRL = 1'b0, + parameter logic QPLL1_EXT_CTRL = 1'b0, + // GT parameters + parameter logic GT_TX_PD = 1'b0, + parameter logic GT_TX_QPLL_SEL = 1'b0, parameter logic GT_TX_POLARITY = 1'b0, + parameter logic GT_TX_ELECIDLE = 1'b0, + parameter logic GT_TX_INHIBIT = 1'b0, + parameter logic [4:0] GT_TX_DIFFCTRL = 5'd16, + parameter logic [6:0] GT_TX_MAINCURSOR = 7'd64, + parameter logic [4:0] GT_TX_POSTCURSOR = 5'd0, + parameter logic [4:0] GT_TX_PRECURSOR = 5'd0, + parameter logic GT_RX_PD = 1'b0, + parameter logic GT_RX_QPLL_SEL = 1'b0, + parameter logic GT_RX_LPM_EN = 1'b0, parameter logic GT_RX_POLARITY = 1'b0, // MAC/PHY parameters @@ -63,18 +80,30 @@ module taxi_eth_mac_25g_us_ch # /* * PLL out */ - input wire logic xcvr_gtrefclk00_in, + input wire logic xcvr_gtrefclk00_in = 1'b0, + input wire logic xcvr_qpll0pd_in = 1'b0, + input wire logic xcvr_qpll0reset_in = 1'b0, + input wire logic [2:0] xcvr_qpll0pcierate_in = 3'd0, output wire logic xcvr_qpll0lock_out, output wire logic xcvr_qpll0clk_out, output wire logic xcvr_qpll0refclk_out, + input wire logic xcvr_gtrefclk01_in = 1'b0, + input wire logic xcvr_qpll1pd_in = 1'b0, + input wire logic xcvr_qpll1reset_in = 1'b0, + input wire logic [2:0] xcvr_qpll1pcierate_in = 3'd0, + output wire logic xcvr_qpll1lock_out, + output wire logic xcvr_qpll1clk_out, + output wire logic xcvr_qpll1refclk_out, /* * PLL in */ - input wire logic xcvr_qpll0lock_in, - output wire logic xcvr_qpll0reset_out, - input wire logic xcvr_qpll0clk_in, - input wire logic xcvr_qpll0refclk_in, + input wire logic xcvr_qpll0lock_in = 1'b0, + input wire logic xcvr_qpll0clk_in = 1'b0, + input wire logic xcvr_qpll0refclk_in = 1'b0, + input wire logic xcvr_qpll1lock_in = 1'b0, + input wire logic xcvr_qpll1clk_in = 1'b0, + input wire logic xcvr_qpll1refclk_in = 1'b0, /* * Serial data @@ -88,12 +117,12 @@ module taxi_eth_mac_25g_us_ch # * MAC clocks */ output wire logic rx_clk, - input wire logic rx_rst_in, + input wire logic rx_rst_in = 1'b0, output wire logic rx_rst_out, output wire logic tx_clk, - input wire logic tx_rst_in, + input wire logic tx_rst_in = 1'b0, output wire logic tx_rst_out, - input wire logic ptp_sample_clk, + input wire logic ptp_sample_clk = 1'b0, /* * Transmit interface (AXI stream) @@ -261,9 +290,31 @@ taxi_eth_phy_25g_us_gt #( .SIM(SIM), .VENDOR(VENDOR), .FAMILY(FAMILY), + .HAS_COMMON(HAS_COMMON), + + // GT type .GT_TYPE(GT_TYPE), + + // PLL parameters + .QPLL0_PD(QPLL0_PD), + .QPLL1_PD(QPLL1_PD), + .QPLL0_EXT_CTRL(QPLL0_EXT_CTRL), + .QPLL1_EXT_CTRL(QPLL1_EXT_CTRL), + + // GT parameters + .GT_TX_PD(GT_TX_PD), + .GT_TX_QPLL_SEL(GT_TX_QPLL_SEL), .GT_TX_POLARITY(GT_TX_POLARITY), + .GT_TX_ELECIDLE(GT_TX_ELECIDLE), + .GT_TX_INHIBIT(GT_TX_INHIBIT), + .GT_TX_DIFFCTRL(GT_TX_DIFFCTRL), + .GT_TX_MAINCURSOR(GT_TX_MAINCURSOR), + .GT_TX_POSTCURSOR(GT_TX_POSTCURSOR), + .GT_TX_PRECURSOR(GT_TX_PRECURSOR), + .GT_RX_PD(GT_RX_PD), + .GT_RX_QPLL_SEL(GT_RX_QPLL_SEL), + .GT_RX_LPM_EN(GT_RX_LPM_EN), .GT_RX_POLARITY(GT_RX_POLARITY) ) gt_inst ( @@ -279,17 +330,29 @@ gt_inst ( * PLL out */ .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0pd_in(xcvr_qpll0pd_in), + .xcvr_qpll0reset_in(xcvr_qpll0reset_in), + .xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in), .xcvr_qpll0lock_out(xcvr_qpll0lock_out), .xcvr_qpll0clk_out(xcvr_qpll0clk_out), .xcvr_qpll0refclk_out(xcvr_qpll0refclk_out), + .xcvr_gtrefclk01_in(xcvr_gtrefclk01_in), + .xcvr_qpll1pd_in(xcvr_qpll1pd_in), + .xcvr_qpll1reset_in(xcvr_qpll1reset_in), + .xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in), + .xcvr_qpll1lock_out(xcvr_qpll1lock_out), + .xcvr_qpll1clk_out(xcvr_qpll1clk_out), + .xcvr_qpll1refclk_out(xcvr_qpll1refclk_out), /* * PLL in */ .xcvr_qpll0lock_in(xcvr_qpll0lock_in), - .xcvr_qpll0reset_out(xcvr_qpll0reset_out), .xcvr_qpll0clk_in(xcvr_qpll0clk_in), .xcvr_qpll0refclk_in(xcvr_qpll0refclk_in), + .xcvr_qpll1lock_in(xcvr_qpll1lock_in), + .xcvr_qpll1clk_in(xcvr_qpll1clk_in), + .xcvr_qpll1refclk_in(xcvr_qpll1refclk_in), /* * Serial data diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f index 83f7d41..3549bae 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f @@ -1,2 +1,6 @@ taxi_eth_phy_25g_us_gt.sv -../lib/taxi/src/sync/rtl/taxi_sync_reset.sv +../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv +../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv +../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv +../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv +../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv index c9ad090..2279349 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv @@ -26,8 +26,25 @@ module taxi_eth_phy_25g_us_gt # // GT type parameter string GT_TYPE = "GTY", + // PLL parameters + parameter logic QPLL0_PD = 1'b0, + parameter logic QPLL1_PD = 1'b1, + parameter logic QPLL0_EXT_CTRL = 1'b0, + parameter logic QPLL1_EXT_CTRL = 1'b0, + // GT parameters + parameter logic GT_TX_PD = 1'b0, + parameter logic GT_TX_QPLL_SEL = 1'b0, parameter logic GT_TX_POLARITY = 1'b0, + parameter logic GT_TX_ELECIDLE = 1'b0, + parameter logic GT_TX_INHIBIT = 1'b0, + parameter logic [4:0] GT_TX_DIFFCTRL = 5'd16, + parameter logic [6:0] GT_TX_MAINCURSOR = 7'd64, + parameter logic [4:0] GT_TX_POSTCURSOR = 5'd0, + parameter logic [4:0] GT_TX_PRECURSOR = 5'd0, + parameter logic GT_RX_PD = 1'b0, + parameter logic GT_RX_QPLL_SEL = 1'b0, + parameter logic GT_RX_LPM_EN = 1'b0, parameter logic GT_RX_POLARITY = 1'b0 ) ( @@ -42,18 +59,30 @@ module taxi_eth_phy_25g_us_gt # /* * PLL out */ - input wire logic xcvr_gtrefclk00_in, + input wire logic xcvr_gtrefclk00_in = 1'b0, + input wire logic xcvr_qpll0pd_in = 1'b0, + input wire logic xcvr_qpll0reset_in = 1'b0, + input wire logic [2:0] xcvr_qpll0pcierate_in = 3'd0, output wire logic xcvr_qpll0lock_out, output wire logic xcvr_qpll0clk_out, output wire logic xcvr_qpll0refclk_out, + input wire logic xcvr_gtrefclk01_in = 1'b0, + input wire logic xcvr_qpll1pd_in = 1'b0, + input wire logic xcvr_qpll1reset_in = 1'b0, + input wire logic [2:0] xcvr_qpll1pcierate_in = 3'd0, + output wire logic xcvr_qpll1lock_out, + output wire logic xcvr_qpll1clk_out, + output wire logic xcvr_qpll1refclk_out, /* * PLL in */ - input wire logic xcvr_qpll0lock_in, - output wire logic xcvr_qpll0reset_out, - input wire logic xcvr_qpll0clk_in, - input wire logic xcvr_qpll0refclk_in, + input wire logic xcvr_qpll0lock_in = 1'b0, + input wire logic xcvr_qpll0clk_in = 1'b0, + input wire logic xcvr_qpll0refclk_in = 1'b0, + input wire logic xcvr_qpll1lock_in = 1'b0, + input wire logic xcvr_qpll1clk_in = 1'b0, + input wire logic xcvr_qpll1refclk_in = 1'b0, /* * Serial data @@ -67,10 +96,10 @@ module taxi_eth_phy_25g_us_gt # * GT user clocks */ output wire logic rx_clk, - input wire logic rx_rst_in, + input wire logic rx_rst_in = 1'b0, output wire logic rx_rst_out, output wire logic tx_clk, - input wire logic tx_rst_in, + input wire logic tx_rst_in = 1'b0, output wire logic tx_rst_out, /* @@ -88,41 +117,252 @@ module taxi_eth_phy_25g_us_gt # localparam GT_USP = FAMILY == "kintexuplus" || FAMILY == "virtexuplus" || FAMILY == "virtexuplusHBM" || FAMILY == "virtexuplus58G" || FAMILY == "zynquplus" || FAMILY == "zynquplusRFSOC"; -wire gt_reset_tx_datapath = tx_rst_in; -wire gt_reset_rx_datapath = rx_rst_in; +wire xcvr_ctrl_rst_sync; -wire gt_reset_tx_done; -wire gt_reset_rx_done; +taxi_sync_reset #( + .N(4) +) +reset_sync_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst), + .out(xcvr_ctrl_rst_sync) +); + +wire gt_qpll0_pd; +wire gt_qpll0_reset; +wire gt_qpll1_pd; +wire gt_qpll1_reset; + +wire qpll0_lock; +wire qpll1_lock; + +if (HAS_COMMON) begin : common_ctrl + + taxi_gt_qpll_reset #( + .QPLL_PD(QPLL0_PD), + .CNT_W(8) + ) + qpll0_reset_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst_sync), + + /* + * GT + */ + .gt_qpll_reset_out(gt_qpll0_reset), + .gt_qpll_pd_out(gt_qpll0_pd), + .gt_qpll_lock_in(xcvr_qpll0lock_out), + + /* + * Control/status + */ + .qpll_reset_in(1'b0), + .qpll_pd_in(QPLL0_PD), + .qpll_lock_out(qpll0_lock) + ); + + taxi_gt_qpll_reset #( + .QPLL_PD(QPLL1_PD), + .CNT_W(8) + ) + qpll1_reset_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst_sync), + + /* + * GT + */ + .gt_qpll_reset_out(gt_qpll1_reset), + .gt_qpll_pd_out(gt_qpll1_pd), + .gt_qpll_lock_in(xcvr_qpll1lock_out), + + /* + * Control/status + */ + .qpll_reset_in(1'b0), + .qpll_pd_in(QPLL1_PD), + .qpll_lock_out(qpll1_lock) + ); + +end else begin : common_ctrl + + assign gt_qpll0_pd = 1'b1; + assign gt_qpll0_reset = 1'b1; + assign gt_qpll1_pd = 1'b1; + assign gt_qpll1_reset = 1'b1; + + taxi_sync_signal #( + .WIDTH(2), + .N(2) + ) + qpll_lock_sync_inst ( + .clk(xcvr_ctrl_clk), + .in({xcvr_qpll1lock_in, xcvr_qpll0lock_in}), + .out({qpll1_lock, qpll0_lock}) + ); + +end + +wire gt_tx_pd; +wire gt_tx_reset; +wire gt_tx_reset_done; +wire gt_userclk_tx_active; +wire gt_tx_pma_reset; +wire gt_tx_pcs_reset; +wire gt_tx_pma_reset_done; +wire gt_tx_prgdiv_reset; +wire gt_tx_prgdiv_reset_done; +wire gt_tx_qpll_sel; +wire gt_tx_userrdy; + +wire tx_reset_done; taxi_sync_reset #( .N(4) ) tx_reset_sync_inst ( .clk(tx_clk), - .rst(!gt_reset_tx_done || tx_rst_in), + .rst(!tx_reset_done || tx_rst_in), .out(tx_rst_out) ); +taxi_gt_tx_reset #( + .GT_TX_PD(GT_TX_PD), + .GT_TX_QPLL_SEL(GT_TX_QPLL_SEL), + .CNT_W(8) +) +gt_tx_reset_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst_sync), + + /* + * GT + */ + .gt_tx_pd_out(gt_tx_pd), + .gt_tx_reset_out(gt_tx_reset), + .gt_tx_reset_done_in(gt_tx_reset_done), + .gt_userclk_tx_active_in(gt_userclk_tx_active), + .gt_tx_pma_reset_out(gt_tx_pma_reset), + .gt_tx_pcs_reset_out(gt_tx_pcs_reset), + .gt_tx_pma_reset_done_in(gt_tx_pma_reset_done), + .gt_tx_prgdiv_reset_out(gt_tx_prgdiv_reset), + .gt_tx_prgdiv_reset_done_in(gt_tx_prgdiv_reset_done), + .gt_tx_qpll_sel_out(gt_tx_qpll_sel), + .gt_tx_userrdy_out(gt_tx_userrdy), + + /* + * Control/status + */ + .qpll0_lock_in(qpll0_lock), + .qpll1_lock_in(qpll1_lock), + .tx_reset_in(tx_rst_in), + .tx_reset_done_out(tx_reset_done), + .tx_pma_reset_in(1'b0), + .tx_pma_reset_done_out(), + .tx_prgdiv_reset_done_out(), + .tx_pcs_reset_in(1'b0), + .tx_pd_in(GT_TX_PD), + .tx_qpll_sel_in(GT_TX_QPLL_SEL) +); + +wire gt_rx_pd; +wire gt_rx_reset; +wire gt_rx_reset_done; +wire gt_userclk_rx_active; +wire gt_rx_pma_reset; +wire gt_rx_dfe_lpm_reset; +wire gt_rx_eyescan_reset; +wire gt_rx_pcs_reset; +wire gt_rx_pma_reset_done; +wire gt_rx_prgdiv_reset; +wire gt_rx_prgdiv_reset_done; +wire gt_rx_qpll_sel; +wire gt_rx_userrdy; +wire gt_rx_cdr_lock; +wire gt_rx_lpm_en; + +wire rx_reset_done; + taxi_sync_reset #( .N(4) ) rx_reset_sync_inst ( .clk(rx_clk), - .rst(!gt_reset_rx_done || rx_rst_in), + .rst(!rx_reset_done || rx_rst_in), .out(rx_rst_out) ); +taxi_gt_rx_reset #( + .GT_RX_PD(GT_RX_PD), + .GT_RX_QPLL_SEL(GT_RX_QPLL_SEL), + .GT_RX_LPM_EN(GT_RX_LPM_EN), + .CNT_W(8), + .CDR_CNT_W(20) +) +gt_rx_reset_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst_sync), + + /* + * GT + */ + .gt_rx_pd_out(gt_rx_pd), + .gt_rx_reset_out(gt_rx_reset), + .gt_rx_reset_done_in(gt_rx_reset_done), + .gt_userclk_rx_active_in(gt_userclk_rx_active), + .gt_rx_pma_reset_out(gt_rx_pma_reset), + .gt_rx_dfe_lpm_reset_out(gt_rx_dfe_lpm_reset), + .gt_rx_eyescan_reset_out(gt_rx_eyescan_reset), + .gt_rx_pcs_reset_out(gt_rx_pcs_reset), + .gt_rx_pma_reset_done_in(gt_rx_pma_reset_done), + .gt_rx_prgdiv_reset_out(gt_rx_prgdiv_reset), + .gt_rx_prgdiv_reset_done_in(gt_rx_prgdiv_reset_done), + .gt_rx_qpll_sel_out(gt_rx_qpll_sel), + .gt_rx_userrdy_out(gt_rx_userrdy), + .gt_rx_cdr_lock_in(gt_rx_cdr_lock), + .gt_rx_lpm_en_out(gt_rx_lpm_en), + + /* + * Control/status + */ + .qpll0_lock_in(qpll0_lock), + .qpll1_lock_in(qpll1_lock), + .rx_reset_in(rx_rst_in), + .rx_reset_done_out(rx_reset_done), + .rx_pma_reset_in(1'b0), + .rx_pma_reset_done_out(), + .rx_prgdiv_reset_done_out(), + .rx_pcs_reset_in(1'b0), + .rx_dfe_lpm_reset_in(1'b0), + .eyescan_reset_in(1'b0), + .rx_pd_in(GT_RX_PD), + .rx_qpll_sel_in(GT_RX_QPLL_SEL), + .rx_lpm_en_in(GT_RX_LPM_EN) +); + if (SIM) begin : xcvr // simulation (no GT core) assign xcvr_gtpowergood_out = 1'b1; - assign xcvr_qpll0lock_out = 1'b1; + assign xcvr_qpll0lock_out = !gt_qpll0_reset && !gt_qpll0_pd; assign xcvr_qpll0clk_out = 1'b0; - assign xcvr_qpll0refclk_out = 1'b0; + assign xcvr_qpll0refclk_out = xcvr_gtrefclk00_in; - assign gt_reset_tx_done = !xcvr_ctrl_rst; - assign gt_reset_rx_done = !xcvr_ctrl_rst; + assign xcvr_qpll1lock_out = !gt_qpll1_reset && !gt_qpll0_pd; + assign xcvr_qpll1clk_out = 1'b0; + assign xcvr_qpll1refclk_out = xcvr_gtrefclk01_in; + + assign gt_tx_reset_done = !gt_tx_reset; + assign gt_userclk_tx_active = gt_tx_qpll_sel ? qpll1_lock : qpll0_lock; + assign gt_tx_pma_reset_done = gt_tx_reset_done; + assign gt_tx_prgdiv_reset_done = gt_tx_reset_done; + + assign gt_rx_reset_done = !gt_rx_reset; + assign gt_userclk_rx_active = gt_rx_qpll_sel ? qpll1_lock : qpll0_lock; + assign gt_rx_pma_reset_done = gt_rx_reset_done; + assign gt_rx_prgdiv_reset_done = gt_rx_reset_done; + assign gt_rx_cdr_lock = gt_rx_reset_done; end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // UltraScale+ GTY (with common) @@ -130,8 +370,6 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr taxi_eth_phy_25g_us_gty_full taxi_eth_phy_25g_us_gty_full_inst ( // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), .gtpowergood_out(xcvr_gtpowergood_out), // PLL @@ -139,6 +377,18 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .qpll0lock_out(xcvr_qpll0lock_out), .qpll0outclk_out(xcvr_qpll0clk_out), .qpll0outrefclk_out(xcvr_qpll0refclk_out), + .gtrefclk01_in(xcvr_gtrefclk01_in), + .qpll1lock_out(xcvr_qpll1lock_out), + .qpll1outclk_out(xcvr_qpll1clk_out), + .qpll1outrefclk_out(xcvr_qpll1refclk_out), + + .qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : gt_qpll0_pd), + .qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : gt_qpll0_reset), + .qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : gt_qpll1_pd), + .qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : gt_qpll1_reset), + + .pcierateqpll0_in(QPLL0_EXT_CTRL ? xcvr_qpll0pcierate_in : 3'd0), + .pcierateqpll1_in(QPLL1_EXT_CTRL ? xcvr_qpll1pcierate_in : 3'd0), // Serial data .gtytxp_out(xcvr_txp), @@ -147,35 +397,63 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .gtyrxn_in(xcvr_rxn), // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_reset_in(gt_tx_reset), .gtwiz_userclk_tx_srcclk_out(), .gtwiz_userclk_tx_usrclk_out(), .gtwiz_userclk_tx_usrclk2_out(tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), + .gtwiz_userclk_tx_active_out(gt_userclk_tx_active), + .gtwiz_reset_tx_done_in(tx_reset_done), + .txpdelecidlemode_in(1'b1), + .txpd_in(gt_tx_pd ? 2'b11 : 2'b00), + .gttxreset_in(gt_tx_reset), + .txpmareset_in(gt_tx_pma_reset), + .txpcsreset_in(gt_tx_pcs_reset), + .txresetdone_out(gt_tx_reset_done), + .txpmaresetdone_out(gt_tx_pma_reset_done), + .txprogdivreset_in(gt_tx_prgdiv_reset), + .txprgdivresetdone_out(gt_tx_prgdiv_reset_done), + .txpllclksel_in(gt_tx_qpll_sel ? 2'b10 : 2'b11), + .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), + .txuserrdy_in(gt_tx_userrdy), .txpolarity_in(GT_TX_POLARITY), + .txelecidle_in(GT_TX_ELECIDLE), + .txinhibit_in(GT_TX_INHIBIT), + .txdiffctrl_in(GT_TX_DIFFCTRL), + .txmaincursor_in(GT_TX_MAINCURSOR), + .txprecursor_in(GT_TX_PRECURSOR), + .txpostcursor_in(GT_TX_POSTCURSOR), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), .txsequence_in(7'b0), // Receive - .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_reset_in(gt_rx_reset), .gtwiz_userclk_rx_srcclk_out(), .gtwiz_userclk_rx_usrclk_out(), .gtwiz_userclk_rx_usrclk2_out(rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), + .gtwiz_userclk_rx_active_out(gt_userclk_rx_active), + .gtwiz_reset_rx_done_in(rx_reset_done), + .rxpd_in(gt_rx_pd ? 2'b11 : 2'b00), + .gtrxreset_in(gt_rx_reset), + .rxpmareset_in(gt_rx_pma_reset), + .rxdfelpmreset_in(gt_rx_dfe_lpm_reset), + .eyescanreset_in(gt_rx_eyescan_reset), + .rxpcsreset_in(gt_rx_pcs_reset), + .rxresetdone_out(gt_rx_reset_done), + .rxpmaresetdone_out(gt_rx_pma_reset_done), + .rxprogdivreset_in(gt_rx_prgdiv_reset), + .rxprgdivresetdone_out(gt_rx_prgdiv_reset_done), + .rxpllclksel_in(gt_rx_qpll_sel ? 2'b10 : 2'b11), + .rxsysclksel_in(gt_rx_qpll_sel ? 2'b11 : 2'b10), + .rxuserrdy_in(gt_rx_userrdy), + + .rxcdrlock_out(gt_rx_cdr_lock), + .rxcdrhold_in(1'b0), + .rxcdrovrden_in(1'b0), + + .rxlpmen_in(gt_rx_lpm_en), .rxpolarity_in(GT_RX_POLARITY), @@ -187,16 +465,12 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .rxstartofseq_out() ); - assign xcvr_qpll0reset_out = 1'b0; - end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr // UltraScale+ GTH (with common) taxi_eth_phy_25g_us_gth_full taxi_eth_phy_25g_us_gth_full_inst ( // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), .gtpowergood_out(xcvr_gtpowergood_out), // PLL @@ -204,6 +478,18 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .qpll0lock_out(xcvr_qpll0lock_out), .qpll0outclk_out(xcvr_qpll0clk_out), .qpll0outrefclk_out(xcvr_qpll0refclk_out), + .gtrefclk01_in(xcvr_gtrefclk01_in), + .qpll1lock_out(xcvr_qpll1lock_out), + .qpll1outclk_out(xcvr_qpll1clk_out), + .qpll1outrefclk_out(xcvr_qpll1refclk_out), + + .qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : gt_qpll0_pd), + .qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : gt_qpll0_reset), + .qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : gt_qpll1_pd), + .qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : gt_qpll1_reset), + + .pcierateqpll0_in(QPLL0_EXT_CTRL ? xcvr_qpll0pcierate_in : 3'd0), + .pcierateqpll1_in(QPLL1_EXT_CTRL ? xcvr_qpll1pcierate_in : 3'd0), // Serial data .gthtxp_out(xcvr_txp), @@ -212,35 +498,63 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .gthrxn_in(xcvr_rxn), // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_reset_in(gt_tx_reset), .gtwiz_userclk_tx_srcclk_out(), .gtwiz_userclk_tx_usrclk_out(), .gtwiz_userclk_tx_usrclk2_out(tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), + .gtwiz_userclk_tx_active_out(gt_userclk_tx_active), + .gtwiz_reset_tx_done_in(tx_reset_done), + .txpdelecidlemode_in(1'b1), + .txpd_in(gt_tx_pd ? 2'b11 : 2'b00), + .gttxreset_in(gt_tx_reset), + .txpmareset_in(gt_tx_pma_reset), + .txpcsreset_in(gt_tx_pcs_reset), + .txresetdone_out(gt_tx_reset_done), + .txpmaresetdone_out(gt_tx_pma_reset_done), + .txprogdivreset_in(gt_tx_prgdiv_reset), + .txprgdivresetdone_out(gt_tx_prgdiv_reset_done), + .txpllclksel_in(gt_tx_qpll_sel ? 2'b10 : 2'b11), + .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), + .txuserrdy_in(gt_tx_userrdy), .txpolarity_in(GT_TX_POLARITY), + .txelecidle_in(GT_TX_ELECIDLE), + .txinhibit_in(GT_TX_INHIBIT), + .txdiffctrl_in(GT_TX_DIFFCTRL), + .txmaincursor_in(GT_TX_MAINCURSOR), + .txprecursor_in(GT_TX_PRECURSOR), + .txpostcursor_in(GT_TX_POSTCURSOR), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), .txsequence_in(7'b0), // Receive - .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_reset_in(gt_rx_reset), .gtwiz_userclk_rx_srcclk_out(), .gtwiz_userclk_rx_usrclk_out(), .gtwiz_userclk_rx_usrclk2_out(rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), + .gtwiz_userclk_rx_active_out(gt_userclk_rx_active), + .gtwiz_reset_rx_done_in(rx_reset_done), + .rxpd_in(gt_rx_pd ? 2'b11 : 2'b00), + .gtrxreset_in(gt_rx_reset), + .rxpmareset_in(gt_rx_pma_reset), + .rxdfelpmreset_in(gt_rx_dfe_lpm_reset), + .eyescanreset_in(gt_rx_eyescan_reset), + .rxpcsreset_in(gt_rx_pcs_reset), + .rxresetdone_out(gt_rx_reset_done), + .rxpmaresetdone_out(gt_rx_pma_reset_done), + .rxprogdivreset_in(gt_rx_prgdiv_reset), + .rxprgdivresetdone_out(gt_rx_prgdiv_reset_done), + .rxpllclksel_in(gt_rx_qpll_sel ? 2'b10 : 2'b11), + .rxsysclksel_in(gt_rx_qpll_sel ? 2'b11 : 2'b10), + .rxuserrdy_in(gt_rx_userrdy), + + .rxcdrlock_out(gt_rx_cdr_lock), + .rxcdrhold_in(1'b0), + .rxcdrovrden_in(1'b0), + + .rxlpmen_in(gt_rx_lpm_en), .rxpolarity_in(GT_RX_POLARITY), @@ -252,16 +566,12 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .rxstartofseq_out() ); - assign xcvr_qpll0reset_out = 1'b0; - end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr // UltraScale GTY (with common) taxi_eth_phy_25g_us_gty_full taxi_eth_phy_25g_us_gty_full_inst ( // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), .gtpowergood_out(xcvr_gtpowergood_out), // PLL @@ -269,6 +579,18 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .qpll0lock_out(xcvr_qpll0lock_out), .qpll0outclk_out(xcvr_qpll0clk_out), .qpll0outrefclk_out(xcvr_qpll0refclk_out), + .gtrefclk01_in(xcvr_gtrefclk01_in), + .qpll1lock_out(xcvr_qpll1lock_out), + .qpll1outclk_out(xcvr_qpll1clk_out), + .qpll1outrefclk_out(xcvr_qpll1refclk_out), + + .qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : gt_qpll0_pd), + .qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : gt_qpll0_reset), + .qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : gt_qpll1_pd), + .qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : gt_qpll1_reset), + + .qpllrsvd2_in(QPLL0_EXT_CTRL ? {2'd0, xcvr_qpll0pcierate_in} : 5'd0), // [2:0] : QPLL0 rate + .qpllrsvd3_in(QPLL1_EXT_CTRL ? {2'd0, xcvr_qpll1pcierate_in} : 5'd0), // [2:0] : QPLL1 rate // Serial data .gtytxp_out(xcvr_txp), @@ -277,35 +599,63 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .gtyrxn_in(xcvr_rxn), // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_reset_in(gt_tx_reset), .gtwiz_userclk_tx_srcclk_out(), .gtwiz_userclk_tx_usrclk_out(), .gtwiz_userclk_tx_usrclk2_out(tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), + .gtwiz_userclk_tx_active_out(gt_userclk_tx_active), + .gtwiz_reset_tx_done_in(tx_reset_done), + .txpdelecidlemode_in(1'b1), + .txpd_in(gt_tx_pd ? 2'b11 : 2'b00), + .gttxreset_in(gt_tx_reset), + .txpmareset_in(gt_tx_pma_reset), + .txpcsreset_in(gt_tx_pcs_reset), + .txresetdone_out(gt_tx_reset_done), + .txpmaresetdone_out(gt_tx_pma_reset_done), + .txprogdivreset_in(gt_tx_prgdiv_reset), + .txprgdivresetdone_out(gt_tx_prgdiv_reset_done), + .txpllclksel_in(gt_tx_qpll_sel ? 2'b10 : 2'b11), + .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), + .txuserrdy_in(gt_tx_userrdy), .txpolarity_in(GT_TX_POLARITY), + .txelecidle_in(GT_TX_ELECIDLE), + .txinhibit_in(GT_TX_INHIBIT), + .txdiffctrl_in(GT_TX_DIFFCTRL), + .txmaincursor_in(GT_TX_MAINCURSOR), + .txprecursor_in(GT_TX_PRECURSOR), + .txpostcursor_in(GT_TX_POSTCURSOR), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), .txsequence_in(7'b0), // Receive - .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_reset_in(gt_rx_reset), .gtwiz_userclk_rx_srcclk_out(), .gtwiz_userclk_rx_usrclk_out(), .gtwiz_userclk_rx_usrclk2_out(rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), + .gtwiz_userclk_rx_active_out(gt_userclk_rx_active), + .gtwiz_reset_rx_done_in(rx_reset_done), + .rxpd_in(gt_rx_pd ? 2'b11 : 2'b00), + .gtrxreset_in(gt_rx_reset), + .rxpmareset_in(gt_rx_pma_reset), + .rxdfelpmreset_in(gt_rx_dfe_lpm_reset), + .eyescanreset_in(gt_rx_eyescan_reset), + .rxpcsreset_in(gt_rx_pcs_reset), + .rxresetdone_out(gt_rx_reset_done), + .rxpmaresetdone_out(gt_rx_pma_reset_done), + .rxprogdivreset_in(gt_rx_prgdiv_reset), + .rxprgdivresetdone_out(gt_rx_prgdiv_reset_done), + .rxpllclksel_in(gt_rx_qpll_sel ? 2'b10 : 2'b11), + .rxsysclksel_in(gt_rx_qpll_sel ? 2'b11 : 2'b10), + .rxuserrdy_in(gt_rx_userrdy), + + .rxcdrlock_out(gt_rx_cdr_lock), + .rxcdrhold_in(1'b0), + .rxcdrovrden_in(1'b0), + + .rxlpmen_in(gt_rx_lpm_en), .rxpolarity_in(GT_RX_POLARITY), @@ -317,16 +667,12 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .rxstartofseq_out() ); - assign xcvr_qpll0reset_out = 1'b0; - end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr // UltraScale GTH (with common) taxi_eth_phy_25g_us_gth_full taxi_eth_phy_25g_us_gth_full_inst ( // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), .gtpowergood_out(xcvr_gtpowergood_out), // PLL @@ -334,6 +680,18 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .qpll0lock_out(xcvr_qpll0lock_out), .qpll0outclk_out(xcvr_qpll0clk_out), .qpll0outrefclk_out(xcvr_qpll0refclk_out), + .gtrefclk01_in(xcvr_gtrefclk01_in), + .qpll1lock_out(xcvr_qpll1lock_out), + .qpll1outclk_out(xcvr_qpll1clk_out), + .qpll1outrefclk_out(xcvr_qpll1refclk_out), + + .qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : gt_qpll0_pd), + .qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : gt_qpll0_reset), + .qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : gt_qpll1_pd), + .qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : gt_qpll1_reset), + + .qpllrsvd2_in(QPLL0_EXT_CTRL ? {2'd0, xcvr_qpll0pcierate_in} : 5'd0), // [2:0] : QPLL0 rate + .qpllrsvd3_in(QPLL1_EXT_CTRL ? {2'd0, xcvr_qpll1pcierate_in} : 5'd0), // [2:0] : QPLL1 rate // Serial data .gthtxp_out(xcvr_txp), @@ -342,35 +700,63 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .gthrxn_in(xcvr_rxn), // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_reset_in(gt_tx_reset), .gtwiz_userclk_tx_srcclk_out(), .gtwiz_userclk_tx_usrclk_out(), .gtwiz_userclk_tx_usrclk2_out(tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), + .gtwiz_userclk_tx_active_out(gt_userclk_tx_active), + .gtwiz_reset_tx_done_in(tx_reset_done), + .txpdelecidlemode_in(1'b1), + .txpd_in(gt_tx_pd ? 2'b11 : 2'b00), + .gttxreset_in(gt_tx_reset), + .txpmareset_in(gt_tx_pma_reset), + .txpcsreset_in(gt_tx_pcs_reset), + .txresetdone_out(gt_tx_reset_done), + .txpmaresetdone_out(gt_tx_pma_reset_done), + .txprogdivreset_in(gt_tx_prgdiv_reset), + .txprgdivresetdone_out(gt_tx_prgdiv_reset_done), + .txpllclksel_in(gt_tx_qpll_sel ? 2'b10 : 2'b11), + .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), + .txuserrdy_in(gt_tx_userrdy), .txpolarity_in(GT_TX_POLARITY), + .txelecidle_in(GT_TX_ELECIDLE), + .txinhibit_in(GT_TX_INHIBIT), + .txdiffctrl_in(GT_TX_DIFFCTRL), + .txmaincursor_in(GT_TX_MAINCURSOR), + .txprecursor_in(GT_TX_PRECURSOR), + .txpostcursor_in(GT_TX_POSTCURSOR), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), .txsequence_in(7'b0), // Receive - .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_reset_in(gt_rx_reset), .gtwiz_userclk_rx_srcclk_out(), .gtwiz_userclk_rx_usrclk_out(), .gtwiz_userclk_rx_usrclk2_out(rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), + .gtwiz_userclk_rx_active_out(gt_userclk_rx_active), + .gtwiz_reset_rx_done_in(rx_reset_done), + .rxpd_in(gt_rx_pd ? 2'b11 : 2'b00), + .gtrxreset_in(gt_rx_reset), + .rxpmareset_in(gt_rx_pma_reset), + .rxdfelpmreset_in(gt_rx_dfe_lpm_reset), + .eyescanreset_in(gt_rx_eyescan_reset), + .rxpcsreset_in(gt_rx_pcs_reset), + .rxresetdone_out(gt_rx_reset_done), + .rxpmaresetdone_out(gt_rx_pma_reset_done), + .rxprogdivreset_in(gt_rx_prgdiv_reset), + .rxprgdivresetdone_out(gt_rx_prgdiv_reset_done), + .rxpllclksel_in(gt_rx_qpll_sel ? 2'b10 : 2'b11), + .rxsysclksel_in(gt_rx_qpll_sel ? 2'b11 : 2'b10), + .rxuserrdy_in(gt_rx_userrdy), + + .rxcdrlock_out(gt_rx_cdr_lock), + .rxcdrhold_in(1'b0), + .rxcdrovrden_in(1'b0), + + .rxlpmen_in(gt_rx_lpm_en), .rxpolarity_in(GT_RX_POLARITY), @@ -382,25 +768,19 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .rxstartofseq_out() ); - assign xcvr_qpll0reset_out = 1'b0; - end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr // UltraScale/UltraScale+ GTY (channel only) taxi_eth_phy_25g_us_gty_channel taxi_eth_phy_25g_us_gty_channel_inst ( // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), .gtpowergood_out(xcvr_gtpowergood_out), // PLL - .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), - .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), - .qpll1clk_in(1'b0), - .qpll1refclk_in(1'b0), + .qpll1clk_in(xcvr_qpll1clk_in), + .qpll1refclk_in(xcvr_qpll1refclk_in), // Serial data .gtytxp_out(xcvr_txp), @@ -409,35 +789,63 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .gtyrxn_in(xcvr_rxn), // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_reset_in(gt_tx_reset), .gtwiz_userclk_tx_srcclk_out(), .gtwiz_userclk_tx_usrclk_out(), .gtwiz_userclk_tx_usrclk2_out(tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), + .gtwiz_userclk_tx_active_out(gt_userclk_tx_active), + .gtwiz_reset_tx_done_in(tx_reset_done), + .txpdelecidlemode_in(1'b1), + .txpd_in(gt_tx_pd ? 2'b11 : 2'b00), + .gttxreset_in(gt_tx_reset), + .txpmareset_in(gt_tx_pma_reset), + .txpcsreset_in(gt_tx_pcs_reset), + .txresetdone_out(gt_tx_reset_done), + .txpmaresetdone_out(gt_tx_pma_reset_done), + .txprogdivreset_in(gt_tx_prgdiv_reset), + .txprgdivresetdone_out(gt_tx_prgdiv_reset_done), + .txpllclksel_in(gt_tx_qpll_sel ? 2'b10 : 2'b11), + .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), + .txuserrdy_in(gt_tx_userrdy), .txpolarity_in(GT_TX_POLARITY), + .txelecidle_in(GT_TX_ELECIDLE), + .txinhibit_in(GT_TX_INHIBIT), + .txdiffctrl_in(GT_TX_DIFFCTRL), + .txmaincursor_in(GT_TX_MAINCURSOR), + .txprecursor_in(GT_TX_PRECURSOR), + .txpostcursor_in(GT_TX_POSTCURSOR), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), .txsequence_in(7'b0), // Receive - .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_reset_in(gt_rx_reset), .gtwiz_userclk_rx_srcclk_out(), .gtwiz_userclk_rx_usrclk_out(), .gtwiz_userclk_rx_usrclk2_out(rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), + .gtwiz_userclk_rx_active_out(gt_userclk_rx_active), + .gtwiz_reset_rx_done_in(rx_reset_done), + .rxpd_in(gt_rx_pd ? 2'b11 : 2'b00), + .gtrxreset_in(gt_rx_reset), + .rxpmareset_in(gt_rx_pma_reset), + .rxdfelpmreset_in(gt_rx_dfe_lpm_reset), + .eyescanreset_in(gt_rx_eyescan_reset), + .rxpcsreset_in(gt_rx_pcs_reset), + .rxresetdone_out(gt_rx_reset_done), + .rxpmaresetdone_out(gt_rx_pma_reset_done), + .rxprogdivreset_in(gt_rx_prgdiv_reset), + .rxprgdivresetdone_out(gt_rx_prgdiv_reset_done), + .rxpllclksel_in(gt_rx_qpll_sel ? 2'b10 : 2'b11), + .rxsysclksel_in(gt_rx_qpll_sel ? 2'b11 : 2'b10), + .rxuserrdy_in(gt_rx_userrdy), + + .rxcdrlock_out(gt_rx_cdr_lock), + .rxcdrhold_in(1'b0), + .rxcdrovrden_in(1'b0), + + .rxlpmen_in(gt_rx_lpm_en), .rxpolarity_in(GT_RX_POLARITY), @@ -459,17 +867,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr taxi_eth_phy_25g_us_gth_channel taxi_eth_phy_25g_us_gth_channel_inst ( // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), .gtpowergood_out(xcvr_gtpowergood_out), // PLL - .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), - .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), - .qpll1clk_in(1'b0), - .qpll1refclk_in(1'b0), + .qpll1clk_in(xcvr_qpll1clk_in), + .qpll1refclk_in(xcvr_qpll1refclk_in), // Serial data .gthtxp_out(xcvr_txp), @@ -478,35 +882,63 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .gthrxn_in(xcvr_rxn), // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_reset_in(gt_tx_reset), .gtwiz_userclk_tx_srcclk_out(), .gtwiz_userclk_tx_usrclk_out(), .gtwiz_userclk_tx_usrclk2_out(tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), + .gtwiz_userclk_tx_active_out(gt_userclk_tx_active), + .gtwiz_reset_tx_done_in(tx_reset_done), + .txpdelecidlemode_in(1'b1), + .txpd_in(gt_tx_pd ? 2'b11 : 2'b00), + .gttxreset_in(gt_tx_reset), + .txpmareset_in(gt_tx_pma_reset), + .txpcsreset_in(gt_tx_pcs_reset), + .txresetdone_out(gt_tx_reset_done), + .txpmaresetdone_out(gt_tx_pma_reset_done), + .txprogdivreset_in(gt_tx_prgdiv_reset), + .txprgdivresetdone_out(gt_tx_prgdiv_reset_done), + .txpllclksel_in(gt_tx_qpll_sel ? 2'b10 : 2'b11), + .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), + .txuserrdy_in(gt_tx_userrdy), .txpolarity_in(GT_TX_POLARITY), + .txelecidle_in(GT_TX_ELECIDLE), + .txinhibit_in(GT_TX_INHIBIT), + .txdiffctrl_in(GT_TX_DIFFCTRL), + .txmaincursor_in(GT_TX_MAINCURSOR), + .txprecursor_in(GT_TX_PRECURSOR), + .txpostcursor_in(GT_TX_POSTCURSOR), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), .txsequence_in(7'b0), // Receive - .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_reset_in(gt_rx_reset), .gtwiz_userclk_rx_srcclk_out(), .gtwiz_userclk_rx_usrclk_out(), .gtwiz_userclk_rx_usrclk2_out(rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), + .gtwiz_userclk_rx_active_out(gt_userclk_rx_active), + .gtwiz_reset_rx_done_in(rx_reset_done), + .rxpd_in(gt_rx_pd ? 2'b11 : 2'b00), + .gtrxreset_in(gt_rx_reset), + .rxpmareset_in(gt_rx_pma_reset), + .rxdfelpmreset_in(gt_rx_dfe_lpm_reset), + .eyescanreset_in(gt_rx_eyescan_reset), + .rxpcsreset_in(gt_rx_pcs_reset), + .rxresetdone_out(gt_rx_reset_done), + .rxpmaresetdone_out(gt_rx_pma_reset_done), + .rxprogdivreset_in(gt_rx_prgdiv_reset), + .rxprgdivresetdone_out(gt_rx_prgdiv_reset_done), + .rxpllclksel_in(gt_rx_qpll_sel ? 2'b10 : 2'b11), + .rxsysclksel_in(gt_rx_qpll_sel ? 2'b11 : 2'b10), + .rxuserrdy_in(gt_rx_userrdy), + + .rxcdrlock_out(gt_rx_cdr_lock), + .rxcdrhold_in(1'b0), + .rxcdrovrden_in(1'b0), + + .rxlpmen_in(gt_rx_lpm_en), .rxpolarity_in(GT_RX_POLARITY), diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl index 1920fc8..fcedb7c 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl index 4ae4a51..03f2e0c 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl index 8fe53c4..10c1412 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl index 5fabfb6..054c8c4 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl index 9d928d6..ade0dd0 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl index a8c96fb..3f85c54 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl index 93d2629..2399e22 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl index bfd2d8b..c2792e4 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl index 2b0f2d7..57fd89a 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl @@ -21,9 +21,34 @@ set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} { + lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in +} else { + lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in +} +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in # channel polarity lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in +# channel EQ +lappend extra_ports rxlpmen_in set config [dict create] @@ -48,7 +73,7 @@ if {$sec_line_rate != 0} { } dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/src/hip/rtl/us/taxi_gt_qpll_reset.sv b/src/hip/rtl/us/taxi_gt_qpll_reset.sv new file mode 100644 index 0000000..4c7afdd --- /dev/null +++ b/src/hip/rtl/us/taxi_gt_qpll_reset.sv @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * GT QPLL reset controller for UltraScale/UltraScale+ GTH/GTY + */ +module taxi_gt_qpll_reset # +( + parameter logic QPLL_PD = 1'b0, + parameter CNT_W = 8 +) +( + input wire logic clk, + input wire logic rst, + + /* + * GT + */ + output wire logic gt_qpll_reset_out, + output wire logic gt_qpll_pd_out, + input wire logic gt_qpll_lock_in, + + /* + * Control/status + */ + input wire logic qpll_reset_in = 1'b0, + input wire logic qpll_pd_in = QPLL_PD, + output wire logic qpll_lock_out +); + +logic qpll_reset_reg = 1'b1; +logic qpll_pd_reg = QPLL_PD; + +logic [CNT_W-1:0] qpll_reset_cnt_reg = '0; + +assign gt_qpll_reset_out = qpll_reset_reg; +assign gt_qpll_pd_out = qpll_pd_reg; + +always_ff @(posedge clk) begin + qpll_pd_reg <= qpll_pd_in; + + if (&qpll_reset_cnt_reg) begin + qpll_reset_reg <= 1'b0; + end else begin + qpll_reset_cnt_reg <= qpll_reset_cnt_reg + 1; + qpll_reset_reg <= 1'b1; + end + + if (qpll_reset_in || qpll_pd_reg) begin + qpll_reset_cnt_reg <= 0; + end + + if (rst) begin + qpll_reset_reg <= 1'b1; + qpll_pd_reg <= QPLL_PD; + qpll_reset_cnt_reg <= '0; + end +end + +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +qpll_lock_sync_inst ( + .clk(clk), + .in(gt_qpll_lock_in), + .out(qpll_lock_out) +); + +endmodule + +`resetall diff --git a/src/hip/rtl/us/taxi_gt_rx_reset.sv b/src/hip/rtl/us/taxi_gt_rx_reset.sv new file mode 100644 index 0000000..a307377 --- /dev/null +++ b/src/hip/rtl/us/taxi_gt_rx_reset.sv @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * GT RX reset controller for UltraScale/UltraScale+ GTH/GTY + */ +module taxi_gt_rx_reset # +( + parameter GT_RX_PD = 1'b0, + parameter GT_RX_QPLL_SEL = 1'b0, + parameter GT_RX_LPM_EN = 1'b0, + parameter CNT_W = 8, + parameter CDR_CNT_W = 20 +) +( + input wire logic clk, + input wire logic rst, + + /* + * GT + */ + output wire logic gt_rx_pd_out, + output wire logic gt_rx_reset_out, + input wire logic gt_rx_reset_done_in, + input wire logic gt_userclk_rx_active_in, + output wire logic gt_rx_pma_reset_out, + output wire logic gt_rx_dfe_lpm_reset_out, + output wire logic gt_rx_eyescan_reset_out, + output wire logic gt_rx_pcs_reset_out, + input wire logic gt_rx_pma_reset_done_in, + output wire logic gt_rx_prgdiv_reset_out, + input wire logic gt_rx_prgdiv_reset_done_in, + output wire logic gt_rx_qpll_sel_out, + output wire logic gt_rx_userrdy_out, + input wire logic gt_rx_cdr_lock_in, + output wire logic gt_rx_lpm_en_out, + + /* + * Control/status + */ + input wire logic qpll0_lock_in, + input wire logic qpll1_lock_in, + input wire logic rx_reset_in = 1'b0, + output wire logic rx_reset_done_out, + input wire logic rx_pma_reset_in = 1'b0, + output wire logic rx_pma_reset_done_out, + output wire logic rx_prgdiv_reset_done_out, + input wire logic rx_pcs_reset_in = 1'b0, + input wire logic rx_dfe_lpm_reset_in = 1'b0, + input wire logic eyescan_reset_in = 1'b0, + input wire logic rx_pd_in = GT_RX_PD, + input wire logic rx_qpll_sel_in = GT_RX_QPLL_SEL, + input wire logic rx_lpm_en_in = GT_RX_LPM_EN +); + +logic gt_rx_reset_reg = 1'b1; +logic gt_rx_pma_reset_reg = 1'b0; +logic gt_rx_pcs_reset_reg = 1'b0; +logic gt_rx_dfe_lpm_reset_reg = 1'b0; +logic gt_eyescan_reset_reg = 1'b0; + +logic gt_rx_prgdiv_reset_reg = 1'b0; +logic gt_rx_userrdy_reg = 1'b0; + +logic gt_rx_pd_reg = GT_RX_PD; + +logic gt_rx_qpll_sel_reg = GT_RX_QPLL_SEL; +logic gt_rx_lpm_en_reg = GT_RX_LPM_EN; + +wire gt_rx_reset_done_sync; +wire gt_rx_pma_reset_done_sync; +wire gt_rx_prgdiv_reset_done_sync; +wire gt_userclk_rx_active_sync; +wire gt_rx_cdr_lock_sync; + +taxi_sync_signal #( + .WIDTH(5), + .N(2) +) +gt_status_sync_inst ( + .clk(clk), + .in({gt_rx_reset_done_in, gt_rx_pma_reset_done_in, gt_rx_prgdiv_reset_done_in, gt_userclk_rx_active_in, gt_rx_cdr_lock_in}), + .out({gt_rx_reset_done_sync, gt_rx_pma_reset_done_sync, gt_rx_prgdiv_reset_done_sync, gt_userclk_rx_active_sync, gt_rx_cdr_lock_sync}) +); + +wire rx_reset_sync; + +taxi_sync_reset #( + .N(4) +) +reset_sync_inst ( + .clk(clk), + .rst(rx_reset_in), + .out(rx_reset_sync) +); + +localparam [2:0] + STATE_RESET = 3'd0, + STATE_WAIT_LOCK = 3'd1, + STATE_WAIT_CDR = 3'd2, + STATE_WAIT_USRCLK = 3'd3, + STATE_DONE = 3'd4; + +logic [2:0] state_reg = STATE_RESET; +logic [CNT_W-1:0] rx_reset_cnt_reg = '0; +logic [CDR_CNT_W-1:0] rx_reset_cdr_cnt_reg = '0; +logic rx_reset_done_reg = 1'b0; + +assign rx_reset_done_out = rx_reset_done_reg; + +assign gt_rx_pd_out = gt_rx_pd_reg; +assign gt_rx_reset_out = gt_rx_reset_reg; +assign gt_rx_pma_reset_out = gt_rx_pma_reset_reg; +assign gt_rx_dfe_lpm_reset_out = gt_rx_dfe_lpm_reset_reg; +assign gt_rx_eyescan_reset_out = gt_eyescan_reset_reg; +assign gt_rx_pcs_reset_out = gt_rx_pcs_reset_reg; +assign gt_rx_prgdiv_reset_out = gt_rx_prgdiv_reset_reg; +assign gt_rx_qpll_sel_out = gt_rx_qpll_sel_reg; +assign gt_rx_userrdy_out = gt_rx_userrdy_reg; +assign gt_rx_lpm_en_out = gt_rx_lpm_en_reg; + +assign rx_reset_done_out = rx_reset_done_reg; +assign rx_pma_reset_done_out = gt_rx_pma_reset_done_sync; +assign rx_prgdiv_reset_done_out = gt_rx_prgdiv_reset_done_sync; + +wire rx_sel_pll_lock = gt_rx_qpll_sel_reg ? qpll1_lock_in : qpll0_lock_in; + +always_ff @(posedge clk) begin + gt_rx_reset_reg <= 1'b1; + gt_rx_pma_reset_reg <= rx_pma_reset_in; + gt_rx_pcs_reset_reg <= rx_pcs_reset_in; + gt_rx_dfe_lpm_reset_reg <= rx_dfe_lpm_reset_in; + gt_eyescan_reset_reg <= eyescan_reset_in; + + gt_rx_prgdiv_reset_reg <= 1'b1; + gt_rx_userrdy_reg <= 1'b0; + + state_reg <= STATE_RESET; + rx_reset_cnt_reg <= '0; + rx_reset_cdr_cnt_reg <= '0; + rx_reset_done_reg <= 1'b0; + + case (state_reg) + STATE_RESET: begin + gt_rx_reset_reg <= 1'b1; + gt_rx_prgdiv_reset_reg <= 1'b1; + gt_rx_userrdy_reg <= 1'b0; + + gt_rx_pd_reg <= rx_pd_in; + gt_rx_qpll_sel_reg <= rx_qpll_sel_in; + + gt_rx_lpm_en_reg <= rx_lpm_en_in; + + state_reg <= STATE_WAIT_LOCK; + end + STATE_WAIT_LOCK: begin + gt_rx_reset_reg <= 1'b1; + gt_rx_prgdiv_reset_reg <= 1'b1; + gt_rx_userrdy_reg <= 1'b0; + + state_reg <= STATE_WAIT_LOCK; + if (rx_sel_pll_lock) begin + // QPLL locked + rx_reset_cnt_reg <= rx_reset_cnt_reg + 1; + if (&rx_reset_cnt_reg) begin + state_reg <= STATE_WAIT_CDR; + end + end + end + STATE_WAIT_CDR: begin + gt_rx_reset_reg <= 1'b0; + gt_rx_prgdiv_reset_reg <= 1'b1; + gt_rx_userrdy_reg <= 1'b0; + + state_reg <= STATE_WAIT_CDR; + + rx_reset_cdr_cnt_reg <= rx_reset_cdr_cnt_reg + 1; + if (&rx_reset_cdr_cnt_reg) begin + state_reg <= STATE_WAIT_USRCLK; + end + + if (gt_rx_cdr_lock_sync) begin + // CDR locked + rx_reset_cnt_reg <= rx_reset_cnt_reg + 1; + if (&rx_reset_cnt_reg) begin + state_reg <= STATE_WAIT_USRCLK; + end + end + end + STATE_WAIT_USRCLK: begin + gt_rx_reset_reg <= 1'b0; + gt_rx_prgdiv_reset_reg <= 1'b0; + gt_rx_userrdy_reg <= 1'b0; + + state_reg <= STATE_WAIT_USRCLK; + if (gt_userclk_rx_active_sync) begin + // user clock running + rx_reset_cnt_reg <= rx_reset_cnt_reg + 1; + if (&rx_reset_cnt_reg) begin + state_reg <= STATE_DONE; + end + end + end + STATE_DONE: begin + gt_rx_reset_reg <= 1'b0; + gt_rx_prgdiv_reset_reg <= 1'b0; + gt_rx_userrdy_reg <= 1'b1; + + rx_reset_done_reg <= gt_rx_reset_done_sync && gt_rx_prgdiv_reset_done_sync; + + state_reg <= STATE_DONE; + end + default: begin + state_reg <= STATE_RESET; + end + endcase + + if (rx_reset_sync || rx_pd_in || !rx_sel_pll_lock || (gt_rx_qpll_sel_reg != rx_qpll_sel_in) || (gt_rx_lpm_en_reg != rx_lpm_en_in)) begin + state_reg <= STATE_RESET; + end + + if (rst) begin + gt_rx_reset_reg <= 1'b1; + gt_rx_pma_reset_reg <= 1'b0; + gt_rx_pcs_reset_reg <= 1'b0; + gt_rx_dfe_lpm_reset_reg <= 1'b0; + gt_eyescan_reset_reg <= 1'b0; + + gt_rx_prgdiv_reset_reg <= 1'b1; + gt_rx_userrdy_reg <= 1'b0; + + gt_rx_pd_reg <= GT_RX_PD; + gt_rx_qpll_sel_reg <= GT_RX_QPLL_SEL; + + state_reg <= STATE_RESET; + rx_reset_done_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/src/hip/rtl/us/taxi_gt_tx_reset.sv b/src/hip/rtl/us/taxi_gt_tx_reset.sv new file mode 100644 index 0000000..598d5c3 --- /dev/null +++ b/src/hip/rtl/us/taxi_gt_tx_reset.sv @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * GT TX reset controller for UltraScale/UltraScale+ GTH/GTY + */ +module taxi_gt_tx_reset # +( + parameter GT_TX_PD = 1'b0, + parameter GT_TX_QPLL_SEL = 1'b0, + parameter CNT_W = 8 +) +( + input wire logic clk, + input wire logic rst, + + /* + * GT + */ + output wire logic gt_tx_pd_out, + output wire logic gt_tx_reset_out, + input wire logic gt_tx_reset_done_in, + input wire logic gt_userclk_tx_active_in, + output wire logic gt_tx_pma_reset_out, + output wire logic gt_tx_pcs_reset_out, + input wire logic gt_tx_pma_reset_done_in, + output wire logic gt_tx_prgdiv_reset_out, + input wire logic gt_tx_prgdiv_reset_done_in, + output wire logic gt_tx_qpll_sel_out, + output wire logic gt_tx_userrdy_out, + + /* + * Control/status + */ + input wire logic qpll0_lock_in, + input wire logic qpll1_lock_in, + input wire logic tx_reset_in = 1'b0, + output wire logic tx_reset_done_out, + input wire logic tx_pma_reset_in = 1'b0, + output wire logic tx_pma_reset_done_out, + output wire logic tx_prgdiv_reset_done_out, + input wire logic tx_pcs_reset_in = 1'b0, + input wire logic tx_pd_in = GT_TX_PD, + input wire logic tx_qpll_sel_in = GT_TX_QPLL_SEL +); + +logic gt_tx_reset_reg = 1'b1; +logic gt_tx_pma_reset_reg = 1'b0; +logic gt_tx_pcs_reset_reg = 1'b0; + +logic gt_tx_prgdiv_reset_reg = 1'b0; +logic gt_tx_userrdy_reg = 1'b0; + +logic gt_tx_pd_reg = GT_TX_PD; + +logic gt_tx_qpll_sel_reg = GT_TX_QPLL_SEL; + +wire gt_tx_reset_done_sync; +wire gt_tx_pma_reset_done_sync; +wire gt_tx_prgdiv_reset_done_sync; +wire gt_userclk_tx_active_sync; + +taxi_sync_signal #( + .WIDTH(4), + .N(2) +) +gt_status_sync_inst ( + .clk(clk), + .in({gt_tx_reset_done_in, gt_tx_pma_reset_done_in, gt_tx_prgdiv_reset_done_in, gt_userclk_tx_active_in}), + .out({gt_tx_reset_done_sync, gt_tx_pma_reset_done_sync, gt_tx_prgdiv_reset_done_sync, gt_userclk_tx_active_sync}) +); + +wire tx_reset_sync; + +taxi_sync_reset #( + .N(4) +) +reset_sync_inst ( + .clk(clk), + .rst(tx_reset_in), + .out(tx_reset_sync) +); + +localparam [1:0] + STATE_RESET = 2'd0, + STATE_WAIT_LOCK = 2'd1, + STATE_WAIT_USRCLK = 2'd2, + STATE_DONE = 2'd3; + +logic [1:0] state_reg = STATE_RESET; +logic [CNT_W-1:0] tx_reset_cnt_reg = '0; +logic tx_reset_done_reg = 1'b0; + +assign gt_tx_pd_out = gt_tx_pd_reg; +assign gt_tx_reset_out = gt_tx_reset_reg; +assign gt_tx_pma_reset_out = gt_tx_pma_reset_reg; +assign gt_tx_pcs_reset_out = gt_tx_pcs_reset_reg; +assign gt_tx_prgdiv_reset_out = gt_tx_prgdiv_reset_reg; +assign gt_tx_qpll_sel_out = gt_tx_qpll_sel_reg; +assign gt_tx_userrdy_out = gt_tx_userrdy_reg; + +assign tx_reset_done_out = tx_reset_done_reg; +assign tx_pma_reset_done_out = gt_tx_pma_reset_done_sync; +assign tx_prgdiv_reset_done_out = gt_tx_prgdiv_reset_done_sync; + +wire tx_sel_pll_lock = gt_tx_qpll_sel_reg ? qpll1_lock_in : qpll0_lock_in; + +always_ff @(posedge clk) begin + gt_tx_reset_reg <= 1'b1; + gt_tx_pma_reset_reg <= tx_pma_reset_in; + gt_tx_pcs_reset_reg <= tx_pcs_reset_in; + + gt_tx_prgdiv_reset_reg <= 1'b1; + gt_tx_userrdy_reg <= 1'b0; + + state_reg <= STATE_RESET; + tx_reset_cnt_reg <= '0; + tx_reset_done_reg <= 1'b0; + + case (state_reg) + STATE_RESET: begin + gt_tx_reset_reg <= 1'b1; + gt_tx_prgdiv_reset_reg <= 1'b1; + gt_tx_userrdy_reg <= 1'b0; + + gt_tx_pd_reg <= tx_pd_in; + gt_tx_qpll_sel_reg <= tx_qpll_sel_in; + + state_reg <= STATE_WAIT_LOCK; + end + STATE_WAIT_LOCK: begin + gt_tx_reset_reg <= 1'b1; + gt_tx_prgdiv_reset_reg <= 1'b1; + gt_tx_userrdy_reg <= 1'b0; + + state_reg <= STATE_WAIT_LOCK; + if (tx_sel_pll_lock) begin + // QPLL locked + tx_reset_cnt_reg <= tx_reset_cnt_reg + 1; + if (&tx_reset_cnt_reg) begin + state_reg <= STATE_WAIT_USRCLK; + end + end + end + STATE_WAIT_USRCLK: begin + gt_tx_reset_reg <= 1'b0; + gt_tx_prgdiv_reset_reg <= 1'b0; + gt_tx_userrdy_reg <= 1'b0; + + state_reg <= STATE_WAIT_USRCLK; + if (gt_userclk_tx_active_sync) begin + // user clock running + tx_reset_cnt_reg <= tx_reset_cnt_reg + 1; + if (&tx_reset_cnt_reg) begin + state_reg <= STATE_DONE; + end + end + end + STATE_DONE: begin + gt_tx_reset_reg <= 1'b0; + gt_tx_prgdiv_reset_reg <= 1'b0; + gt_tx_userrdy_reg <= 1'b1; + + tx_reset_done_reg <= gt_tx_reset_done_sync && gt_tx_prgdiv_reset_done_sync; + + state_reg <= STATE_DONE; + end + default: begin + state_reg <= STATE_RESET; + end + endcase + + if (tx_reset_sync || tx_pd_in || !tx_sel_pll_lock || (gt_tx_qpll_sel_reg != tx_qpll_sel_in)) begin + state_reg <= STATE_RESET; + end + + if (rst) begin + gt_tx_reset_reg <= 1'b1; + gt_tx_pma_reset_reg <= 1'b0; + gt_tx_pcs_reset_reg <= 1'b0; + + gt_tx_prgdiv_reset_reg <= 1'b1; + gt_tx_userrdy_reg <= 1'b0; + + gt_tx_pd_reg <= GT_TX_PD; + gt_tx_qpll_sel_reg <= GT_TX_QPLL_SEL; + + state_reg <= STATE_RESET; + tx_reset_done_reg <= 1'b0; + end +end + +endmodule + +`resetall