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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-03 14:22:31 -08:00
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# Taxi Transport Library # Taxi Transport Library
[![Build Status](https://github.com/fpganinja/taxi/workflows/Regression%20Tests/badge.svg?branch=master)](https://github.com/fpganinja/taxi/actions/) [![Regression Tests](https://github.com/fpganinja/taxi/actions/workflows/regression-tests.yml/badge.svg)](https://github.com/fpganinja/taxi/actions/workflows/regression-tests.yml)
AXI, AXI stream, Ethernet, and PCIe components in System Verilog. AXI, AXI stream, Ethernet, and PCIe components in System Verilog.