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axi: Add AXI crossbar 1S wrappers and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
3
src/axi/rtl/taxi_axi_crossbar_1s.f
Normal file
3
src/axi/rtl/taxi_axi_crossbar_1s.f
Normal file
@@ -0,0 +1,3 @@
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taxi_axi_crossbar_1s.sv
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taxi_axi_crossbar_1s_wr.f
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taxi_axi_crossbar_1s_rd.f
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152
src/axi/rtl/taxi_axi_crossbar_1s.sv
Normal file
152
src/axi/rtl/taxi_axi_crossbar_1s.sv
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@@ -0,0 +1,152 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 crossbar
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*/
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module taxi_axi_crossbar_1s #
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(
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Address width in bits for address decoding
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parameter ADDR_W = 32,
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// TODO fix parametrization once verilator issue 5890 is fixed
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// Number of concurrent unique IDs
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parameter S_THREADS = 2,
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// Number of concurrent operations for each slave interface
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// 1 concatenated fields of 32 bits
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parameter S_ACCEPT = 16,
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
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// set to zero for default addressing based on M_ADDR_W
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parameter M_BASE_ADDR = '0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Number of concurrent operations for each master interface
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// M_COUNT concatenated fields of 32 bits
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parameter M_ISSUE = {M_COUNT{32'd4}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}},
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// Slave interface AW channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AW_REG_TYPE = 2'd0,
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// Slave interface W channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_W_REG_TYPE = 2'd0,
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// Slave interface B channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_B_REG_TYPE = 2'd1,
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AR_REG_TYPE = 2'd0,
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_R_REG_TYPE = 2'd2,
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// Master interface AW channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface W channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
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// Master interface B channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4 slave interface
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*/
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taxi_axi_if.wr_slv s_axi_wr,
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taxi_axi_if.rd_slv s_axi_rd,
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/*
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* AXI4 master interfaces
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*/
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taxi_axi_if.wr_mst m_axi_wr[M_COUNT],
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taxi_axi_if.rd_mst m_axi_rd[M_COUNT]
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);
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taxi_axi_crossbar_1s_wr #(
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.M_COUNT(M_COUNT),
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.ADDR_W(ADDR_W),
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.S_THREADS(S_THREADS),
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.S_ACCEPT(S_ACCEPT),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_W(M_ADDR_W),
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.M_ISSUE(M_ISSUE),
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.M_SECURE(M_SECURE),
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.S_AW_REG_TYPE(S_AW_REG_TYPE),
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.S_W_REG_TYPE(S_W_REG_TYPE),
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.S_B_REG_TYPE(S_B_REG_TYPE)
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)
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wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI slave interface
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*/
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.s_axi_wr(s_axi_wr),
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/*
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* AXI master interfaces
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*/
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.m_axi_wr(m_axi_wr)
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);
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taxi_axi_crossbar_1s_rd #(
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.M_COUNT(M_COUNT),
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.ADDR_W(ADDR_W),
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.S_THREADS(S_THREADS),
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.S_ACCEPT(S_ACCEPT),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_W(M_ADDR_W),
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.M_ISSUE(M_ISSUE),
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.M_SECURE(M_SECURE),
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.S_AR_REG_TYPE(S_AR_REG_TYPE),
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.S_R_REG_TYPE(S_R_REG_TYPE)
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)
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rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI slave interface
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*/
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.s_axi_rd(s_axi_rd),
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/*
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* AXI master interfaces
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*/
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.m_axi_rd(m_axi_rd)
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);
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endmodule
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`resetall
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3
src/axi/rtl/taxi_axi_crossbar_1s_rd.f
Normal file
3
src/axi/rtl/taxi_axi_crossbar_1s_rd.f
Normal file
@@ -0,0 +1,3 @@
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taxi_axi_crossbar_1s_rd.sv
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taxi_axi_crossbar_rd.f
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taxi_axi_tie_rd.sv
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130
src/axi/rtl/taxi_axi_crossbar_1s_rd.sv
Normal file
130
src/axi/rtl/taxi_axi_crossbar_1s_rd.sv
Normal file
@@ -0,0 +1,130 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 crossbar
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*/
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module taxi_axi_crossbar_1s_rd #
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(
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Address width in bits for address decoding
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parameter ADDR_W = 32,
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// TODO fix parametrization once verilator issue 5890 is fixed
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// Number of concurrent unique IDs
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parameter S_THREADS = 2,
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// Number of concurrent operations for each slave interface
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// 1 concatenated fields of 32 bits
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parameter S_ACCEPT = 16,
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
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// set to zero for default addressing based on M_ADDR_W
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parameter M_BASE_ADDR = '0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Number of concurrent operations for each master interface
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// M_COUNT concatenated fields of 32 bits
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parameter M_ISSUE = {M_COUNT{32'd4}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}},
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AR_REG_TYPE = 2'd0,
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_R_REG_TYPE = 2'd2,
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4 slave interface
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*/
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taxi_axi_if.rd_slv s_axi_rd,
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/*
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* AXI4 master interfaces
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*/
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taxi_axi_if.rd_mst m_axi_rd[M_COUNT]
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);
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taxi_axi_if #(
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.DATA_W(s_axi_rd.DATA_W),
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.ADDR_W(s_axi_rd.ADDR_W),
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.STRB_W(s_axi_rd.STRB_W),
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.ID_W(s_axi_rd.ID_W),
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.AWUSER_EN(s_axi_rd.AWUSER_EN),
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.AWUSER_W(s_axi_rd.AWUSER_W),
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.WUSER_EN(s_axi_rd.WUSER_EN),
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.WUSER_W(s_axi_rd.WUSER_W),
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.BUSER_EN(s_axi_rd.BUSER_EN),
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.BUSER_W(s_axi_rd.BUSER_W),
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.ARUSER_EN(s_axi_rd.ARUSER_EN),
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.ARUSER_W(s_axi_rd.ARUSER_W),
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.RUSER_EN(s_axi_rd.RUSER_EN),
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.RUSER_W(s_axi_rd.RUSER_W),
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.MAX_BURST_LEN(s_axi_rd.MAX_BURST_LEN),
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.NARROW_BURST_EN(s_axi_rd.NARROW_BURST_EN)
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)
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s_axi_rd_int[1]();
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taxi_axi_tie_rd
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tie_inst (
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.s_axi_rd(s_axi_rd),
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.m_axi_rd(s_axi_rd_int[0])
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);
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taxi_axi_crossbar_rd #(
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.S_COUNT(1),
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.M_COUNT(M_COUNT),
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.ADDR_W(ADDR_W),
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.S_THREADS(S_THREADS),
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.S_ACCEPT(S_ACCEPT),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_W(M_ADDR_W),
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.M_ISSUE(M_ISSUE),
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.M_SECURE(M_SECURE),
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.S_AR_REG_TYPE(S_AR_REG_TYPE),
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.S_R_REG_TYPE(S_R_REG_TYPE)
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)
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rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI slave interface
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*/
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.s_axi_rd(s_axi_rd_int),
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/*
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* AXI master interfaces
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*/
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.m_axi_rd(m_axi_rd)
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);
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endmodule
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`resetall
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3
src/axi/rtl/taxi_axi_crossbar_1s_wr.f
Normal file
3
src/axi/rtl/taxi_axi_crossbar_1s_wr.f
Normal file
@@ -0,0 +1,3 @@
|
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taxi_axi_crossbar_1s_wr.sv
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taxi_axi_crossbar_wr.f
|
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taxi_axi_tie_wr.sv
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137
src/axi/rtl/taxi_axi_crossbar_1s_wr.sv
Normal file
137
src/axi/rtl/taxi_axi_crossbar_1s_wr.sv
Normal file
@@ -0,0 +1,137 @@
|
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// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
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Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
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/*
|
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* AXI4 crossbar
|
||||
*/
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module taxi_axi_crossbar_1s_wr #
|
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(
|
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// Number of AXI outputs (master interfaces)
|
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parameter M_COUNT = 4,
|
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// Address width in bits for address decoding
|
||||
parameter ADDR_W = 32,
|
||||
// TODO fix parametrization once verilator issue 5890 is fixed
|
||||
// Number of concurrent unique IDs
|
||||
parameter S_THREADS = 2,
|
||||
// Number of concurrent operations for each slave interface
|
||||
// 1 concatenated fields of 32 bits
|
||||
parameter S_ACCEPT = 16,
|
||||
// Number of regions per master interface
|
||||
parameter M_REGIONS = 1,
|
||||
// Master interface base addresses
|
||||
// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
|
||||
// set to zero for default addressing based on M_ADDR_W
|
||||
parameter M_BASE_ADDR = '0,
|
||||
// Master interface address widths
|
||||
// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
|
||||
parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
|
||||
// Number of concurrent operations for each master interface
|
||||
// M_COUNT concatenated fields of 32 bits
|
||||
parameter M_ISSUE = {M_COUNT{32'd4}},
|
||||
// Secure master (fail operations based on awprot/arprot)
|
||||
// M_COUNT bits
|
||||
parameter M_SECURE = {M_COUNT{1'b0}},
|
||||
// Slave interface AW channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_AW_REG_TYPE = 2'd0,
|
||||
// Slave interface W channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_W_REG_TYPE = 2'd0,
|
||||
// Slave interface B channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter S_B_REG_TYPE = 2'd1,
|
||||
// Master interface AW channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
|
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// Master interface W channel register type (output)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
|
||||
// Master interface B channel register type (input)
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter M_B_REG_TYPE = {M_COUNT{2'd0}}
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
taxi_axi_if.wr_slv s_axi_wr,
|
||||
|
||||
/*
|
||||
* AXI4 master interfaces
|
||||
*/
|
||||
taxi_axi_if.wr_mst m_axi_wr[M_COUNT]
|
||||
);
|
||||
|
||||
taxi_axi_if #(
|
||||
.DATA_W(s_axi_wr.DATA_W),
|
||||
.ADDR_W(s_axi_wr.ADDR_W),
|
||||
.STRB_W(s_axi_wr.STRB_W),
|
||||
.ID_W(s_axi_wr.ID_W),
|
||||
.AWUSER_EN(s_axi_wr.AWUSER_EN),
|
||||
.AWUSER_W(s_axi_wr.AWUSER_W),
|
||||
.WUSER_EN(s_axi_wr.WUSER_EN),
|
||||
.WUSER_W(s_axi_wr.WUSER_W),
|
||||
.BUSER_EN(s_axi_wr.BUSER_EN),
|
||||
.BUSER_W(s_axi_wr.BUSER_W),
|
||||
.ARUSER_EN(s_axi_wr.ARUSER_EN),
|
||||
.ARUSER_W(s_axi_wr.ARUSER_W),
|
||||
.RUSER_EN(s_axi_wr.RUSER_EN),
|
||||
.RUSER_W(s_axi_wr.RUSER_W),
|
||||
.MAX_BURST_LEN(s_axi_wr.MAX_BURST_LEN),
|
||||
.NARROW_BURST_EN(s_axi_wr.NARROW_BURST_EN)
|
||||
)
|
||||
s_axi_wr_int[1]();
|
||||
|
||||
taxi_axi_tie_wr
|
||||
tie_inst (
|
||||
.s_axi_wr(s_axi_wr),
|
||||
.m_axi_wr(s_axi_wr_int[0])
|
||||
);
|
||||
|
||||
taxi_axi_crossbar_wr #(
|
||||
.S_COUNT(1),
|
||||
.M_COUNT(M_COUNT),
|
||||
.ADDR_W(ADDR_W),
|
||||
.S_THREADS(S_THREADS),
|
||||
.S_ACCEPT(S_ACCEPT),
|
||||
.M_REGIONS(M_REGIONS),
|
||||
.M_BASE_ADDR(M_BASE_ADDR),
|
||||
.M_ADDR_W(M_ADDR_W),
|
||||
.M_ISSUE(M_ISSUE),
|
||||
.M_SECURE(M_SECURE),
|
||||
.S_AW_REG_TYPE(S_AW_REG_TYPE),
|
||||
.S_W_REG_TYPE(S_W_REG_TYPE),
|
||||
.S_B_REG_TYPE(S_B_REG_TYPE)
|
||||
)
|
||||
wr_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI slave interface
|
||||
*/
|
||||
.s_axi_wr(s_axi_wr_int),
|
||||
|
||||
/*
|
||||
* AXI master interfaces
|
||||
*/
|
||||
.m_axi_wr(m_axi_wr)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user