diff --git a/src/pcie/rtl/taxi_pcie_msix_apb.sv b/src/pcie/rtl/taxi_pcie_msix_apb.sv index 157597a..4c4679e 100644 --- a/src/pcie/rtl/taxi_pcie_msix_apb.sv +++ b/src/pcie/rtl/taxi_pcie_msix_apb.sv @@ -71,7 +71,8 @@ localparam PBA_ADDR_W_INT = PBA_ADDR_W > 0 ? PBA_ADDR_W : 1; localparam INDEX_SHIFT = $clog2(64/8); localparam WORD_SELECT_SHIFT = $clog2(APB_DATA_W/8); -localparam WORD_SELECT_W = 64 > APB_DATA_W ? $clog2((64+7)/8) - $clog2(APB_DATA_W/8) : 0; +localparam WORD_SELECT_W = 64 > APB_DATA_W ? $clog2((64+7)/8) - $clog2(APB_DATA_W/8) : 1; +localparam RATIO = 64/APB_DATA_W; // bus width assertions if (APB_STRB_W * 8 != APB_DATA_W) @@ -381,7 +382,7 @@ always_comb begin tbl_apb_mem_rd_en = 1'b0; tbl_apb_mem_wr_en = 1'b0; tbl_apb_mem_wr_be = 8'(s_apb.pstrb << (s_apb_paddr_word * APB_STRB_W)); - tbl_apb_mem_wr_data = {2**WORD_SELECT_W{s_apb.pwdata}}; + tbl_apb_mem_wr_data = {RATIO{s_apb.pwdata}}; pba_apb_mem_rd_en = 1'b0; tbl_rd_data_valid_next = 1'b0; diff --git a/src/pcie/rtl/taxi_pcie_msix_axil.sv b/src/pcie/rtl/taxi_pcie_msix_axil.sv index 27ae3ff..15f5b77 100644 --- a/src/pcie/rtl/taxi_pcie_msix_axil.sv +++ b/src/pcie/rtl/taxi_pcie_msix_axil.sv @@ -72,7 +72,8 @@ localparam PBA_ADDR_W_INT = PBA_ADDR_W > 0 ? PBA_ADDR_W : 1; localparam INDEX_SHIFT = $clog2(64/8); localparam WORD_SELECT_SHIFT = $clog2(AXIL_DATA_W/8); -localparam WORD_SELECT_W = 64 > AXIL_DATA_W ? $clog2((64+7)/8) - $clog2(AXIL_DATA_W/8) : 0; +localparam WORD_SELECT_W = 64 > AXIL_DATA_W ? $clog2((64+7)/8) - $clog2(AXIL_DATA_W/8) : 1; +localparam RATIO = 64/AXIL_DATA_W; // bus width assertions if (AXIL_STRB_W * 8 != AXIL_DATA_W) @@ -399,7 +400,7 @@ always_comb begin tbl_axil_mem_rd_en = 1'b0; tbl_axil_mem_wr_en = 1'b0; tbl_axil_mem_wr_be = 8'(s_axil_wr.wstrb << (s_axil_awaddr_word * AXIL_STRB_W)); - tbl_axil_mem_wr_data = {2**WORD_SELECT_W{s_axil_wr.wdata}}; + tbl_axil_mem_wr_data = {RATIO{s_axil_wr.wdata}}; pba_axil_mem_rd_en = 1'b0; tbl_rd_data_valid_next = tbl_rd_data_valid_reg;