From 8e416499f1ae0528a45190520dcb9040a4b9b6ea Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 14 Apr 2026 23:53:29 -0700 Subject: [PATCH] eth: Fix HTG-9200 XDC Signed-off-by: Alex Forencich --- src/eth/example/HTG9200/fpga/syn/fpga.xdc | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/src/eth/example/HTG9200/fpga/syn/fpga.xdc b/src/eth/example/HTG9200/fpga/syn/fpga.xdc index 16a1b30..4857df4 100644 --- a/src/eth/example/HTG9200/fpga/syn/fpga.xdc +++ b/src/eth/example/HTG9200/fpga/syn/fpga.xdc @@ -38,20 +38,3 @@ create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p] # 80 MHz EMCCLK #set_property -dict {LOC AL27 IOSTANDARD LVCMOS18} [get_ports emc_clk] #create_clock -period 12.5 -name emc_clk [get_ports emc_clk] - -# PLL control -set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] -set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] -set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] -set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_lol_n}] -set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] -set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] -set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] - -#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] -#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] - -set_false_path -to [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] -set_output_delay 0 [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] -set_false_path -from [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] -set_input_delay 0 [get_ports {clk_gty2_intr_n clk_gty2_lol_n}]