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https://github.com/fpganinja/taxi.git
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lfsr: Add parametrizable LFSR module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
313
rtl/lfsr/taxi_lfsr.sv
Normal file
313
rtl/lfsr/taxi_lfsr.sv
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@@ -0,0 +1,313 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Parametrizable combinatorial parallel LFSR/CRC
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*/
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module taxi_lfsr #
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(
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// width of LFSR
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parameter LFSR_W = 31,
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// LFSR polynomial
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parameter logic [LFSR_W-1:0] LFSR_POLY = 31'h10000001,
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// LFSR configuration: 0 for Fibonacci (PRBS), 1 for Galois (CRC)
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parameter logic LFSR_GALOIS = 1'b0,
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// LFSR feed forward enable
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parameter logic LFSR_FEED_FORWARD = 1'b0,
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// bit-reverse input and output
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parameter logic REVERSE = 1'b0,
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// width of data input
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parameter DATA_W = 8
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)
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(
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input wire logic [DATA_W-1:0] data_in,
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input wire logic [LFSR_W-1:0] state_in,
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output wire logic [DATA_W-1:0] data_out,
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output wire logic [LFSR_W-1:0] state_out
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);
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/*
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Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR
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next state computation, shifting DATA_W bits per pass through the module. Input data
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is XORed with LFSR feedback path, tie data_in to zero if this is not required.
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Works in two parts: statically computes a set of bit masks, then uses these bit masks to
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select bits for XORing to compute the next state.
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Ports:
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data_in
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Data bits to be shifted through the LFSR (DATA_W bits)
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state_in
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LFSR/CRC current state input (LFSR_W bits)
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data_out
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Data bits shifted out of LFSR (DATA_W bits)
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state_out
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LFSR/CRC next state output (LFSR_W bits)
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Parameters:
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LFSR_W
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Specify width of LFSR/CRC register
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LFSR_POLY
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Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
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x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
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would be represented as
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32'h04c11db7
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Note that the largest term (x^32) is suppressed. This term is generated automatically based
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on LFSR_W.
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LFSR_GALOIS
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Specify the LFSR configuration, either Fibonacci (0) or Galois (1). Fibonacci is generally used
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for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
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scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
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generators and checkers.
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Fibonacci style (example for 64b66b scrambler, 0x8000000001)
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DIN (LSB first)
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|
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V
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(+)<---------------------------(+)<-----------------------------.
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| ^ |
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| .----. .----. .----. | .----. .----. .----. |
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+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
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| '----' '----' '----' '----' '----' '----'
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V
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DOUT
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Galois style (example for CRC16, 0x8005)
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,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
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| | | ^
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| .----. .----. V .----. .----. V .----. |
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`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
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'----' '----' '----' '----' '----'
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LFSR_FEED_FORWARD
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Generate feed forward instead of feed back LFSR. Enable this for PRBS checking and self-
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synchronous descrambling.
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Fibonacci feed-forward style (example for 64b66b descrambler, 0x8000000001)
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DIN (LSB first)
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|
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| .----. .----. .----. .----. .----. .----.
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+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--.
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| '----' '----' '----' | '----' '----' '----' |
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| V |
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(+)<---------------------------(+)------------------------------'
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V
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DOUT
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Galois feed-forward style
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,-------------------+-------------------------+------------+--- DIN (MSB first)
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| | | |
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| .----. .----. V .----. .----. V .----. V
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`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |->(+)-> DOUT
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'----' '----' '----' '----' '----'
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REVERSE
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Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
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DATA_W
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Specify width of input and output data bus. The module will perform one shift per input
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data bit, so if the input data bus is not required tie data_in to zero and set DATA_W
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to the required number of shifts per clock cycle.
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Settings for common LFSR/CRC implementations:
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Name Configuration Length Polynomial Initial value Notes
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CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
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CRC16-CCITT Galois 16 16'h1021 16'h1d0f
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CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
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CRC32C Galois, bit-reverse 32 32'h1edc6f41 32'hffffffff iSCSI, Intel CRC32 instruction; invert final output
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PRBS6 Fibonacci 6 6'h21 any
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PRBS7 Fibonacci 7 7'h41 any
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PRBS9 Fibonacci 9 9'h021 any ITU V.52
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PRBS10 Fibonacci 10 10'h081 any ITU
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PRBS11 Fibonacci 11 11'h201 any ITU O.152
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PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
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PRBS17 Fibonacci 17 17'h04001 any
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PRBS20 Fibonacci 20 20'h00009 any ITU V.57
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PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
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PRBS29 Fibonacci, inverted 29 29'h08000001 any
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PRBS31 Fibonacci, inverted 31 31'h10000001 any
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64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
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128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
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*/
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function [LFSR_W+DATA_W-1:0][LFSR_W+DATA_W-1:0] lfsr_mask();
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logic [LFSR_W-1:0] lfsr_mask_state[LFSR_W-1:0];
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logic [DATA_W-1:0] lfsr_mask_data[LFSR_W-1:0];
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logic [LFSR_W-1:0] output_mask_state[DATA_W-1:0];
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logic [DATA_W-1:0] output_mask_data[DATA_W-1:0];
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logic [LFSR_W-1:0] state_val;
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logic [DATA_W-1:0] data_val;
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logic [DATA_W-1:0] data_mask;
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// init bit masks
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for (integer i = 0; i < LFSR_W; i = i + 1) begin
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lfsr_mask_state[i] = '0;
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lfsr_mask_state[i][i] = 1'b1;
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lfsr_mask_data[i] = '0;
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end
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for (integer i = 0; i < DATA_W; i = i + 1) begin
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output_mask_state[i] = '0;
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if (i < LFSR_W) begin
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output_mask_state[i][i] = 1'b1;
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end
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output_mask_data[i] = '0;
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end
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// simulate shift register
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if (LFSR_GALOIS) begin
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// Galois configuration
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for (data_mask = {1'b1, {DATA_W-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
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// determine shift in value
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// current value in last FF, XOR with input data bit (MSB first)
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state_val = lfsr_mask_state[LFSR_W-1];
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data_val = lfsr_mask_data[LFSR_W-1];
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data_val = data_val ^ data_mask;
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// shift
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for (integer j = LFSR_W-1; j > 0; j = j - 1) begin
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lfsr_mask_state[j] = lfsr_mask_state[j-1];
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lfsr_mask_data[j] = lfsr_mask_data[j-1];
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end
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for (integer j = DATA_W-1; j > 0; j = j - 1) begin
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output_mask_state[j] = output_mask_state[j-1];
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output_mask_data[j] = output_mask_data[j-1];
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end
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output_mask_state[0] = state_val;
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output_mask_data[0] = data_val;
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if (LFSR_FEED_FORWARD) begin
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// only shift in new input data
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state_val = '0;
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data_val = data_mask;
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end
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lfsr_mask_state[0] = state_val;
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lfsr_mask_data[0] = data_val;
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// add XOR inputs at correct indicies
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for (integer j = 1; j < LFSR_W; j = j + 1) begin
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if (LFSR_POLY[j]) begin
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lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
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lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
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end
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end
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end
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end else begin
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// Fibonacci configuration
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for (data_mask = {1'b1, {DATA_W-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
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// determine shift in value
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// current value in last FF, XOR with input data bit (MSB first)
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state_val = lfsr_mask_state[LFSR_W-1];
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data_val = lfsr_mask_data[LFSR_W-1];
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data_val = data_val ^ data_mask;
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// add XOR inputs from correct indicies
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for (integer j = 1; j < LFSR_W; j = j + 1) begin
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if (LFSR_POLY[j]) begin
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state_val = lfsr_mask_state[j-1] ^ state_val;
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data_val = lfsr_mask_data[j-1] ^ data_val;
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end
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end
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// shift
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for (integer j = LFSR_W-1; j > 0; j = j - 1) begin
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lfsr_mask_state[j] = lfsr_mask_state[j-1];
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lfsr_mask_data[j] = lfsr_mask_data[j-1];
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end
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for (integer j = DATA_W-1; j > 0; j = j - 1) begin
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output_mask_state[j] = output_mask_state[j-1];
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output_mask_data[j] = output_mask_data[j-1];
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end
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output_mask_state[0] = state_val;
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output_mask_data[0] = data_val;
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if (LFSR_FEED_FORWARD) begin
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// only shift in new input data
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state_val = '0;
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data_val = data_mask;
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end
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lfsr_mask_state[0] = state_val;
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lfsr_mask_data[0] = data_val;
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end
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end
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if (REVERSE) begin
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// output reversed
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for (integer i = 0; i < LFSR_W; i = i + 1) begin
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for (integer j = 0; j < LFSR_W; j = j + 1) begin
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lfsr_mask[i][j] = lfsr_mask_state[LFSR_W-i-1][LFSR_W-j-1];
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end
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for (integer j = 0; j < DATA_W; j = j + 1) begin
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lfsr_mask[i][j+LFSR_W] = lfsr_mask_data[LFSR_W-i-1][DATA_W-j-1];
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end
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end
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for (integer i = 0; i < DATA_W; i = i + 1) begin
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for (integer j = 0; j < LFSR_W; j = j + 1) begin
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lfsr_mask[i+LFSR_W][j] = output_mask_state[DATA_W-i-1][LFSR_W-j-1];
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end
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for (integer j = 0; j < DATA_W; j = j + 1) begin
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lfsr_mask[i+LFSR_W][j+LFSR_W] = output_mask_data[DATA_W-i-1][DATA_W-j-1];
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end
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end
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end else begin
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// output normal
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for (integer i = 0; i < LFSR_W; i = i + 1) begin
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lfsr_mask[i] = {lfsr_mask_data[i], lfsr_mask_state[i]};
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end
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for (integer i = 0; i < DATA_W; i = i + 1) begin
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lfsr_mask[i+LFSR_W] = {output_mask_data[i], output_mask_state[i]};
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end
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end
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endfunction
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wire [LFSR_W+DATA_W-1:0][LFSR_W+DATA_W-1:0] mask = lfsr_mask();
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for (genvar n = 0; n < LFSR_W; n = n + 1) begin : lfsr_state
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assign state_out[n] = ^({data_in, state_in} & mask[n]);
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end
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for (genvar n = 0; n < DATA_W; n = n + 1) begin : lfsr_data
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assign data_out[n] = ^({data_in, state_in} & mask[n+LFSR_W]);
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end
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endmodule
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`resetall
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50
tb/lfsr/taxi_lfsr/Makefile
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50
tb/lfsr/taxi_lfsr/Makefile
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@@ -0,0 +1,50 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2023-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_lfsr
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = $(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_LFSR_W ?= 32
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export PARAM_LFSR_POLY ?= "32'h4c11db7"
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export PARAM_LFSR_GALOIS ?= "1'b1"
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export PARAM_LFSR_FEED_FORWARD ?= "1'b0"
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export PARAM_REVERSE ?= "1'b1"
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export PARAM_DATA_W ?= 8
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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238
tb/lfsr/taxi_lfsr/test_taxi_lfsr.py
Normal file
238
tb/lfsr/taxi_lfsr/test_taxi_lfsr.py
Normal file
@@ -0,0 +1,238 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2023-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import zlib
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import pytest
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import cocotb_test.simulator
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import cocotb
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from cocotb.triggers import Timer
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from cocotb.regression import TestFactory
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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dut.data_in.setimmediatevalue(0)
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dut.state_in.setimmediatevalue(0)
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def chunks(lst, n, padvalue=None):
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return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
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def crc32(data):
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return zlib.crc32(data) & 0xffffffff
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def crc32c(data, crc=0xffffffff, poly=0x82f63b78):
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for d in data:
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crc = crc ^ d
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for bit in range(0, 8):
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if crc & 1:
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crc = (crc >> 1) ^ poly
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else:
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crc = crc >> 1
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return ~crc & 0xffffffff
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async def run_test_crc(dut, ref_crc):
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data_width = len(dut.data_in)
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byte_lanes = data_width // 8
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state_width = len(dut.state_in)
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state_mask = 2**state_width-1
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await Timer(10, 'ns')
|
||||
|
||||
block = bytes([(x+1)*0x11 for x in range(byte_lanes)])
|
||||
|
||||
dut.state_in.value = state_mask
|
||||
dut.data_in.value = int.from_bytes(block, 'little')
|
||||
await Timer(10, 'ns')
|
||||
|
||||
val = ~dut.state_out.value.integer & state_mask
|
||||
ref = ref_crc(block)
|
||||
|
||||
tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
|
||||
|
||||
assert val == ref
|
||||
|
||||
await Timer(10, 'ns')
|
||||
|
||||
block = bytearray(itertools.islice(itertools.cycle(range(256)), 1024))
|
||||
|
||||
dut.state_in.value = state_mask
|
||||
for b in chunks(block, byte_lanes):
|
||||
dut.data_in.value = int.from_bytes(b, 'little')
|
||||
await Timer(10, 'ns')
|
||||
dut.state_in.value = dut.state_out.value
|
||||
|
||||
val = ~int(dut.state_out.value) & state_mask
|
||||
ref = ref_crc(block)
|
||||
|
||||
tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
|
||||
|
||||
assert val == ref
|
||||
|
||||
await Timer(10, 'ns')
|
||||
|
||||
|
||||
def prbs9(state=0x1ff):
|
||||
while True:
|
||||
for i in range(8):
|
||||
if bool(state & 0x10) ^ bool(state & 0x100):
|
||||
state = ((state & 0xff) << 1) | 1
|
||||
else:
|
||||
state = (state & 0xff) << 1
|
||||
yield ~state & 0xff
|
||||
|
||||
|
||||
def prbs31(state=0x7fffffff):
|
||||
while True:
|
||||
for i in range(8):
|
||||
if bool(state & 0x08000000) ^ bool(state & 0x40000000):
|
||||
state = ((state & 0x3fffffff) << 1) | 1
|
||||
else:
|
||||
state = (state & 0x3fffffff) << 1
|
||||
yield ~state & 0xff
|
||||
|
||||
|
||||
async def run_test_prbs(dut, ref_prbs):
|
||||
|
||||
data_width = len(dut.data_in)
|
||||
byte_lanes = data_width // 8
|
||||
data_mask = 2**data_width-1
|
||||
|
||||
state_width = len(dut.state_in)
|
||||
state_mask = 2**state_width-1
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await Timer(10, 'ns')
|
||||
|
||||
dut.state_in.value = state_mask
|
||||
dut.data_in.value = 0
|
||||
gen = chunks(ref_prbs(), byte_lanes)
|
||||
|
||||
await Timer(10, 'ns')
|
||||
|
||||
for i in range(512):
|
||||
ref = int.from_bytes(bytes(next(gen)), 'big')
|
||||
val = ~int(dut.data_out.value) & data_mask
|
||||
|
||||
tb.log.info("PRBS: 0x%x (ref: 0x%x)", val, ref)
|
||||
|
||||
assert ref == val
|
||||
|
||||
dut.state_in.value = dut.state_out.value
|
||||
|
||||
await Timer(10, 'ns')
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
if cocotb.top.LFSR_POLY.value == 0x4c11db7:
|
||||
factory = TestFactory(run_test_crc)
|
||||
factory.add_option("ref_crc", [crc32])
|
||||
factory.generate_tests()
|
||||
|
||||
if cocotb.top.LFSR_POLY.value == 0x1edc6f41:
|
||||
factory = TestFactory(run_test_crc)
|
||||
factory.add_option("ref_crc", [crc32c])
|
||||
factory.generate_tests()
|
||||
|
||||
if cocotb.top.LFSR_POLY.value == 0x021:
|
||||
factory = TestFactory(run_test_prbs)
|
||||
factory.add_option("ref_prbs", [prbs9])
|
||||
factory.generate_tests()
|
||||
|
||||
if cocotb.top.LFSR_POLY.value == 0x10000001:
|
||||
factory = TestFactory(run_test_prbs)
|
||||
factory.add_option("ref_prbs", [prbs31])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_galois", "reverse", "data_w"), [
|
||||
(32, "32'h4c11db7", 1, 1, 8),
|
||||
(32, "32'h4c11db7", 1, 1, 64),
|
||||
(32, "32'h1edc6f41", 1, 1, 8),
|
||||
(32, "32'h1edc6f41", 1, 1, 64),
|
||||
(9, "9'h021", 0, 0, 8),
|
||||
(9, "9'h021", 0, 0, 64),
|
||||
(31, "31'h10000001", 0, 0, 8),
|
||||
(31, "31'h10000001", 0, 0, 64),
|
||||
])
|
||||
def test_taxi_lfsr(request, lfsr_w, lfsr_poly, lfsr_galois, reverse, data_w):
|
||||
dut = "taxi_lfsr"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, "lfsr", f"{dut}.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['LFSR_W'] = lfsr_w
|
||||
parameters['LFSR_POLY'] = lfsr_poly
|
||||
parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
|
||||
parameters['LFSR_FEED_FORWARD'] = "1'b0"
|
||||
parameters['REVERSE'] = f"1'b{reverse}"
|
||||
parameters['DATA_W'] = data_w
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user