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eth: Add taxi_axis_if to MAC file list files

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-11 15:54:15 -08:00
parent 2616e3f3e3
commit 8f8572bdee
10 changed files with 4 additions and 6 deletions
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1
rtl/eth/taxi_eth_mac_10g.f
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@@ -8,3 +8,4 @@ taxi_mac_ctrl_rx.sv
taxi_mac_pause_ctrl_tx.sv taxi_mac_pause_ctrl_tx.sv
taxi_mac_pause_ctrl_rx.sv taxi_mac_pause_ctrl_rx.sv
../lfsr/taxi_lfsr.sv ../lfsr/taxi_lfsr.sv
../axis/taxi_axis_if.sv

1
rtl/eth/taxi_eth_mac_1g.f
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@@ -6,3 +6,4 @@ taxi_mac_ctrl_rx.sv
taxi_mac_pause_ctrl_tx.sv taxi_mac_pause_ctrl_tx.sv
taxi_mac_pause_ctrl_rx.sv taxi_mac_pause_ctrl_rx.sv
../lfsr/taxi_lfsr.sv ../lfsr/taxi_lfsr.sv
../axis/taxi_axis_if.sv

1
rtl/eth/taxi_eth_mac_phy_10g_rx.f
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@@ -2,3 +2,4 @@ taxi_eth_mac_phy_10g_rx.sv
taxi_eth_phy_10g_rx_if.f taxi_eth_phy_10g_rx_if.f
taxi_axis_baser_rx_64.sv taxi_axis_baser_rx_64.sv
../lfsr/taxi_lfsr.sv ../lfsr/taxi_lfsr.sv
../axis/taxi_axis_if.sv

1
rtl/eth/taxi_eth_mac_phy_10g_tx.f
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@@ -2,3 +2,4 @@ taxi_eth_mac_phy_10g_tx.sv
taxi_eth_phy_10g_tx_if.f taxi_eth_phy_10g_tx_if.f
taxi_axis_baser_tx_64.sv taxi_axis_baser_tx_64.sv
../lfsr/taxi_lfsr.sv ../lfsr/taxi_lfsr.sv
../axis/taxi_axis_if.sv

1
tb/eth/taxi_eth_mac_10g/Makefile
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@@ -20,7 +20,6 @@ MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL) TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f
VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
# handle file list files # handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

1
tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py
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@@ -717,7 +717,6 @@ def test_taxi_eth_mac_10g(request, data_w, dic_en, pfc_en):
verilog_sources = [ verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"), os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, "eth", f"{dut}.f"), os.path.join(rtl_dir, "eth", f"{dut}.f"),
os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
] ]
verilog_sources = process_f_files(verilog_sources) verilog_sources = process_f_files(verilog_sources)

1
tb/eth/taxi_eth_mac_1g/Makefile
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@@ -20,7 +20,6 @@ MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL) TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f
VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
# handle file list files # handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

1
tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py
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@@ -704,7 +704,6 @@ def test_taxi_eth_mac_1g(request, pfc_en):
verilog_sources = [ verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"), os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, "eth", f"{dut}.f"), os.path.join(rtl_dir, "eth", f"{dut}.f"),
os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
] ]
verilog_sources = process_f_files(verilog_sources) verilog_sources = process_f_files(verilog_sources)

1
tb/eth/taxi_eth_mac_phy_10g/Makefile
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@@ -20,7 +20,6 @@ MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL) TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f
VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
# handle file list files # handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

1
tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py
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@@ -743,7 +743,6 @@ def test_taxi_eth_mac_phy_10g(request, data_w, dic_en, pfc_en):
verilog_sources = [ verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"), os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, "eth", f"{dut}.f"), os.path.join(rtl_dir, "eth", f"{dut}.f"),
os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
] ]
verilog_sources = process_f_files(verilog_sources) verilog_sources = process_f_files(verilog_sources)