From 900483d0cde0d00a4d628ec1a27c08bef4638626 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 23 Dec 2025 17:46:13 -0800 Subject: [PATCH] axi: Add AXI-lite crossbar 1S wrappers and testbench Signed-off-by: Alex Forencich --- src/axi/rtl/taxi_axil_crossbar_1s.f | 3 + src/axi/rtl/taxi_axil_crossbar_1s.sv | 148 ++++++++++ src/axi/rtl/taxi_axil_crossbar_1s_rd.f | 3 + src/axi/rtl/taxi_axil_crossbar_1s_rd.sv | 124 +++++++++ src/axi/rtl/taxi_axil_crossbar_1s_wr.f | 3 + src/axi/rtl/taxi_axil_crossbar_1s_wr.sv | 131 +++++++++ src/axi/tb/taxi_axil_crossbar_1s/Makefile | 66 +++++ .../test_taxi_axil_crossbar_1s.py | 254 ++++++++++++++++++ .../test_taxi_axil_crossbar_1s.sv | 129 +++++++++ 9 files changed, 861 insertions(+) create mode 100644 src/axi/rtl/taxi_axil_crossbar_1s.f create mode 100644 src/axi/rtl/taxi_axil_crossbar_1s.sv create mode 100644 src/axi/rtl/taxi_axil_crossbar_1s_rd.f create mode 100644 src/axi/rtl/taxi_axil_crossbar_1s_rd.sv create mode 100644 src/axi/rtl/taxi_axil_crossbar_1s_wr.f create mode 100644 src/axi/rtl/taxi_axil_crossbar_1s_wr.sv create mode 100644 src/axi/tb/taxi_axil_crossbar_1s/Makefile create mode 100644 src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.py create mode 100644 src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.sv diff --git a/src/axi/rtl/taxi_axil_crossbar_1s.f b/src/axi/rtl/taxi_axil_crossbar_1s.f new file mode 100644 index 0000000..a7b26e2 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_1s.f @@ -0,0 +1,3 @@ +taxi_axil_crossbar_1s.sv +taxi_axil_crossbar_1s_wr.f +taxi_axil_crossbar_1s_rd.f diff --git a/src/axi/rtl/taxi_axil_crossbar_1s.sv b/src/axi/rtl/taxi_axil_crossbar_1s.sv new file mode 100644 index 0000000..f7a98e6 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_1s.sv @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite crossbar + */ +module taxi_axil_crossbar_1s # +( + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of concurrent operations for each slave interface + // 1 concatenated fields of 32 bits + parameter S_ACCEPT = 32'd16, + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Number of concurrent operations for each master interface + // M_COUNT concatenated fields of 32 bits + parameter M_ISSUE = {M_COUNT{32'd16}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}}, + // Slave interface AW channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AW_REG_TYPE = 2'd0, + // Slave interface W channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_W_REG_TYPE = 2'd0, + // Slave interface B channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_B_REG_TYPE = 2'd1, + // Slave interface AR channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AR_REG_TYPE = 2'd0, + // Slave interface R channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_R_REG_TYPE = 2'd2, + // Master interface AW channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface W channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, + // Master interface B channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, + // Master interface AR channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface R channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_R_REG_TYPE = {M_COUNT{2'd0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-lite slave interface + */ + taxi_axil_if.wr_slv s_axil_wr, + taxi_axil_if.rd_slv s_axil_rd, + + /* + * AXI4-lite master interfaces + */ + taxi_axil_if.wr_mst m_axil_wr[M_COUNT], + taxi_axil_if.rd_mst m_axil_rd[M_COUNT] +); + +taxi_axil_crossbar_1s_wr #( + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AW_REG_TYPE(S_AW_REG_TYPE), + .S_W_REG_TYPE(S_W_REG_TYPE), + .S_B_REG_TYPE(S_B_REG_TYPE) +) +wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI lite slave interface + */ + .s_axil_wr(s_axil_wr), + + /* + * AXI lite master interfaces + */ + .m_axil_wr(m_axil_wr) +); + +taxi_axil_crossbar_1s_rd #( + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AR_REG_TYPE(S_AR_REG_TYPE), + .S_R_REG_TYPE(S_R_REG_TYPE) +) +rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI lite slave interface + */ + .s_axil_rd(s_axil_rd), + + /* + * AXI lite master interfaces + */ + .m_axil_rd(m_axil_rd) +); + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axil_crossbar_1s_rd.f b/src/axi/rtl/taxi_axil_crossbar_1s_rd.f new file mode 100644 index 0000000..30e6ab7 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_1s_rd.f @@ -0,0 +1,3 @@ +taxi_axil_crossbar_1s_rd.sv +taxi_axil_crossbar_rd.f +taxi_axil_tie_rd.sv diff --git a/src/axi/rtl/taxi_axil_crossbar_1s_rd.sv b/src/axi/rtl/taxi_axil_crossbar_1s_rd.sv new file mode 100644 index 0000000..1a380d4 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_1s_rd.sv @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite crossbar + */ +module taxi_axil_crossbar_1s_rd # +( + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of concurrent operations for each slave interface + // 1 concatenated fields of 32 bits + parameter S_ACCEPT = 32'd16, + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Number of concurrent operations for each master interface + // M_COUNT concatenated fields of 32 bits + parameter M_ISSUE = {M_COUNT{32'd16}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}}, + // Slave interface AR channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AR_REG_TYPE = 2'd0, + // Slave interface R channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_R_REG_TYPE = 2'd2, + // Master interface AR channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface R channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_R_REG_TYPE = {M_COUNT{2'd0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-lite slave interface + */ + taxi_axil_if.rd_slv s_axil_rd, + + /* + * AXI4-lite master interfaces + */ + taxi_axil_if.rd_mst m_axil_rd[M_COUNT] +); + +taxi_axil_if #( + .DATA_W(s_axil_rd.DATA_W), + .ADDR_W(s_axil_rd.ADDR_W), + .STRB_W(s_axil_rd.STRB_W), + .AWUSER_EN(s_axil_rd.AWUSER_EN), + .AWUSER_W(s_axil_rd.AWUSER_W), + .WUSER_EN(s_axil_rd.WUSER_EN), + .WUSER_W(s_axil_rd.WUSER_W), + .BUSER_EN(s_axil_rd.BUSER_EN), + .BUSER_W(s_axil_rd.BUSER_W), + .ARUSER_EN(s_axil_rd.ARUSER_EN), + .ARUSER_W(s_axil_rd.ARUSER_W), + .RUSER_EN(s_axil_rd.RUSER_EN), + .RUSER_W(s_axil_rd.RUSER_W) +) +s_axil_rd_int[1](); + +taxi_axil_tie_rd +tie_inst ( + .s_axil_rd(s_axil_rd), + .m_axil_rd(s_axil_rd_int[0]) +); + +taxi_axil_crossbar_rd #( + .S_COUNT(1), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AR_REG_TYPE(S_AR_REG_TYPE), + .S_R_REG_TYPE(S_R_REG_TYPE) +) +rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI lite slave interface + */ + .s_axil_rd(s_axil_rd_int), + + /* + * AXI lite master interfaces + */ + .m_axil_rd(m_axil_rd) +); + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axil_crossbar_1s_wr.f b/src/axi/rtl/taxi_axil_crossbar_1s_wr.f new file mode 100644 index 0000000..7305d8f --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_1s_wr.f @@ -0,0 +1,3 @@ +taxi_axil_crossbar_1s_wr.sv +taxi_axil_crossbar_wr.f +taxi_axil_tie_wr.sv diff --git a/src/axi/rtl/taxi_axil_crossbar_1s_wr.sv b/src/axi/rtl/taxi_axil_crossbar_1s_wr.sv new file mode 100644 index 0000000..823b5dd --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_1s_wr.sv @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite crossbar + */ +module taxi_axil_crossbar_1s_wr # +( + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of concurrent operations for each slave interface + // 1 concatenated fields of 32 bits + parameter S_ACCEPT = 32'd16, + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Number of concurrent operations for each master interface + // M_COUNT concatenated fields of 32 bits + parameter M_ISSUE = {M_COUNT{32'd16}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}}, + // Slave interface AW channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AW_REG_TYPE = 2'd0, + // Slave interface W channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_W_REG_TYPE = 2'd0, + // Slave interface B channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_B_REG_TYPE = 2'd1, + // Master interface AW channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface W channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, + // Master interface B channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_B_REG_TYPE = {M_COUNT{2'd0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-lite slave interface + */ + taxi_axil_if.wr_slv s_axil_wr, + + /* + * AXI4-lite master interfaces + */ + taxi_axil_if.wr_mst m_axil_wr[M_COUNT] +); + +taxi_axil_if #( + .DATA_W(s_axil_wr.DATA_W), + .ADDR_W(s_axil_wr.ADDR_W), + .STRB_W(s_axil_wr.STRB_W), + .AWUSER_EN(s_axil_wr.AWUSER_EN), + .AWUSER_W(s_axil_wr.AWUSER_W), + .WUSER_EN(s_axil_wr.WUSER_EN), + .WUSER_W(s_axil_wr.WUSER_W), + .BUSER_EN(s_axil_wr.BUSER_EN), + .BUSER_W(s_axil_wr.BUSER_W), + .ARUSER_EN(s_axil_wr.ARUSER_EN), + .ARUSER_W(s_axil_wr.ARUSER_W), + .RUSER_EN(s_axil_wr.RUSER_EN), + .RUSER_W(s_axil_wr.RUSER_W) +) +s_axil_wr_int[1](); + +taxi_axil_tie_wr +tie_inst ( + .s_axil_wr(s_axil_wr), + .m_axil_wr(s_axil_wr_int[0]) +); + +taxi_axil_crossbar_wr #( + .S_COUNT(1), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AW_REG_TYPE(S_AW_REG_TYPE), + .S_W_REG_TYPE(S_W_REG_TYPE), + .S_B_REG_TYPE(S_B_REG_TYPE) +) +wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI lite slave interface + */ + .s_axil_wr(s_axil_wr_int), + + /* + * AXI lite master interfaces + */ + .m_axil_wr(m_axil_wr) +); + +endmodule + +`resetall diff --git a/src/axi/tb/taxi_axil_crossbar_1s/Makefile b/src/axi/tb/taxi_axil_crossbar_1s/Makefile new file mode 100644 index 0000000..3873314 --- /dev/null +++ b/src/axi/tb/taxi_axil_crossbar_1s/Makefile @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_axil_crossbar_1s +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_M_COUNT := 4 +export PARAM_DATA_W := 32 +export PARAM_ADDR_W := 32 +export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_AWUSER_EN := 0 +export PARAM_AWUSER_W := 1 +export PARAM_WUSER_EN := 0 +export PARAM_WUSER_W := 1 +export PARAM_BUSER_EN := 0 +export PARAM_BUSER_W := 1 +export PARAM_ARUSER_EN := 0 +export PARAM_ARUSER_W := 1 +export PARAM_RUSER_EN := 0 +export PARAM_RUSER_W := 1 +export PARAM_M_REGIONS := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.py b/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.py new file mode 100644 index 0000000..2c43574 --- /dev/null +++ b/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.py @@ -0,0 +1,254 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst) + self.axil_ram = [AxiLiteRam(AxiLiteBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axil] + + def set_idle_generator(self, generator=None): + if generator: + self.axil_master.write_if.aw_channel.set_pause_generator(generator()) + self.axil_master.write_if.w_channel.set_pause_generator(generator()) + self.axil_master.read_if.ar_channel.set_pause_generator(generator()) + for ram in self.axil_ram: + ram.write_if.b_channel.set_pause_generator(generator()) + ram.read_if.r_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.axil_master.write_if.b_channel.set_pause_generator(generator()) + self.axil_master.read_if.r_channel.set_pause_generator(generator()) + for ram in self.axil_ram: + ram.write_if.aw_channel.set_pause_generator(generator()) + ram.write_if.w_channel.set_pause_generator(generator()) + ram.read_if.ar_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + ram_addr = offset+0x1000 + addr = ram_addr + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axil_ram[m].write(ram_addr-128, b'\xaa'*(length+256)) + + await tb.axil_master.write(addr, test_data) + + tb.log.debug("%s", tb.axil_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48)) + + assert tb.axil_ram[m].read(ram_addr, length) == test_data + assert tb.axil_ram[m].read(ram_addr-1, 1) == b'\xaa' + assert tb.axil_ram[m].read(ram_addr+length, 1) == b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + ram_addr = offset+0x1000 + addr = ram_addr + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axil_ram[m].write(ram_addr, test_data) + + data = await tb.axil_master.read(addr, length) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + m = random.randrange(len(tb.axil_ram)) + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if getattr(cocotb, 'top', None) is not None: + + m_count = len(cocotb.top.m_axil) + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.add_option("m", range(min(m_count, 2))) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("data_w", [8, 16, 32]) +@pytest.mark.parametrize("m_count", [1, 4]) +def test_taxi_axil_crossbar_1s(request, m_count, data_w): + dut = "taxi_axil_crossbar_1s" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['M_COUNT'] = m_count + parameters['DATA_W'] = data_w + parameters['ADDR_W'] = 32 + parameters['STRB_W'] = parameters['DATA_W'] // 8 + parameters['AWUSER_EN'] = 0 + parameters['AWUSER_W'] = 1 + parameters['WUSER_EN'] = 0 + parameters['WUSER_W'] = 1 + parameters['BUSER_EN'] = 0 + parameters['BUSER_W'] = 1 + parameters['ARUSER_EN'] = 0 + parameters['ARUSER_W'] = 1 + parameters['RUSER_EN'] = 0 + parameters['RUSER_W'] = 1 + parameters['M_REGIONS'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.sv b/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.sv new file mode 100644 index 0000000..6762698 --- /dev/null +++ b/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.sv @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-lite crossbar testbench + */ +module test_taxi_axil_crossbar_1s # +( + /* verilator lint_off WIDTHTRUNC */ + parameter M_COUNT = 4, + parameter DATA_W = 32, + parameter ADDR_W = 32, + parameter STRB_W = (DATA_W/8), + parameter logic AWUSER_EN = 1'b0, + parameter AWUSER_W = 1, + parameter logic WUSER_EN = 1'b0, + parameter WUSER_W = 1, + parameter logic BUSER_EN = 1'b0, + parameter BUSER_W = 1, + parameter logic ARUSER_EN = 1'b0, + parameter ARUSER_W = 1, + parameter logic RUSER_EN = 1'b0, + parameter RUSER_W = 1, + parameter S_ACCEPT = 16, + parameter M_REGIONS = 1, + parameter M_BASE_ADDR = '0, + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + parameter M_ISSUE = {M_COUNT{32'd4}}, + parameter M_SECURE = {M_COUNT{1'b0}}, + parameter S_AW_REG_TYPE = 2'd0, + parameter S_W_REG_TYPE = 2'd0, + parameter S_B_REG_TYPE = 2'd1, + parameter S_AR_REG_TYPE = 2'd0, + parameter S_R_REG_TYPE = 2'd2, + parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, + parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, + parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, + parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, + parameter M_R_REG_TYPE = {M_COUNT{2'd0}} + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axil_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) s_axil(); + +taxi_axil_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) m_axil[M_COUNT](); + +taxi_axil_crossbar_1s #( + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AW_REG_TYPE(S_AW_REG_TYPE), + .S_W_REG_TYPE(S_W_REG_TYPE), + .S_B_REG_TYPE(S_B_REG_TYPE), + .S_AR_REG_TYPE(S_AR_REG_TYPE), + .S_R_REG_TYPE(S_R_REG_TYPE), + .M_AW_REG_TYPE(M_AW_REG_TYPE), + .M_W_REG_TYPE(M_W_REG_TYPE), + .M_B_REG_TYPE(M_B_REG_TYPE), + .M_AR_REG_TYPE(M_AR_REG_TYPE), + .M_R_REG_TYPE(M_R_REG_TYPE) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4-lite slave interface + */ + .s_axil_wr(s_axil), + .s_axil_rd(s_axil), + + /* + * AXI4-lite master interface + */ + .m_axil_wr(m_axil), + .m_axil_rd(m_axil) +); + +endmodule + +`resetall