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eth: Enable tuser signal in example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-11-06 17:44:50 -08:00
parent 434f31887e
commit 9009880073
19 changed files with 54 additions and 54 deletions
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4
src/eth/example/Alveo/fpga/rtl/fpga_core.sv
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@@ -231,12 +231,12 @@ assign eth_port_lpmode = '0;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
wire eth_gty_rx_status[GTY_CNT];