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eth: Add MAC statistics module to 10G MAC+PCS

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-09 12:18:42 -07:00
parent ddf1b37f4e
commit 93d9c8c9f6
11 changed files with 621 additions and 116 deletions
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82
rtl/eth/taxi_eth_mac_phy_10g_fifo.sv
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@@ -33,6 +33,11 @@ module taxi_eth_mac_phy_10g_fifo #
parameter BITSLIP_HIGH_CYCLES = 0,
parameter BITSLIP_LOW_CYCLES = 7,
parameter COUNT_125US = 125000/6.4,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = 1,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -77,6 +82,19 @@ module taxi_eth_mac_phy_10g_fifo #
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
/*
* PTP clock
*/
input wire logic [PTP_TS_W-1:0] ptp_ts = '0,
input wire logic ptp_ts_step = 1'b0,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
@@ -95,17 +113,13 @@ module taxi_eth_mac_phy_10g_fifo #
output wire logic rx_fifo_bad_frame,
output wire logic rx_fifo_good_frame,
/*
* PTP clock
*/
input wire logic [PTP_TS_W-1:0] ptp_ts = '0,
input wire logic ptp_ts_step = 1'b0,
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1,
input wire logic cfg_tx_prbs31_enable = 1'b0,
input wire logic cfg_rx_prbs31_enable = 1'b0
@@ -254,6 +268,8 @@ end else begin
end
wire stat_rx_fifo_drop;
taxi_eth_mac_phy_10g #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
@@ -270,7 +286,12 @@ taxi_eth_mac_phy_10g #(
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
.COUNT_125US(COUNT_125US),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_phy_10g_inst (
.tx_clk(tx_clk),
@@ -330,20 +351,49 @@ eth_mac_phy_10g_inst (
.tx_pause_req(0),
.tx_pause_ack(),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(),
.tx_error_underflow(tx_error_underflow_int),
.stat_tx_byte(),
.stat_tx_pkt_len(),
.stat_tx_pkt_ucast(),
.stat_tx_pkt_mcast(),
.stat_tx_pkt_bcast(),
.stat_tx_pkt_vlan(),
.stat_tx_pkt_good(),
.stat_tx_pkt_bad(),
.stat_tx_err_oversize(),
.stat_tx_err_user(),
.stat_tx_err_underflow(tx_error_underflow_int),
.rx_start_packet(),
.rx_error_count(),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.rx_bad_block(rx_bad_block_int),
.rx_sequence_error(rx_sequence_error_int),
.rx_block_lock(rx_block_lock_int),
.rx_high_ber(rx_high_ber_int),
.rx_status(rx_status_int),
.stat_rx_byte(),
.stat_rx_pkt_len(),
.stat_rx_pkt_fragment(),
.stat_rx_pkt_jabber(),
.stat_rx_pkt_ucast(),
.stat_rx_pkt_mcast(),
.stat_rx_pkt_bcast(),
.stat_rx_pkt_vlan(),
.stat_rx_pkt_good(),
.stat_rx_pkt_bad(rx_error_bad_frame_int),
.stat_rx_err_oversize(),
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_err_bad_block(rx_bad_block_int),
.stat_rx_err_framing(rx_sequence_error_int),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -366,8 +416,10 @@ eth_mac_phy_10g_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
@@ -532,7 +584,7 @@ rx_fifo (
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_overflow(stat_rx_fifo_drop),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),